src/mem/protocol/MOESI_CMP_directory-msg.sm

   1 /*
   2  * Copyright (c) 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /*
  42  * $Id$
  43  *
  44  */
  45
  46 // CoherenceRequestType
  47 enumeration(CoherenceRequestType, desc="...") {
  48   GETX,      desc="Get eXclusive";
  49   GETS,      desc="Get Shared";
  50   PUTX,      desc="Put eXclusive";
  51   PUTO,      desc="Put Owned";
  52   PUTO_SHARERS,      desc="Put Owned, but sharers exist so don't remove from sharers list";
  53   PUTS,      desc="Put Shared";
  54   INV,       desc="Invalidation";
  55   WRITEBACK_CLEAN_DATA,   desc="Clean writeback (contains data)";
  56   WRITEBACK_CLEAN_ACK,    desc="Clean writeback (contains no data)";
  57   WRITEBACK_DIRTY_DATA,   desc="Dirty writeback (contains data)";
  58   DMA_READ,  desc="DMA Read";
  59   DMA_WRITE, desc="DMA Write";
  60 }
  61
  62 // CoherenceResponseType
  63 enumeration(CoherenceResponseType, desc="...") {
  64   ACK,               desc="ACKnowledgment, responder doesn't have a copy";
  65   DATA,              desc="Data";
  66   DATA_EXCLUSIVE,    desc="Data, no processor has a copy";
  67   UNBLOCK,           desc="Unblock";
  68   UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M";
  69   WB_ACK,            desc="Writeback ack";
  70   WB_ACK_DATA,       desc="Writeback ack";
  71   WB_NACK,           desc="Writeback neg. ack";
  72   DMA_ACK,           desc="Ack that a DMA write completed";
  73 }
  74
  75 // TriggerType
  76 enumeration(TriggerType, desc="...") {
  77   ALL_ACKS,            desc="See corresponding event";
  78 }
  79
  80 // TriggerMsg
  81 structure(TriggerMsg, desc="...", interface="Message") {
  82   Addr addr,             desc="Physical address for this request";
  83   TriggerType Type,            desc="Type of trigger";
  84
  85   bool functionalRead(Packet *pkt) {
  86     // Trigger message does not hold data
  87     return false;
  88   }
  89
  90   bool functionalWrite(Packet *pkt) {
  91     // Trigger message does not hold data
  92     return false;
  93   }
  94 }
  95
  96 // RequestMsg (and also forwarded requests)
  97 structure(RequestMsg, desc="...", interface="Message") {
  98   Addr addr,             desc="Physical address for this request";
  99   int Len,                     desc="Length of Request";
 100   CoherenceRequestType Type,   desc="Type of request (GetS, GetX, PutX, etc)";
 101   MachineID Requestor,            desc="Node who initiated the request";
 102   MachineType RequestorMachine,   desc="type of component";
 103   NetDest Destination,             desc="Multicast destination mask";
 104   DataBlock DataBlk,           desc="data for the cache line (DMA WRITE request)";
 105   int Acks,                    desc="How many acks to expect";
 106   MessageSizeType MessageSize, desc="size category of the message";
 107   RubyAccessMode AccessMode,    desc="user/supervisor access type";
 108   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 109
 110   bool functionalRead(Packet *pkt) {
 111     // Read only those messages that contain the data
 112     if (Type == CoherenceRequestType:DMA_READ ||
 113         Type == CoherenceRequestType:DMA_WRITE ||
 114         Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
 115         Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) {
 116         return testAndRead(addr, DataBlk, pkt);
 117     }
 118     return false;
 119   }
 120
 121   bool functionalWrite(Packet *pkt) {
 122     // No check required since all messages are written
 123     return testAndWrite(addr, DataBlk, pkt);
 124   }
 125 }
 126
 127 // ResponseMsg (and also unblock requests)
 128 structure(ResponseMsg, desc="...", interface="Message") {
 129   Addr addr,             desc="Physical address for this request";
 130   CoherenceResponseType Type,  desc="Type of response (Ack, Data, etc)";
 131   MachineID Sender,               desc="Node who sent the data";
 132   MachineType SenderMachine,   desc="type of component sending msg";
 133   NetDest Destination,             desc="Node to whom the data is sent";
 134   DataBlock DataBlk,           desc="data for the cache line";
 135   bool Dirty,                  desc="Is the data dirty (different than memory)?";
 136   int Acks,                    desc="How many acks to expect";
 137   MessageSizeType MessageSize, desc="size category of the message";
 138
 139   bool functionalRead(Packet *pkt) {
 140     // Read only those messages that contain the data
 141     if (Type == CoherenceResponseType:DATA ||
 142         Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 143         return testAndRead(addr, DataBlk, pkt);
 144     }
 145     return false;
 146   }
 147
 148   bool functionalWrite(Packet *pkt) {
 149     // No check required since all messages are written
 150     return testAndWrite(addr, DataBlk, pkt);
 151   }
 152 }