SCons: Clean up some inconsistent capitalization in scons options.
[gem5.git] / src / mem / protocol / MOESI_CMP_token-L1cache.sm
1
2 /*
3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * $Id: MOESI_CMP_token-L1cache.sm 1.22 05/01/19 15:55:39-06:00 beckmann@s0-28.cs.wisc.edu $
32 *
33 */
34
35 machine(L1Cache, "Token protocol")
36 : Sequencer * sequencer,
37 CacheMemory * L1IcacheMemory,
38 CacheMemory * L1DcacheMemory,
39 int l2_select_num_bits,
40 int N_tokens,
41 int l1_request_latency = 2,
42 int l1_response_latency = 2,
43 int retry_threshold = 1,
44 int fixed_timeout_latency = 100,
45 bool dynamic_timeout_enabled = true,
46 bool no_mig_atomic = true
47 {
48
49 // From this node's L1 cache TO the network
50
51 // a local L1 -> this L2 bank
52 MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false";
53 MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true";
54 // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
55 MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false";
56
57
58 // To this node's L1 cache FROM the network
59 // a L2 bank -> this L1
60 MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false";
61 MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true";
62 // a L2 bank -> this L1
63 MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
64
65 // STATES
66 state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
67 // Base states
68 NP, AccessPermission:Invalid, "NP", desc="Not Present";
69 I, AccessPermission:Invalid, "I", desc="Idle";
70 S, AccessPermission:Read_Only, "S", desc="Shared";
71 O, AccessPermission:Read_Only, "O", desc="Owned";
72 M, AccessPermission:Read_Only, "M", desc="Modified (dirty)";
73 MM, AccessPermission:Read_Write, "MM", desc="Modified (dirty and locally modified)";
74 M_W, AccessPermission:Read_Only, "M^W", desc="Modified (dirty), waiting";
75 MM_W, AccessPermission:Read_Write, "MM^W", desc="Modified (dirty and locally modified), waiting";
76
77 // Transient States
78 IM, AccessPermission:Busy, "IM", desc="Issued GetX";
79 SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have an old copy of the line";
80 OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
81 IS, AccessPermission:Busy, "IS", desc="Issued GetS";
82
83 // Locked states
84 I_L, AccessPermission:Busy, "I^L", desc="Invalid, Locked";
85 S_L, AccessPermission:Busy, "S^L", desc="Shared, Locked";
86 IM_L, AccessPermission:Busy, "IM^L", desc="Invalid, Locked, trying to go to Modified";
87 SM_L, AccessPermission:Busy, "SM^L", desc="Shared, Locked, trying to go to Modified";
88 IS_L, AccessPermission:Busy, "IS^L", desc="Invalid, Locked, trying to go to Shared";
89 }
90
91 // EVENTS
92 enumeration(Event, desc="Cache events") {
93 Load, desc="Load request from the processor";
94 Ifetch, desc="I-fetch request from the processor";
95 Store, desc="Store request from the processor";
96 Atomic, desc="Atomic request from the processor";
97 L1_Replacement, desc="L1 Replacement";
98
99 // Responses
100 Data_Shared, desc="Received a data message, we are now a sharer";
101 Data_Owner, desc="Received a data message, we are now the owner";
102 Data_All_Tokens, desc="Received a data message, we are now the owner, we now have all the tokens";
103 Ack, desc="Received an ack message";
104 Ack_All_Tokens, desc="Received an ack message, we now have all the tokens";
105
106 // Requests
107 Transient_GETX, desc="A GetX from another processor";
108 Transient_Local_GETX, desc="A GetX from another processor";
109 Transient_GETS, desc="A GetS from another processor";
110 Transient_Local_GETS, desc="A GetS from another processor";
111 Transient_GETS_Last_Token, desc="A GetS from another processor";
112 Transient_Local_GETS_Last_Token, desc="A GetS from another processor";
113
114 // Lock/Unlock for distributed
115 Persistent_GETX, desc="Another processor has priority to read/write";
116 Persistent_GETS, desc="Another processor has priority to read";
117 Persistent_GETS_Last_Token, desc="Another processor has priority to read, no more tokens";
118 Own_Lock_or_Unlock, desc="This processor now has priority";
119
120 // Triggers
121 Request_Timeout, desc="Timeout";
122 Use_TimeoutStarverX, desc="Timeout";
123 Use_TimeoutStarverS, desc="Timeout";
124 Use_TimeoutNoStarvers, desc="Timeout";
125 Use_TimeoutNoStarvers_NoMig, desc="Timeout Don't Migrate";
126 }
127
128 // TYPES
129
130 // CacheEntry
131 structure(Entry, desc="...", interface="AbstractCacheEntry") {
132 State CacheState, desc="cache state";
133 bool Dirty, desc="Is the data dirty (different than memory)?";
134 int Tokens, desc="The number of tokens we're holding for the line";
135 DataBlock DataBlk, desc="data for the block";
136 }
137
138
139 // TBE fields
140 structure(TBE, desc="...") {
141 Address Address, desc="Physical address for this TBE";
142 State TBEState, desc="Transient state";
143 int IssueCount, default="0", desc="The number of times we've issued a request for this line.";
144 Address PC, desc="Program counter of request";
145
146 bool WentPersistent, default="false", desc="Request went persistent";
147 bool ExternalResponse, default="false", desc="Response came from an external controller";
148 bool IsAtomic, default="false", desc="Request was an atomic request";
149
150 AccessType AccessType, desc="Type of request (used for profiling)";
151 Time IssueTime, desc="Time the request was issued";
152 AccessModeType AccessMode, desc="user/supervisor access type";
153 PrefetchBit Prefetch, desc="Is this a prefetch request";
154 }
155
156 external_type(TBETable) {
157 TBE lookup(Address);
158 void allocate(Address);
159 void deallocate(Address);
160 bool isPresent(Address);
161 }
162
163 external_type(PersistentTable) {
164 void persistentRequestLock(Address, MachineID, AccessType);
165 void persistentRequestUnlock(Address, MachineID);
166 bool okToIssueStarving(Address, MachineID);
167 MachineID findSmallest(Address);
168 AccessType typeOfSmallest(Address);
169 void markEntries(Address);
170 bool isLocked(Address);
171 int countStarvingForAddress(Address);
172 int countReadStarvingForAddress(Address);
173 }
174
175 void set_cache_entry(AbstractCacheEntry b);
176 void unset_cache_entry();
177 void set_tbe(TBE b);
178 void unset_tbe();
179
180 TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
181
182 MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
183
184 bool starving, default="false";
185 int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
186
187 PersistentTable persistentTable;
188 TimerTable useTimerTable;
189 TimerTable reissueTimerTable;
190
191 int outstandingRequests, default="0";
192 int outstandingPersistentRequests, default="0";
193
194 int averageLatencyHysteresis, default="(8)"; // Constant that provides hysteresis for calculated the estimated average
195 int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))";
196
197 int averageLatencyEstimate() {
198 DPRINTF(RubySlicc, "%d\n",
199 (averageLatencyCounter >> averageLatencyHysteresis));
200 //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
201 return averageLatencyCounter >> averageLatencyHysteresis;
202 }
203
204 void updateAverageLatencyEstimate(int latency) {
205 DPRINTF(RubySlicc, "%d\n", latency);
206 assert(latency >= 0);
207
208 // By subtracting the current average and then adding the most
209 // recent sample, we calculate an estimate of the recent average.
210 // If we simply used a running sum and divided by the total number
211 // of entries, the estimate of the average would adapt very slowly
212 // after the execution has run for a long time.
213 // averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
214
215 averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
216 }
217
218 Entry getCacheEntry(Address addr), return_by_pointer="yes" {
219 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
220 if(is_valid(L1Dcache_entry)) {
221 return L1Dcache_entry;
222 }
223
224 Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
225 return L1Icache_entry;
226 }
227
228 Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
229 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
230 return L1Dcache_entry;
231 }
232
233 Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
234 Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
235 return L1Icache_entry;
236 }
237
238 int getTokens(Entry cache_entry) {
239 if (is_valid(cache_entry)) {
240 return cache_entry.Tokens;
241 }
242 return 0;
243 }
244
245 State getState(TBE tbe, Entry cache_entry, Address addr) {
246
247 if (is_valid(tbe)) {
248 return tbe.TBEState;
249 } else if (is_valid(cache_entry)) {
250 return cache_entry.CacheState;
251 } else {
252 if ((persistentTable.isLocked(addr) == true) && (persistentTable.findSmallest(addr) != machineID)) {
253 // Not in cache, in persistent table, but this processor isn't highest priority
254 return State:I_L;
255 } else {
256 return State:NP;
257 }
258 }
259 }
260
261 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
262 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
263
264 if (is_valid(tbe)) {
265 assert(state != State:I);
266 assert(state != State:S);
267 assert(state != State:O);
268 assert(state != State:MM);
269 assert(state != State:M);
270 tbe.TBEState := state;
271 }
272
273 if (is_valid(cache_entry)) {
274 // Make sure the token count is in range
275 assert(cache_entry.Tokens >= 0);
276 assert(cache_entry.Tokens <= max_tokens());
277 assert(cache_entry.Tokens != (max_tokens() / 2));
278
279 if ((state == State:I_L) ||
280 (state == State:IM_L) ||
281 (state == State:IS_L)) {
282 // Make sure we have no tokens in the "Invalid, locked" states
283 assert(cache_entry.Tokens == 0);
284
285 // Make sure the line is locked
286 // assert(persistentTable.isLocked(addr));
287
288 // But we shouldn't have highest priority for it
289 // assert(persistentTable.findSmallest(addr) != id);
290
291 } else if ((state == State:S_L) ||
292 (state == State:SM_L)) {
293 assert(cache_entry.Tokens >= 1);
294 assert(cache_entry.Tokens < (max_tokens() / 2));
295
296 // Make sure the line is locked...
297 // assert(persistentTable.isLocked(addr));
298
299 // ...But we shouldn't have highest priority for it...
300 // assert(persistentTable.findSmallest(addr) != id);
301
302 // ...And it must be a GETS request
303 // assert(persistentTable.typeOfSmallest(addr) == AccessType:Read);
304
305 } else {
306
307 // If there is an entry in the persistent table of this block,
308 // this processor needs to have an entry in the table for this
309 // block, and that entry better be the smallest (highest
310 // priority). Otherwise, the state should have been one of
311 // locked states
312
313 //if (persistentTable.isLocked(addr)) {
314 // assert(persistentTable.findSmallest(addr) == id);
315 //}
316 }
317
318 // in M and E you have all the tokens
319 if (state == State:MM || state == State:M || state == State:MM_W || state == State:M_W) {
320 assert(cache_entry.Tokens == max_tokens());
321 }
322
323 // in NP you have no tokens
324 if (state == State:NP) {
325 assert(cache_entry.Tokens == 0);
326 }
327
328 // You have at least one token in S-like states
329 if (state == State:S || state == State:SM) {
330 assert(cache_entry.Tokens > 0);
331 }
332
333 // You have at least half the token in O-like states
334 if (state == State:O && state == State:OM) {
335 assert(cache_entry.Tokens > (max_tokens() / 2));
336 }
337
338 cache_entry.CacheState := state;
339 }
340 }
341
342 Event mandatory_request_type_to_event(CacheRequestType type) {
343 if (type == CacheRequestType:LD) {
344 return Event:Load;
345 } else if (type == CacheRequestType:IFETCH) {
346 return Event:Ifetch;
347 } else if (type == CacheRequestType:ST) {
348 return Event:Store;
349 } else if (type == CacheRequestType:ATOMIC) {
350 if (no_mig_atomic) {
351 return Event:Atomic;
352 } else {
353 return Event:Store;
354 }
355 } else {
356 error("Invalid CacheRequestType");
357 }
358 }
359
360 AccessType cache_request_type_to_access_type(CacheRequestType type) {
361 if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) {
362 return AccessType:Read;
363 } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
364 return AccessType:Write;
365 } else {
366 error("Invalid CacheRequestType");
367 }
368 }
369
370 GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
371 if (machineIDToMachineType(sender) == MachineType:L1Cache) {
372 //
373 // NOTE direct local hits should not call this
374 //
375 return GenericMachineType:L1Cache_wCC;
376 } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
377
378 if (sender == (mapAddressToRange(addr,
379 MachineType:L2Cache,
380 l2_select_low_bit,
381 l2_select_num_bits))) {
382
383 return GenericMachineType:L2Cache;
384 } else {
385 return GenericMachineType:L2Cache_wCC;
386 }
387 } else {
388 return ConvertMachToGenericMach(machineIDToMachineType(sender));
389 }
390 }
391
392 bool okToIssueStarving(Address addr, MachineID machinID) {
393 return persistentTable.okToIssueStarving(addr, machineID);
394 }
395
396 void markPersistentEntries(Address addr) {
397 persistentTable.markEntries(addr);
398 }
399
400 void setExternalResponse(TBE tbe) {
401 assert(is_valid(tbe));
402 tbe.ExternalResponse := true;
403 }
404
405 bool IsAtomic(TBE tbe) {
406 assert(is_valid(tbe));
407 return tbe.IsAtomic;
408 }
409
410 // ** OUT_PORTS **
411 out_port(persistentNetwork_out, PersistentMsg, persistentFromL1Cache);
412 out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
413 out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
414 out_port(requestRecycle_out, RequestMsg, requestToL1Cache);
415
416 // ** IN_PORTS **
417
418 // Use Timer
419 in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
420 if (useTimerTable_in.isReady()) {
421 TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
422
423 if (persistentTable.isLocked(useTimerTable.readyAddress()) &&
424 (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
425 if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
426 trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress(),
427 getCacheEntry(useTimerTable.readyAddress()), tbe);
428 } else {
429 trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress(),
430 getCacheEntry(useTimerTable.readyAddress()), tbe);
431 }
432 } else {
433 if (no_mig_atomic && IsAtomic(tbe)) {
434 trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress(),
435 getCacheEntry(useTimerTable.readyAddress()), tbe);
436 } else {
437 trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress(),
438 getCacheEntry(useTimerTable.readyAddress()), tbe);
439 }
440 }
441 }
442 }
443
444 // Reissue Timer
445 in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
446 if (reissueTimerTable_in.isReady()) {
447 trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
448 getCacheEntry(reissueTimerTable.readyAddress()),
449 L1_TBEs[reissueTimerTable.readyAddress()]);
450 }
451 }
452
453 // Persistent Network
454 in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
455 if (persistentNetwork_in.isReady()) {
456 peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
457 assert(in_msg.Destination.isElement(machineID));
458
459 // Apply the lockdown or unlockdown message to the table
460 if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
461 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
462 } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
463 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
464 } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
465 persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
466 } else {
467 error("Unexpected message");
468 }
469
470 // React to the message based on the current state of the table
471 Entry cache_entry := getCacheEntry(in_msg.Address);
472 TBE tbe := L1_TBEs[in_msg.Address];
473
474 if (persistentTable.isLocked(in_msg.Address)) {
475 if (persistentTable.findSmallest(in_msg.Address) == machineID) {
476 // Our Own Lock - this processor is highest priority
477 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
478 cache_entry, tbe);
479 } else {
480 if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
481 if (getTokens(cache_entry) == 1 ||
482 getTokens(cache_entry) == (max_tokens() / 2) + 1) {
483 trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
484 cache_entry, tbe);
485 } else {
486 trigger(Event:Persistent_GETS, in_msg.Address,
487 cache_entry, tbe);
488 }
489 } else {
490 trigger(Event:Persistent_GETX, in_msg.Address,
491 cache_entry, tbe);
492 }
493 }
494 } else {
495 // Unlock case - no entries in the table
496 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
497 cache_entry, tbe);
498 }
499 }
500 }
501 }
502
503 // Response Network
504 in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
505 if (responseNetwork_in.isReady()) {
506 peek(responseNetwork_in, ResponseMsg, block_on="Address") {
507 assert(in_msg.Destination.isElement(machineID));
508
509 Entry cache_entry := getCacheEntry(in_msg.Address);
510 TBE tbe := L1_TBEs[in_msg.Address];
511
512 // Mark TBE flag if response received off-chip. Use this to update average latency estimate
513 if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
514
515 if (in_msg.Sender == mapAddressToRange(in_msg.Address,
516 MachineType:L2Cache,
517 l2_select_low_bit,
518 l2_select_num_bits)) {
519
520 // came from an off-chip L2 cache
521 if (is_valid(tbe)) {
522 // L1_TBEs[in_msg.Address].ExternalResponse := true;
523 // profile_offchipL2_response(in_msg.Address);
524 }
525 }
526 else {
527 // profile_onchipL2_response(in_msg.Address );
528 }
529 } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
530 if (is_valid(tbe)) {
531 setExternalResponse(tbe);
532 // profile_memory_response( in_msg.Address);
533 }
534 } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
535 //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
536 //if (is_valid(tbe)) {
537 // tbe.ExternalResponse := true;
538 // profile_offchipL1_response(in_msg.Address );
539 //}
540 //}
541 //else {
542 // profile_onchipL1_response(in_msg.Address );
543 //}
544 } else {
545 error("unexpected SenderMachine");
546 }
547
548
549 if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
550 if (in_msg.Type == CoherenceResponseType:ACK) {
551 assert(in_msg.Tokens < (max_tokens() / 2));
552 trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
553 } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
554 trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
555 } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
556 assert(in_msg.Tokens < (max_tokens() / 2));
557 trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
558 } else {
559 error("Unexpected message");
560 }
561 } else {
562 if (in_msg.Type == CoherenceResponseType:ACK) {
563 assert(in_msg.Tokens < (max_tokens() / 2));
564 trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
565 } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
566 trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
567 } else {
568 error("Unexpected message");
569 }
570 }
571 }
572 }
573 }
574
575 // Request Network
576 in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
577 if (requestNetwork_in.isReady()) {
578 peek(requestNetwork_in, RequestMsg, block_on="Address") {
579 assert(in_msg.Destination.isElement(machineID));
580
581 Entry cache_entry := getCacheEntry(in_msg.Address);
582 TBE tbe := L1_TBEs[in_msg.Address];
583
584 if (in_msg.Type == CoherenceRequestType:GETX) {
585 if (in_msg.isLocal) {
586 trigger(Event:Transient_Local_GETX, in_msg.Address,
587 cache_entry, tbe);
588 }
589 else {
590 trigger(Event:Transient_GETX, in_msg.Address,
591 cache_entry, tbe);
592 }
593 } else if (in_msg.Type == CoherenceRequestType:GETS) {
594 if (getTokens(cache_entry) == 1 ||
595 getTokens(cache_entry) == (max_tokens() / 2) + 1) {
596 if (in_msg.isLocal) {
597 trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
598 cache_entry, tbe);
599 }
600 else {
601 trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
602 cache_entry, tbe);
603 }
604 }
605 else {
606 if (in_msg.isLocal) {
607 trigger(Event:Transient_Local_GETS, in_msg.Address,
608 cache_entry, tbe);
609 }
610 else {
611 trigger(Event:Transient_GETS, in_msg.Address,
612 cache_entry, tbe);
613 }
614 }
615 } else {
616 error("Unexpected message");
617 }
618 }
619 }
620 }
621
622 // Mandatory Queue
623 in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
624 if (mandatoryQueue_in.isReady()) {
625 peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
626 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
627
628 TBE tbe := L1_TBEs[in_msg.LineAddress];
629
630 if (in_msg.Type == CacheRequestType:IFETCH) {
631 // ** INSTRUCTION ACCESS ***
632
633 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
634 if (is_valid(L1Icache_entry)) {
635 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
636 trigger(mandatory_request_type_to_event(in_msg.Type),
637 in_msg.LineAddress, L1Icache_entry, tbe);
638 } else {
639
640 // Check to see if it is in the OTHER L1
641 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
642 if (is_valid(L1Dcache_entry)) {
643 // The block is in the wrong L1, try to write it to the L2
644 trigger(Event:L1_Replacement, in_msg.LineAddress,
645 L1Dcache_entry, tbe);
646 }
647
648 if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
649 // L1 does't have the line, but we have space for it in the L1
650 trigger(mandatory_request_type_to_event(in_msg.Type),
651 in_msg.LineAddress, L1Icache_entry, tbe);
652 } else {
653 // No room in the L1, so we need to make room
654 trigger(Event:L1_Replacement,
655 L1IcacheMemory.cacheProbe(in_msg.LineAddress),
656 getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
657 L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
658 }
659 }
660 } else {
661 // *** DATA ACCESS ***
662
663 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
664 if (is_valid(L1Dcache_entry)) {
665 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
666 trigger(mandatory_request_type_to_event(in_msg.Type),
667 in_msg.LineAddress, L1Dcache_entry, tbe);
668 } else {
669
670 // Check to see if it is in the OTHER L1
671 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
672 if (is_valid(L1Icache_entry)) {
673 // The block is in the wrong L1, try to write it to the L2
674 trigger(Event:L1_Replacement, in_msg.LineAddress,
675 L1Icache_entry, tbe);
676 }
677
678 if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
679 // L1 does't have the line, but we have space for it in the L1
680 trigger(mandatory_request_type_to_event(in_msg.Type),
681 in_msg.LineAddress, L1Dcache_entry, tbe);
682 } else {
683 // No room in the L1, so we need to make room
684 trigger(Event:L1_Replacement,
685 L1DcacheMemory.cacheProbe(in_msg.LineAddress),
686 getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
687 L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
688 }
689 }
690 }
691 }
692 }
693 }
694
695 // ACTIONS
696
697 action(a_issueReadRequest, "a", desc="Issue GETS") {
698 assert(is_valid(tbe));
699 if (tbe.IssueCount == 0) {
700 // Update outstanding requests
701 //profile_outstanding_request(outstandingRequests);
702 outstandingRequests := outstandingRequests + 1;
703 }
704
705 if (tbe.IssueCount >= retry_threshold) {
706 // Issue a persistent request if possible
707 if (okToIssueStarving(address, machineID) && (starving == false)) {
708 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
709 out_msg.Address := address;
710 out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
711 out_msg.Requestor := machineID;
712 out_msg.Destination.broadcast(MachineType:L1Cache);
713
714 //
715 // Currently the configuration system limits the system to only one
716 // chip. Therefore, if we assume one shared L2 cache, then only one
717 // pertinent L2 cache exist.
718 //
719 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
720
721 out_msg.Destination.add(mapAddressToRange(address,
722 MachineType:L2Cache,
723 l2_select_low_bit,
724 l2_select_num_bits));
725
726 out_msg.Destination.add(map_Address_to_Directory(address));
727 out_msg.MessageSize := MessageSizeType:Persistent_Control;
728 out_msg.Prefetch := tbe.Prefetch;
729 out_msg.AccessMode := tbe.AccessMode;
730 }
731 markPersistentEntries(address);
732 starving := true;
733
734 if (tbe.IssueCount == 0) {
735 //profile_persistent_prediction(address, tbe.AccessType);
736 }
737
738 // Update outstanding requests
739 //profile_outstanding_persistent_request(outstandingPersistentRequests);
740 outstandingPersistentRequests := outstandingPersistentRequests + 1;
741
742 // Increment IssueCount
743 tbe.IssueCount := tbe.IssueCount + 1;
744
745 tbe.WentPersistent := true;
746
747 // Do not schedule a wakeup, a persistent requests will always complete
748 }
749 else {
750
751 // We'd like to issue a persistent request, but are not allowed
752 // to issue a P.R. right now. This, we do not increment the
753 // IssueCount.
754
755 // Set a wakeup timer
756 reissueTimerTable.set(address, 10);
757
758 }
759 } else {
760 // Make a normal request
761 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
762 out_msg.Address := address;
763 out_msg.Type := CoherenceRequestType:GETS;
764 out_msg.Requestor := machineID;
765 out_msg.Destination.add(mapAddressToRange(address,
766 MachineType:L2Cache,
767 l2_select_low_bit,
768 l2_select_num_bits));
769
770 out_msg.RetryNum := tbe.IssueCount;
771 if (tbe.IssueCount == 0) {
772 out_msg.MessageSize := MessageSizeType:Request_Control;
773 } else {
774 out_msg.MessageSize := MessageSizeType:Reissue_Control;
775 }
776 out_msg.Prefetch := tbe.Prefetch;
777 out_msg.AccessMode := tbe.AccessMode;
778 }
779
780 // send to other local L1s, with local bit set
781 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
782 out_msg.Address := address;
783 out_msg.Type := CoherenceRequestType:GETS;
784 out_msg.Requestor := machineID;
785 //
786 // Since only one chip, assuming all L1 caches are local
787 //
788 //out_msg.Destination := getOtherLocalL1IDs(machineID);
789 out_msg.Destination.broadcast(MachineType:L1Cache);
790 out_msg.Destination.remove(machineID);
791
792 out_msg.RetryNum := tbe.IssueCount;
793 out_msg.isLocal := true;
794 if (tbe.IssueCount == 0) {
795 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
796 } else {
797 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
798 }
799 out_msg.Prefetch := tbe.Prefetch;
800 out_msg.AccessMode := tbe.AccessMode;
801 }
802
803 // Increment IssueCount
804 tbe.IssueCount := tbe.IssueCount + 1;
805
806 // Set a wakeup timer
807
808 if (dynamic_timeout_enabled) {
809 reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
810 } else {
811 reissueTimerTable.set(address, fixed_timeout_latency);
812 }
813
814 }
815 }
816
817 action(b_issueWriteRequest, "b", desc="Issue GETX") {
818
819 assert(is_valid(tbe));
820 if (tbe.IssueCount == 0) {
821 // Update outstanding requests
822 //profile_outstanding_request(outstandingRequests);
823 outstandingRequests := outstandingRequests + 1;
824 }
825
826 if (tbe.IssueCount >= retry_threshold) {
827 // Issue a persistent request if possible
828 if ( okToIssueStarving(address, machineID) && (starving == false)) {
829 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
830 out_msg.Address := address;
831 out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
832 out_msg.Requestor := machineID;
833 out_msg.Destination.broadcast(MachineType:L1Cache);
834
835 //
836 // Currently the configuration system limits the system to only one
837 // chip. Therefore, if we assume one shared L2 cache, then only one
838 // pertinent L2 cache exist.
839 //
840 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
841
842 out_msg.Destination.add(mapAddressToRange(address,
843 MachineType:L2Cache,
844 l2_select_low_bit,
845 l2_select_num_bits));
846
847 out_msg.Destination.add(map_Address_to_Directory(address));
848 out_msg.MessageSize := MessageSizeType:Persistent_Control;
849 out_msg.Prefetch := tbe.Prefetch;
850 out_msg.AccessMode := tbe.AccessMode;
851 }
852 markPersistentEntries(address);
853 starving := true;
854
855 // Update outstanding requests
856 //profile_outstanding_persistent_request(outstandingPersistentRequests);
857 outstandingPersistentRequests := outstandingPersistentRequests + 1;
858
859 if (tbe.IssueCount == 0) {
860 //profile_persistent_prediction(address, tbe.AccessType);
861 }
862
863 // Increment IssueCount
864 tbe.IssueCount := tbe.IssueCount + 1;
865
866 tbe.WentPersistent := true;
867
868 // Do not schedule a wakeup, a persistent requests will always complete
869 }
870 else {
871
872 // We'd like to issue a persistent request, but are not allowed
873 // to issue a P.R. right now. This, we do not increment the
874 // IssueCount.
875
876 // Set a wakeup timer
877 reissueTimerTable.set(address, 10);
878 }
879
880
881 } else {
882 // Make a normal request
883 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
884 out_msg.Address := address;
885 out_msg.Type := CoherenceRequestType:GETX;
886 out_msg.Requestor := machineID;
887
888 out_msg.Destination.add(mapAddressToRange(address,
889 MachineType:L2Cache,
890 l2_select_low_bit,
891 l2_select_num_bits));
892
893 out_msg.RetryNum := tbe.IssueCount;
894
895 if (tbe.IssueCount == 0) {
896 out_msg.MessageSize := MessageSizeType:Request_Control;
897 } else {
898 out_msg.MessageSize := MessageSizeType:Reissue_Control;
899 }
900 out_msg.Prefetch := tbe.Prefetch;
901 out_msg.AccessMode := tbe.AccessMode;
902 }
903
904 // send to other local L1s too
905 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
906 out_msg.Address := address;
907 out_msg.Type := CoherenceRequestType:GETX;
908 out_msg.Requestor := machineID;
909 out_msg.isLocal := true;
910
911 //
912 // Since only one chip, assuming all L1 caches are local
913 //
914 //out_msg.Destination := getOtherLocalL1IDs(machineID);
915 out_msg.Destination.broadcast(MachineType:L1Cache);
916 out_msg.Destination.remove(machineID);
917
918 out_msg.RetryNum := tbe.IssueCount;
919 if (tbe.IssueCount == 0) {
920 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
921 } else {
922 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
923 }
924 out_msg.Prefetch := tbe.Prefetch;
925 out_msg.AccessMode := tbe.AccessMode;
926 }
927
928 // Increment IssueCount
929 tbe.IssueCount := tbe.IssueCount + 1;
930
931 DPRINTF(RubySlicc, "incremented issue count to %d\n",
932 tbe.IssueCount);
933
934 // Set a wakeup timer
935 if (dynamic_timeout_enabled) {
936 reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
937 } else {
938 reissueTimerTable.set(address, fixed_timeout_latency);
939 }
940 }
941 }
942
943 action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") {
944 peek(responseNetwork_in, ResponseMsg) {
945 // FIXME, should use a 3rd vnet
946 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
947 out_msg.Address := address;
948 out_msg.Type := in_msg.Type;
949 out_msg.Sender := machineID;
950 out_msg.Destination.add(map_Address_to_Directory(address));
951 out_msg.Tokens := in_msg.Tokens;
952 out_msg.MessageSize := in_msg.MessageSize;
953 out_msg.DataBlk := in_msg.DataBlk;
954 out_msg.Dirty := in_msg.Dirty;
955 }
956 }
957 }
958
959 action(c_ownedReplacement, "c", desc="Issue writeback") {
960 assert(is_valid(cache_entry));
961 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
962 out_msg.Address := address;
963 out_msg.Sender := machineID;
964
965 out_msg.Destination.add(mapAddressToRange(address,
966 MachineType:L2Cache,
967 l2_select_low_bit,
968 l2_select_num_bits));
969
970 out_msg.Tokens := cache_entry.Tokens;
971 out_msg.DataBlk := cache_entry.DataBlk;
972 out_msg.Dirty := cache_entry.Dirty;
973 out_msg.Type := CoherenceResponseType:WB_OWNED;
974
975 // always send the data?
976 out_msg.MessageSize := MessageSizeType:Writeback_Data;
977 }
978 cache_entry.Tokens := 0;
979 }
980
981 action(cc_sharedReplacement, "\c", desc="Issue shared writeback") {
982
983 // don't send writeback if replacing block with no tokens
984 assert(is_valid(cache_entry));
985 assert (cache_entry.Tokens > 0);
986 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
987 out_msg.Address := address;
988 out_msg.Sender := machineID;
989
990 out_msg.Destination.add(mapAddressToRange(address,
991 MachineType:L2Cache,
992 l2_select_low_bit,
993 l2_select_num_bits));
994
995 out_msg.Tokens := cache_entry.Tokens;
996 out_msg.DataBlk := cache_entry.DataBlk;
997 // assert(cache_entry.Dirty == false);
998 out_msg.Dirty := false;
999
1000 out_msg.MessageSize := MessageSizeType:Writeback_Data;
1001 out_msg.Type := CoherenceResponseType:WB_SHARED_DATA;
1002 }
1003 cache_entry.Tokens := 0;
1004 }
1005
1006 action(tr_tokenReplacement, "tr", desc="Issue token writeback") {
1007 assert(is_valid(cache_entry));
1008 if (cache_entry.Tokens > 0) {
1009 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1010 out_msg.Address := address;
1011 out_msg.Sender := machineID;
1012
1013 out_msg.Destination.add(mapAddressToRange(address,
1014 MachineType:L2Cache,
1015 l2_select_low_bit,
1016 l2_select_num_bits));
1017
1018 out_msg.Tokens := cache_entry.Tokens;
1019 out_msg.DataBlk := cache_entry.DataBlk;
1020 // assert(cache_entry.Dirty == false);
1021 out_msg.Dirty := false;
1022
1023 // always send the data?
1024 out_msg.MessageSize := MessageSizeType:Writeback_Control;
1025 out_msg.Type := CoherenceResponseType:WB_TOKENS;
1026 }
1027 }
1028 cache_entry.Tokens := 0;
1029 }
1030
1031
1032 action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") {
1033 assert(is_valid(cache_entry));
1034 peek(requestNetwork_in, RequestMsg) {
1035 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1036 out_msg.Address := address;
1037 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1038 out_msg.Sender := machineID;
1039 out_msg.Destination.add(in_msg.Requestor);
1040 out_msg.Tokens := 1;
1041 out_msg.DataBlk := cache_entry.DataBlk;
1042 // out_msg.Dirty := cache_entry.Dirty;
1043 out_msg.Dirty := false;
1044 if (in_msg.isLocal) {
1045 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1046 } else {
1047 out_msg.MessageSize := MessageSizeType:Response_Data;
1048 }
1049 }
1050 }
1051 cache_entry.Tokens := cache_entry.Tokens - 1;
1052 assert(cache_entry.Tokens >= 1);
1053 }
1054
1055 action(d_sendDataWithNTokenIfAvail, "\dd", desc="Send data and a token from cache to requestor") {
1056 assert(is_valid(cache_entry));
1057 peek(requestNetwork_in, RequestMsg) {
1058 if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1059 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1060 out_msg.Address := address;
1061 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1062 out_msg.Sender := machineID;
1063 out_msg.Destination.add(in_msg.Requestor);
1064 out_msg.Tokens := N_tokens;
1065 out_msg.DataBlk := cache_entry.DataBlk;
1066 // out_msg.Dirty := cache_entry.Dirty;
1067 out_msg.Dirty := false;
1068 if (in_msg.isLocal) {
1069 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1070 } else {
1071 out_msg.MessageSize := MessageSizeType:Response_Data;
1072 }
1073 }
1074 cache_entry.Tokens := cache_entry.Tokens - N_tokens;
1075 }
1076 else if (cache_entry.Tokens > 1) {
1077 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1078 out_msg.Address := address;
1079 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1080 out_msg.Sender := machineID;
1081 out_msg.Destination.add(in_msg.Requestor);
1082 out_msg.Tokens := 1;
1083 out_msg.DataBlk := cache_entry.DataBlk;
1084 // out_msg.Dirty := cache_entry.Dirty;
1085 out_msg.Dirty := false;
1086 if (in_msg.isLocal) {
1087 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1088 } else {
1089 out_msg.MessageSize := MessageSizeType:Response_Data;
1090 }
1091 }
1092 cache_entry.Tokens := cache_entry.Tokens - 1;
1093 }
1094 }
1095 // assert(cache_entry.Tokens >= 1);
1096 }
1097
1098 action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") {
1099 peek(requestNetwork_in, RequestMsg) {
1100 assert(is_valid(cache_entry));
1101 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1102 out_msg.Address := address;
1103 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1104 out_msg.Sender := machineID;
1105 out_msg.Destination.add(in_msg.Requestor);
1106 assert(cache_entry.Tokens > (max_tokens() / 2));
1107 out_msg.Tokens := cache_entry.Tokens;
1108 out_msg.DataBlk := cache_entry.DataBlk;
1109 out_msg.Dirty := cache_entry.Dirty;
1110 if (in_msg.isLocal) {
1111 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1112 } else {
1113 out_msg.MessageSize := MessageSizeType:Response_Data;
1114 }
1115 }
1116 }
1117 cache_entry.Tokens := 0;
1118 }
1119
1120 action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") {
1121 // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1122 assert(is_valid(cache_entry));
1123 if (cache_entry.Tokens > 0) {
1124 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1125 out_msg.Address := address;
1126 if (cache_entry.Tokens > (max_tokens() / 2)) {
1127 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1128 } else {
1129 out_msg.Type := CoherenceResponseType:ACK;
1130 }
1131 out_msg.Sender := machineID;
1132 out_msg.Destination.add(persistentTable.findSmallest(address));
1133 assert(cache_entry.Tokens >= 1);
1134 out_msg.Tokens := cache_entry.Tokens;
1135 out_msg.DataBlk := cache_entry.DataBlk;
1136 out_msg.MessageSize := MessageSizeType:Response_Control;
1137 }
1138 }
1139 cache_entry.Tokens := 0;
1140 }
1141
1142 action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
1143 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1144 assert(is_valid(cache_entry));
1145 assert(cache_entry.Tokens > 0);
1146 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1147 out_msg.Address := address;
1148 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1149 out_msg.Sender := machineID;
1150 out_msg.Destination.add(persistentTable.findSmallest(address));
1151 assert(cache_entry.Tokens > (max_tokens() / 2));
1152 out_msg.Tokens := cache_entry.Tokens;
1153 out_msg.DataBlk := cache_entry.DataBlk;
1154 out_msg.Dirty := cache_entry.Dirty;
1155 out_msg.MessageSize := MessageSizeType:Response_Data;
1156 }
1157 cache_entry.Tokens := 0;
1158 }
1159
1160 action(f_sendAckWithAllButNorOneTokens, "f", desc="Send ack with all our tokens but one to starver.") {
1161 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1162 assert(is_valid(cache_entry));
1163 assert(cache_entry.Tokens > 0);
1164 if (cache_entry.Tokens > 1) {
1165 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1166 out_msg.Address := address;
1167 if (cache_entry.Tokens > (max_tokens() / 2)) {
1168 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1169 } else {
1170 out_msg.Type := CoherenceResponseType:ACK;
1171 }
1172 out_msg.Sender := machineID;
1173 out_msg.Destination.add(persistentTable.findSmallest(address));
1174 assert(cache_entry.Tokens >= 1);
1175 if (cache_entry.Tokens > N_tokens) {
1176 out_msg.Tokens := cache_entry.Tokens - N_tokens;
1177 } else {
1178 out_msg.Tokens := cache_entry.Tokens - 1;
1179 }
1180 out_msg.DataBlk := cache_entry.DataBlk;
1181 out_msg.MessageSize := MessageSizeType:Response_Control;
1182 }
1183 }
1184 if (cache_entry.Tokens > N_tokens) {
1185 cache_entry.Tokens := N_tokens;
1186 } else {
1187 cache_entry.Tokens := 1;
1188 }
1189 }
1190
1191 action(ff_sendDataWithAllButNorOneTokens, "\f", desc="Send data and out tokens but one to starver") {
1192 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1193 assert(is_valid(cache_entry));
1194 assert(cache_entry.Tokens > ((max_tokens() / 2) + 1));
1195 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1196 out_msg.Address := address;
1197 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1198 out_msg.Sender := machineID;
1199 out_msg.Destination.add(persistentTable.findSmallest(address));
1200 if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1201 out_msg.Tokens := cache_entry.Tokens - N_tokens;
1202 } else {
1203 out_msg.Tokens := cache_entry.Tokens - 1;
1204 }
1205 assert(out_msg.Tokens > (max_tokens() / 2));
1206 out_msg.DataBlk := cache_entry.DataBlk;
1207 out_msg.Dirty := cache_entry.Dirty;
1208 out_msg.MessageSize := MessageSizeType:Response_Data;
1209 }
1210 if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1211 cache_entry.Tokens := N_tokens;
1212 } else {
1213 cache_entry.Tokens := 1;
1214 }
1215 }
1216
1217 action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") {
1218 assert(is_valid(cache_entry));
1219 assert(cache_entry.Tokens == ((max_tokens() / 2) + 1));
1220 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1221 out_msg.Address := address;
1222 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1223 out_msg.Sender := machineID;
1224 out_msg.Destination.add(persistentTable.findSmallest(address));
1225 out_msg.Tokens := cache_entry.Tokens;
1226 assert(out_msg.Tokens > (max_tokens() / 2));
1227 out_msg.DataBlk := cache_entry.DataBlk;
1228 out_msg.Dirty := cache_entry.Dirty;
1229 out_msg.MessageSize := MessageSizeType:Response_Data;
1230 }
1231 cache_entry.Tokens := 0;
1232 }
1233
1234 action(g_bounceResponseToStarver, "g", desc="Redirect response to starving processor") {
1235 // assert(persistentTable.isLocked(address));
1236
1237 peek(responseNetwork_in, ResponseMsg) {
1238 // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1239 // FIXME, should use a 3rd vnet in some cases
1240 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
1241 out_msg.Address := address;
1242 out_msg.Type := in_msg.Type;
1243 out_msg.Sender := machineID;
1244 out_msg.Destination.add(persistentTable.findSmallest(address));
1245 out_msg.Tokens := in_msg.Tokens;
1246 out_msg.DataBlk := in_msg.DataBlk;
1247 out_msg.Dirty := in_msg.Dirty;
1248 out_msg.MessageSize := in_msg.MessageSize;
1249 }
1250 }
1251 }
1252
1253
1254 action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
1255 assert(is_valid(cache_entry));
1256 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1257 address, cache_entry.DataBlk);
1258
1259 sequencer.readCallback(address,
1260 GenericMachineType:L1Cache,
1261 cache_entry.DataBlk);
1262
1263 }
1264
1265 action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
1266 assert(is_valid(cache_entry));
1267 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1268 address, cache_entry.DataBlk);
1269 peek(responseNetwork_in, ResponseMsg) {
1270
1271 sequencer.readCallback(address,
1272 getNondirectHitMachType(address, in_msg.Sender),
1273 cache_entry.DataBlk);
1274
1275 }
1276 }
1277
1278 action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
1279 assert(is_valid(cache_entry));
1280 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1281 address, cache_entry.DataBlk);
1282
1283 sequencer.writeCallback(address,
1284 GenericMachineType:L1Cache,
1285 cache_entry.DataBlk);
1286
1287 cache_entry.Dirty := true;
1288 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1289 }
1290
1291 action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
1292 assert(is_valid(cache_entry));
1293 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1294 address, cache_entry.DataBlk);
1295 peek(responseNetwork_in, ResponseMsg) {
1296
1297 sequencer.writeCallback(address,
1298 getNondirectHitMachType(address, in_msg.Sender),
1299 cache_entry.DataBlk);
1300
1301 }
1302 cache_entry.Dirty := true;
1303 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1304 }
1305
1306 action(i_allocateTBE, "i", desc="Allocate TBE") {
1307 check_allocate(L1_TBEs);
1308 L1_TBEs.allocate(address);
1309 set_tbe(L1_TBEs[address]);
1310 tbe.IssueCount := 0;
1311 peek(mandatoryQueue_in, CacheMsg) {
1312 tbe.PC := in_msg.ProgramCounter;
1313 tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
1314 if (in_msg.Type == CacheRequestType:ATOMIC) {
1315 tbe.IsAtomic := true;
1316 }
1317 tbe.Prefetch := in_msg.Prefetch;
1318 tbe.AccessMode := in_msg.AccessMode;
1319 }
1320 tbe.IssueTime := get_time();
1321 }
1322
1323 action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
1324 peek(mandatoryQueue_in, CacheMsg) {
1325 APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1326 }
1327 }
1328
1329 action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
1330 if (reissueTimerTable.isSet(address)) {
1331 reissueTimerTable.unset(address);
1332 }
1333 }
1334
1335 action(jj_unsetUseTimer, "\j", desc="Unset use timer.") {
1336 useTimerTable.unset(address);
1337 }
1338
1339 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
1340 mandatoryQueue_in.dequeue();
1341 }
1342
1343 action(l_popPersistentQueue, "l", desc="Pop persistent queue.") {
1344 persistentNetwork_in.dequeue();
1345 }
1346
1347 action(m_popRequestQueue, "m", desc="Pop request queue.") {
1348 requestNetwork_in.dequeue();
1349 }
1350
1351 action(n_popResponseQueue, "n", desc="Pop response queue") {
1352 responseNetwork_in.dequeue();
1353 }
1354
1355 action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
1356 useTimerTable.set(address, 50);
1357 }
1358
1359 action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
1360 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1361 out_msg.Address := address;
1362 out_msg.Type := CoherenceResponseType:INV;
1363 out_msg.Tokens := 0;
1364 out_msg.Sender := machineID;
1365
1366 out_msg.Destination.add(mapAddressToRange(address,
1367 MachineType:L2Cache,
1368 l2_select_low_bit,
1369 l2_select_num_bits));
1370
1371 out_msg.MessageSize := MessageSizeType:Response_Control;
1372 }
1373 }
1374
1375
1376 action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
1377 peek(responseNetwork_in, ResponseMsg) {
1378 assert(is_valid(cache_entry));
1379 assert(in_msg.Tokens != 0);
1380 DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
1381 in_msg.Address, in_msg.Tokens);
1382 cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
1383 DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
1384
1385 if (cache_entry.Dirty == false && in_msg.Dirty) {
1386 cache_entry.Dirty := true;
1387 }
1388 }
1389 }
1390
1391 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1392
1393 assert(is_valid(tbe));
1394 if (tbe.WentPersistent) {
1395 // assert(starving == true);
1396 outstandingRequests := outstandingRequests - 1;
1397 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
1398 out_msg.Address := address;
1399 out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
1400 out_msg.Requestor := machineID;
1401 out_msg.Destination.broadcast(MachineType:L1Cache);
1402
1403 //
1404 // Currently the configuration system limits the system to only one
1405 // chip. Therefore, if we assume one shared L2 cache, then only one
1406 // pertinent L2 cache exist.
1407 //
1408 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
1409
1410 out_msg.Destination.add(mapAddressToRange(address,
1411 MachineType:L2Cache,
1412 l2_select_low_bit,
1413 l2_select_num_bits));
1414
1415 out_msg.Destination.add(map_Address_to_Directory(address));
1416 out_msg.MessageSize := MessageSizeType:Persistent_Control;
1417 }
1418 starving := false;
1419 }
1420
1421 // Update average latency
1422 if (tbe.IssueCount <= 1) {
1423 if (tbe.ExternalResponse == true) {
1424 updateAverageLatencyEstimate(time_to_int(get_time()) - time_to_int(tbe.IssueTime));
1425 }
1426 }
1427
1428 // Profile
1429 //if (tbe.WentPersistent) {
1430 // profile_token_retry(address, tbe.AccessType, 2);
1431 //}
1432 //else {
1433 // profile_token_retry(address, tbe.AccessType, 1);
1434 //}
1435
1436 //profile_token_retry(address, tbe.AccessType, tbe.IssueCount);
1437 L1_TBEs.deallocate(address);
1438 unset_tbe();
1439 }
1440
1441 action(t_sendAckWithCollectedTokens, "t", desc="Send ack with the tokens we've collected thus far.") {
1442 assert(is_valid(cache_entry));
1443 if (cache_entry.Tokens > 0) {
1444 peek(requestNetwork_in, RequestMsg) {
1445 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1446 out_msg.Address := address;
1447 if (cache_entry.Tokens > (max_tokens() / 2)) {
1448 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1449 } else {
1450 out_msg.Type := CoherenceResponseType:ACK;
1451 }
1452 out_msg.Sender := machineID;
1453 out_msg.Destination.add(in_msg.Requestor);
1454 assert(cache_entry.Tokens >= 1);
1455 out_msg.Tokens := cache_entry.Tokens;
1456 out_msg.DataBlk := cache_entry.DataBlk;
1457 out_msg.MessageSize := MessageSizeType:Response_Control;
1458 }
1459 }
1460 }
1461 cache_entry.Tokens := 0;
1462 }
1463
1464 action(u_writeDataToCache, "u", desc="Write data to cache") {
1465 peek(responseNetwork_in, ResponseMsg) {
1466 assert(is_valid(cache_entry));
1467 cache_entry.DataBlk := in_msg.DataBlk;
1468 if (cache_entry.Dirty == false && in_msg.Dirty) {
1469 cache_entry.Dirty := in_msg.Dirty;
1470 }
1471
1472 }
1473 }
1474
1475 action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1476 assert(getTokens(cache_entry) == 0);
1477 if (L1DcacheMemory.isTagPresent(address)) {
1478 L1DcacheMemory.deallocate(address);
1479 } else {
1480 L1IcacheMemory.deallocate(address);
1481 }
1482 unset_cache_entry();
1483 }
1484
1485 action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1486 if (is_valid(cache_entry)) {
1487 } else {
1488 set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
1489 }
1490 }
1491
1492 action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
1493 if (is_valid(cache_entry)) {
1494 } else {
1495 set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
1496 }
1497 }
1498
1499 action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1500 peek(mandatoryQueue_in, CacheMsg) {
1501 if (L1DcacheMemory.isTagPresent(address)) {
1502 L1DcacheMemory.profileMiss(in_msg);
1503 } else {
1504 L1IcacheMemory.profileMiss(in_msg);
1505 }
1506 }
1507 }
1508
1509 action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
1510 peek(responseNetwork_in, ResponseMsg) {
1511 assert(is_valid(cache_entry));
1512 assert(cache_entry.DataBlk == in_msg.DataBlk);
1513 }
1514 }
1515
1516 action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1517 peek(mandatoryQueue_in, CacheMsg) {
1518 APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1519 }
1520 stall_and_wait(mandatoryQueue_in, address);
1521 }
1522
1523 action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1524 wake_up_dependents(address);
1525 }
1526
1527 action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1528 wake_up_all_dependents();
1529 }
1530
1531 //*****************************************************
1532 // TRANSITIONS
1533 //*****************************************************
1534
1535 // Transitions for Load/Store/L2_Replacement from transient states
1536 transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
1537 ta_traceStalledAddress;
1538 zz_stallAndWaitMandatoryQueue;
1539 }
1540
1541 transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
1542 zz_stallAndWaitMandatoryQueue;
1543 }
1544
1545 transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
1546 zz_stallAndWaitMandatoryQueue;
1547 }
1548
1549
1550 // Lockdowns
1551 transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
1552 l_popPersistentQueue;
1553 }
1554
1555 // Transitions from NP
1556 transition(NP, Load, IS) {
1557 ii_allocateL1DCacheBlock;
1558 i_allocateTBE;
1559 a_issueReadRequest;
1560 uu_profileMiss;
1561 k_popMandatoryQueue;
1562 }
1563
1564 transition(NP, Ifetch, IS) {
1565 pp_allocateL1ICacheBlock;
1566 i_allocateTBE;
1567 a_issueReadRequest;
1568 uu_profileMiss;
1569 k_popMandatoryQueue;
1570 }
1571
1572 transition(NP, {Store, Atomic}, IM) {
1573 ii_allocateL1DCacheBlock;
1574 i_allocateTBE;
1575 b_issueWriteRequest;
1576 uu_profileMiss;
1577 k_popMandatoryQueue;
1578 }
1579
1580 transition(NP, {Ack, Data_Shared, Data_Owner, Data_All_Tokens}) {
1581 bb_bounceResponse;
1582 n_popResponseQueue;
1583 }
1584
1585 transition(NP, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) {
1586 m_popRequestQueue;
1587 }
1588
1589 transition(NP, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1590 l_popPersistentQueue;
1591 }
1592
1593 // Transitions from Idle
1594 transition(I, Load, IS) {
1595 i_allocateTBE;
1596 a_issueReadRequest;
1597 uu_profileMiss;
1598 k_popMandatoryQueue;
1599 }
1600
1601 transition(I, Ifetch, IS) {
1602 i_allocateTBE;
1603 a_issueReadRequest;
1604 uu_profileMiss;
1605 k_popMandatoryQueue;
1606 }
1607
1608 transition(I, {Store, Atomic}, IM) {
1609 i_allocateTBE;
1610 b_issueWriteRequest;
1611 uu_profileMiss;
1612 k_popMandatoryQueue;
1613 }
1614
1615 transition(I, L1_Replacement) {
1616 ta_traceStalledAddress;
1617 tr_tokenReplacement;
1618 gg_deallocateL1CacheBlock;
1619 ka_wakeUpAllDependents;
1620 }
1621
1622 transition(I, {Transient_GETX, Transient_Local_GETX}) {
1623 t_sendAckWithCollectedTokens;
1624 m_popRequestQueue;
1625 }
1626
1627 transition(I, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1628 m_popRequestQueue;
1629 }
1630
1631 transition(I, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1632 e_sendAckWithCollectedTokens;
1633 l_popPersistentQueue;
1634 }
1635
1636 transition(I_L, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}) {
1637 l_popPersistentQueue;
1638 }
1639
1640 transition(I, Ack) {
1641 q_updateTokensFromResponse;
1642 n_popResponseQueue;
1643 }
1644
1645 transition(I, Data_Shared, S) {
1646 u_writeDataToCache;
1647 q_updateTokensFromResponse;
1648 n_popResponseQueue;
1649 }
1650
1651 transition(I, Data_Owner, O) {
1652 u_writeDataToCache;
1653 q_updateTokensFromResponse;
1654 n_popResponseQueue;
1655 }
1656
1657 transition(I, Data_All_Tokens, M) {
1658 u_writeDataToCache;
1659 q_updateTokensFromResponse;
1660 n_popResponseQueue;
1661 }
1662
1663 // Transitions from Shared
1664 transition({S, SM, S_L, SM_L}, {Load, Ifetch}) {
1665 h_load_hit;
1666 k_popMandatoryQueue;
1667 }
1668
1669 transition(S, {Store, Atomic}, SM) {
1670 i_allocateTBE;
1671 b_issueWriteRequest;
1672 uu_profileMiss;
1673 k_popMandatoryQueue;
1674 }
1675
1676 transition(S, L1_Replacement, I) {
1677 ta_traceStalledAddress;
1678 cc_sharedReplacement; // Only needed in some cases
1679 gg_deallocateL1CacheBlock;
1680 ka_wakeUpAllDependents;
1681 }
1682
1683 transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
1684 t_sendAckWithCollectedTokens;
1685 p_informL2AboutTokenLoss;
1686 m_popRequestQueue;
1687 }
1688
1689 // only owner responds to non-local requests
1690 transition(S, Transient_GETS) {
1691 m_popRequestQueue;
1692 }
1693
1694 transition(S, Transient_Local_GETS) {
1695 d_sendDataWithToken;
1696 m_popRequestQueue;
1697 }
1698
1699 transition(S, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1700 m_popRequestQueue;
1701 }
1702
1703 transition({S, S_L}, Persistent_GETX, I_L) {
1704 e_sendAckWithCollectedTokens;
1705 p_informL2AboutTokenLoss;
1706 l_popPersistentQueue;
1707 }
1708
1709 transition(S, {Persistent_GETS, Persistent_GETS_Last_Token}, S_L) {
1710 f_sendAckWithAllButNorOneTokens;
1711 l_popPersistentQueue;
1712 }
1713
1714 transition(S_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1715 l_popPersistentQueue;
1716 }
1717
1718 transition(S, Ack) {
1719 q_updateTokensFromResponse;
1720 n_popResponseQueue;
1721 }
1722
1723 transition(S, Data_Shared) {
1724 w_assertIncomingDataAndCacheDataMatch;
1725 q_updateTokensFromResponse;
1726 n_popResponseQueue;
1727 }
1728
1729 transition(S, Data_Owner, O) {
1730 w_assertIncomingDataAndCacheDataMatch;
1731 q_updateTokensFromResponse;
1732 n_popResponseQueue;
1733 }
1734
1735 transition(S, Data_All_Tokens, M) {
1736 w_assertIncomingDataAndCacheDataMatch;
1737 q_updateTokensFromResponse;
1738 n_popResponseQueue;
1739 }
1740
1741 // Transitions from Owned
1742 transition({O, OM}, {Load, Ifetch}) {
1743 h_load_hit;
1744 k_popMandatoryQueue;
1745 }
1746
1747 transition(O, {Store, Atomic}, OM) {
1748 i_allocateTBE;
1749 b_issueWriteRequest;
1750 uu_profileMiss;
1751 k_popMandatoryQueue;
1752 }
1753
1754 transition(O, L1_Replacement, I) {
1755 ta_traceStalledAddress;
1756 c_ownedReplacement;
1757 gg_deallocateL1CacheBlock;
1758 ka_wakeUpAllDependents;
1759 }
1760
1761 transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
1762 dd_sendDataWithAllTokens;
1763 p_informL2AboutTokenLoss;
1764 m_popRequestQueue;
1765 }
1766
1767 transition(O, Persistent_GETX, I_L) {
1768 ee_sendDataWithAllTokens;
1769 p_informL2AboutTokenLoss;
1770 l_popPersistentQueue;
1771 }
1772
1773 transition(O, Persistent_GETS, S_L) {
1774 ff_sendDataWithAllButNorOneTokens;
1775 l_popPersistentQueue;
1776 }
1777
1778 transition(O, Persistent_GETS_Last_Token, I_L) {
1779 fo_sendDataWithOwnerToken;
1780 l_popPersistentQueue;
1781 }
1782
1783 transition(O, Transient_GETS) {
1784 d_sendDataWithToken;
1785 m_popRequestQueue;
1786 }
1787
1788 transition(O, Transient_Local_GETS) {
1789 d_sendDataWithToken;
1790 m_popRequestQueue;
1791 }
1792
1793 // ran out of tokens, wait for it to go persistent
1794 transition(O, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1795 m_popRequestQueue;
1796 }
1797
1798 transition(O, Ack) {
1799 q_updateTokensFromResponse;
1800 n_popResponseQueue;
1801 }
1802
1803 transition(O, Ack_All_Tokens, M) {
1804 q_updateTokensFromResponse;
1805 n_popResponseQueue;
1806 }
1807
1808 transition(O, Data_Shared) {
1809 w_assertIncomingDataAndCacheDataMatch;
1810 q_updateTokensFromResponse;
1811 n_popResponseQueue;
1812 }
1813
1814 transition(O, Data_All_Tokens, M) {
1815 w_assertIncomingDataAndCacheDataMatch;
1816 q_updateTokensFromResponse;
1817 n_popResponseQueue;
1818 }
1819
1820 // Transitions from Modified
1821 transition({MM, MM_W}, {Load, Ifetch}) {
1822 h_load_hit;
1823 k_popMandatoryQueue;
1824 }
1825
1826 transition({MM_W}, {Store, Atomic}) {
1827 hh_store_hit;
1828 k_popMandatoryQueue;
1829 }
1830
1831 transition(MM, Store) {
1832 hh_store_hit;
1833 k_popMandatoryQueue;
1834 }
1835
1836 transition(MM, Atomic, M) {
1837 hh_store_hit;
1838 k_popMandatoryQueue;
1839 }
1840
1841 transition(MM, L1_Replacement, I) {
1842 ta_traceStalledAddress;
1843 c_ownedReplacement;
1844 gg_deallocateL1CacheBlock;
1845 ka_wakeUpAllDependents;
1846 }
1847
1848 transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
1849 dd_sendDataWithAllTokens;
1850 p_informL2AboutTokenLoss;
1851 m_popRequestQueue;
1852 }
1853
1854 transition({MM_W}, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1855 m_popRequestQueue;
1856 }
1857
1858 // Implement the migratory sharing optimization, even for persistent requests
1859 transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
1860 ee_sendDataWithAllTokens;
1861 p_informL2AboutTokenLoss;
1862 l_popPersistentQueue;
1863 }
1864
1865 // ignore persistent requests in lockout period
1866 transition(MM_W, {Persistent_GETX, Persistent_GETS}) {
1867 l_popPersistentQueue;
1868 }
1869
1870 transition(MM_W, Use_TimeoutNoStarvers, MM) {
1871 s_deallocateTBE;
1872 jj_unsetUseTimer;
1873 kd_wakeUpDependents;
1874 }
1875
1876 transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
1877 s_deallocateTBE;
1878 jj_unsetUseTimer;
1879 kd_wakeUpDependents;
1880 }
1881
1882 // Transitions from Dirty Exclusive
1883 transition({M, M_W}, {Load, Ifetch}) {
1884 h_load_hit;
1885 k_popMandatoryQueue;
1886 }
1887
1888 transition(M, Store, MM) {
1889 hh_store_hit;
1890 k_popMandatoryQueue;
1891 }
1892
1893 transition(M, Atomic) {
1894 hh_store_hit;
1895 k_popMandatoryQueue;
1896 }
1897
1898 transition(M_W, Store, MM_W) {
1899 hh_store_hit;
1900 k_popMandatoryQueue;
1901 }
1902
1903 transition(M_W, Atomic) {
1904 hh_store_hit;
1905 k_popMandatoryQueue;
1906 }
1907
1908 transition(M, L1_Replacement, I) {
1909 ta_traceStalledAddress;
1910 c_ownedReplacement;
1911 gg_deallocateL1CacheBlock;
1912 ka_wakeUpAllDependents;
1913 }
1914
1915 transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
1916 dd_sendDataWithAllTokens;
1917 p_informL2AboutTokenLoss;
1918 m_popRequestQueue;
1919 }
1920
1921 transition(M, Transient_Local_GETS, O) {
1922 d_sendDataWithToken;
1923 m_popRequestQueue;
1924 }
1925
1926 transition(M, Transient_GETS, O) {
1927 d_sendDataWithNTokenIfAvail;
1928 m_popRequestQueue;
1929 }
1930
1931 transition(M_W, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1932 m_popRequestQueue;
1933 }
1934
1935 transition(M, Persistent_GETX, I_L) {
1936 ee_sendDataWithAllTokens;
1937 p_informL2AboutTokenLoss;
1938 l_popPersistentQueue;
1939 }
1940
1941 transition(M, Persistent_GETS, S_L) {
1942 ff_sendDataWithAllButNorOneTokens;
1943 l_popPersistentQueue;
1944 }
1945
1946 // ignore persistent requests in lockout period
1947 transition(M_W, {Persistent_GETX, Persistent_GETS}) {
1948 l_popPersistentQueue;
1949 }
1950
1951 transition(M_W, Use_TimeoutStarverS, S_L) {
1952 s_deallocateTBE;
1953 ff_sendDataWithAllButNorOneTokens;
1954 jj_unsetUseTimer;
1955 }
1956
1957 // someone unlocked during timeout
1958 transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
1959 s_deallocateTBE;
1960 jj_unsetUseTimer;
1961 kd_wakeUpDependents;
1962 }
1963
1964 transition(M_W, Use_TimeoutStarverX, I_L) {
1965 s_deallocateTBE;
1966 ee_sendDataWithAllTokens;
1967 p_informL2AboutTokenLoss;
1968 jj_unsetUseTimer;
1969 }
1970
1971
1972
1973 // migratory
1974 transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
1975 s_deallocateTBE;
1976 ee_sendDataWithAllTokens;
1977 p_informL2AboutTokenLoss;
1978 jj_unsetUseTimer;
1979
1980 }
1981
1982
1983 // Transient_GETX and Transient_GETS in transient states
1984 transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1985 m_popRequestQueue; // Even if we have the data, we can pretend we don't have it yet.
1986 }
1987
1988 transition(IS, {Transient_GETX, Transient_Local_GETX}) {
1989 t_sendAckWithCollectedTokens;
1990 m_popRequestQueue;
1991 }
1992
1993 transition(IS, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1994 m_popRequestQueue;
1995 }
1996
1997 transition(IS, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IS_L) {
1998 e_sendAckWithCollectedTokens;
1999 l_popPersistentQueue;
2000 }
2001
2002 transition(IS_L, {Persistent_GETX, Persistent_GETS}) {
2003 l_popPersistentQueue;
2004 }
2005
2006 transition(IM, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IM_L) {
2007 e_sendAckWithCollectedTokens;
2008 l_popPersistentQueue;
2009 }
2010
2011 transition(IM_L, {Persistent_GETX, Persistent_GETS}) {
2012 l_popPersistentQueue;
2013 }
2014
2015 transition({SM, SM_L}, Persistent_GETX, IM_L) {
2016 e_sendAckWithCollectedTokens;
2017 l_popPersistentQueue;
2018 }
2019
2020 transition(SM, {Persistent_GETS, Persistent_GETS_Last_Token}, SM_L) {
2021 f_sendAckWithAllButNorOneTokens;
2022 l_popPersistentQueue;
2023 }
2024
2025 transition(SM_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
2026 l_popPersistentQueue;
2027 }
2028
2029 transition(OM, Persistent_GETX, IM_L) {
2030 ee_sendDataWithAllTokens;
2031 l_popPersistentQueue;
2032 }
2033
2034 transition(OM, Persistent_GETS, SM_L) {
2035 ff_sendDataWithAllButNorOneTokens;
2036 l_popPersistentQueue;
2037 }
2038
2039 transition(OM, Persistent_GETS_Last_Token, IM_L) {
2040 fo_sendDataWithOwnerToken;
2041 l_popPersistentQueue;
2042 }
2043
2044 // Transitions from IM/SM
2045
2046 transition({IM, SM}, Ack) {
2047 q_updateTokensFromResponse;
2048 n_popResponseQueue;
2049 }
2050
2051 transition(IM, Data_Shared, SM) {
2052 u_writeDataToCache;
2053 q_updateTokensFromResponse;
2054 n_popResponseQueue;
2055 }
2056
2057 transition(IM, Data_Owner, OM) {
2058 u_writeDataToCache;
2059 q_updateTokensFromResponse;
2060 n_popResponseQueue;
2061 }
2062
2063 transition(IM, Data_All_Tokens, MM_W) {
2064 u_writeDataToCache;
2065 q_updateTokensFromResponse;
2066 xx_external_store_hit;
2067 o_scheduleUseTimeout;
2068 j_unsetReissueTimer;
2069 n_popResponseQueue;
2070 kd_wakeUpDependents;
2071 }
2072
2073 transition(SM, Data_Shared) {
2074 w_assertIncomingDataAndCacheDataMatch;
2075 q_updateTokensFromResponse;
2076 n_popResponseQueue;
2077 }
2078
2079 transition(SM, Data_Owner, OM) {
2080 w_assertIncomingDataAndCacheDataMatch;
2081 q_updateTokensFromResponse;
2082 n_popResponseQueue;
2083 }
2084
2085 transition(SM, Data_All_Tokens, MM_W) {
2086 w_assertIncomingDataAndCacheDataMatch;
2087 q_updateTokensFromResponse;
2088 xx_external_store_hit;
2089 o_scheduleUseTimeout;
2090 j_unsetReissueTimer;
2091 n_popResponseQueue;
2092 kd_wakeUpDependents;
2093 }
2094
2095 transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens. We give them up here to avoid livelock
2096 t_sendAckWithCollectedTokens;
2097 m_popRequestQueue;
2098 }
2099
2100 transition({IM, SM}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2101 m_popRequestQueue;
2102 }
2103
2104 transition({IM, SM}, Request_Timeout) {
2105 j_unsetReissueTimer;
2106 b_issueWriteRequest;
2107 }
2108
2109 // Transitions from OM
2110
2111 transition(OM, Ack) {
2112 q_updateTokensFromResponse;
2113 n_popResponseQueue;
2114 }
2115
2116 transition(OM, Ack_All_Tokens, MM_W) {
2117 q_updateTokensFromResponse;
2118 xx_external_store_hit;
2119 o_scheduleUseTimeout;
2120 j_unsetReissueTimer;
2121 n_popResponseQueue;
2122 kd_wakeUpDependents;
2123 }
2124
2125 transition(OM, Data_Shared) {
2126 w_assertIncomingDataAndCacheDataMatch;
2127 q_updateTokensFromResponse;
2128 n_popResponseQueue;
2129 }
2130
2131 transition(OM, Data_All_Tokens, MM_W) {
2132 w_assertIncomingDataAndCacheDataMatch;
2133 q_updateTokensFromResponse;
2134 xx_external_store_hit;
2135 o_scheduleUseTimeout;
2136 j_unsetReissueTimer;
2137 n_popResponseQueue;
2138 kd_wakeUpDependents;
2139 }
2140
2141 transition(OM, Request_Timeout) {
2142 j_unsetReissueTimer;
2143 b_issueWriteRequest;
2144 }
2145
2146 // Transitions from IS
2147
2148 transition(IS, Ack) {
2149 q_updateTokensFromResponse;
2150 n_popResponseQueue;
2151 }
2152
2153 transition(IS, Data_Shared, S) {
2154 u_writeDataToCache;
2155 q_updateTokensFromResponse;
2156 x_external_load_hit;
2157 s_deallocateTBE;
2158 j_unsetReissueTimer;
2159 n_popResponseQueue;
2160 kd_wakeUpDependents;
2161 }
2162
2163 transition(IS, Data_Owner, O) {
2164 u_writeDataToCache;
2165 q_updateTokensFromResponse;
2166 x_external_load_hit;
2167 s_deallocateTBE;
2168 j_unsetReissueTimer;
2169 n_popResponseQueue;
2170 kd_wakeUpDependents;
2171 }
2172
2173 transition(IS, Data_All_Tokens, M_W) {
2174 u_writeDataToCache;
2175 q_updateTokensFromResponse;
2176 x_external_load_hit;
2177 o_scheduleUseTimeout;
2178 j_unsetReissueTimer;
2179 n_popResponseQueue;
2180 kd_wakeUpDependents;
2181 }
2182
2183 transition(IS, Request_Timeout) {
2184 j_unsetReissueTimer;
2185 a_issueReadRequest;
2186 }
2187
2188 // Transitions from I_L
2189
2190 transition(I_L, Load, IS_L) {
2191 ii_allocateL1DCacheBlock;
2192 i_allocateTBE;
2193 a_issueReadRequest;
2194 uu_profileMiss;
2195 k_popMandatoryQueue;
2196 }
2197
2198 transition(I_L, Ifetch, IS_L) {
2199 pp_allocateL1ICacheBlock;
2200 i_allocateTBE;
2201 a_issueReadRequest;
2202 uu_profileMiss;
2203 k_popMandatoryQueue;
2204 }
2205
2206 transition(I_L, {Store, Atomic}, IM_L) {
2207 ii_allocateL1DCacheBlock;
2208 i_allocateTBE;
2209 b_issueWriteRequest;
2210 uu_profileMiss;
2211 k_popMandatoryQueue;
2212 }
2213
2214
2215 // Transitions from S_L
2216
2217 transition(S_L, {Store, Atomic}, SM_L) {
2218 i_allocateTBE;
2219 b_issueWriteRequest;
2220 uu_profileMiss;
2221 k_popMandatoryQueue;
2222 }
2223
2224 // Other transitions from *_L states
2225
2226 transition({I_L, IM_L, IS_L, S_L, SM_L}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS, Transient_GETX, Transient_Local_GETX}) {
2227 m_popRequestQueue;
2228 }
2229
2230 transition({I_L, IM_L, IS_L, S_L, SM_L}, Ack) {
2231 g_bounceResponseToStarver;
2232 n_popResponseQueue;
2233 }
2234
2235 transition({I_L, IM_L, S_L, SM_L}, {Data_Shared, Data_Owner}) {
2236 g_bounceResponseToStarver;
2237 n_popResponseQueue;
2238 }
2239
2240 transition({I_L, S_L}, Data_All_Tokens) {
2241 g_bounceResponseToStarver;
2242 n_popResponseQueue;
2243 }
2244
2245 transition(IS_L, Request_Timeout) {
2246 j_unsetReissueTimer;
2247 a_issueReadRequest;
2248 }
2249
2250 transition({IM_L, SM_L}, Request_Timeout) {
2251 j_unsetReissueTimer;
2252 b_issueWriteRequest;
2253 }
2254
2255 // Opportunisticly Complete the memory operation in the following
2256 // cases. Note: these transitions could just use
2257 // g_bounceResponseToStarver, but if we have the data and tokens, we
2258 // might as well complete the memory request while we have the
2259 // chance (and then immediately forward on the data)
2260
2261 transition(IM_L, Data_All_Tokens, MM_W) {
2262 u_writeDataToCache;
2263 q_updateTokensFromResponse;
2264 xx_external_store_hit;
2265 j_unsetReissueTimer;
2266 o_scheduleUseTimeout;
2267 n_popResponseQueue;
2268 kd_wakeUpDependents;
2269 }
2270
2271 transition(SM_L, Data_All_Tokens, S_L) {
2272 u_writeDataToCache;
2273 q_updateTokensFromResponse;
2274 xx_external_store_hit;
2275 ff_sendDataWithAllButNorOneTokens;
2276 s_deallocateTBE;
2277 j_unsetReissueTimer;
2278 n_popResponseQueue;
2279 }
2280
2281 transition(IS_L, Data_Shared, I_L) {
2282 u_writeDataToCache;
2283 q_updateTokensFromResponse;
2284 x_external_load_hit;
2285 s_deallocateTBE;
2286 e_sendAckWithCollectedTokens;
2287 p_informL2AboutTokenLoss;
2288 j_unsetReissueTimer;
2289 n_popResponseQueue;
2290 }
2291
2292 transition(IS_L, Data_Owner, I_L) {
2293 u_writeDataToCache;
2294 q_updateTokensFromResponse;
2295 x_external_load_hit;
2296 ee_sendDataWithAllTokens;
2297 s_deallocateTBE;
2298 p_informL2AboutTokenLoss;
2299 j_unsetReissueTimer;
2300 n_popResponseQueue;
2301 }
2302
2303 transition(IS_L, Data_All_Tokens, M_W) {
2304 u_writeDataToCache;
2305 q_updateTokensFromResponse;
2306 x_external_load_hit;
2307 j_unsetReissueTimer;
2308 o_scheduleUseTimeout;
2309 n_popResponseQueue;
2310 kd_wakeUpDependents;
2311 }
2312
2313
2314 // Own_Lock_or_Unlock
2315
2316 transition(I_L, Own_Lock_or_Unlock, I) {
2317 l_popPersistentQueue;
2318 kd_wakeUpDependents;
2319 }
2320
2321 transition(S_L, Own_Lock_or_Unlock, S) {
2322 l_popPersistentQueue;
2323 kd_wakeUpDependents;
2324 }
2325
2326 transition(IM_L, Own_Lock_or_Unlock, IM) {
2327 l_popPersistentQueue;
2328 kd_wakeUpDependents;
2329 }
2330
2331 transition(IS_L, Own_Lock_or_Unlock, IS) {
2332 l_popPersistentQueue;
2333 kd_wakeUpDependents;
2334 }
2335
2336 transition(SM_L, Own_Lock_or_Unlock, SM) {
2337 l_popPersistentQueue;
2338 kd_wakeUpDependents;
2339 }
2340 }
2341