src/mem/protocol/MOESI_CMP_token-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id: MOESI_CMP_token-L1cache.sm 1.22 05/01/19 15:55:39-06:00 beckmann@s0-28.cs.wisc.edu $
  32  *
  33  */
  34
  35 machine(L1Cache, "Token protocol")
  36  : Sequencer * sequencer,
  37    CacheMemory * L1IcacheMemory,
  38    CacheMemory * L1DcacheMemory,
  39    int l2_select_num_bits,
  40    int N_tokens,
  41    int l1_request_latency = 2,
  42    int l1_response_latency = 2,
  43    int retry_threshold = 1,
  44    int fixed_timeout_latency = 100,
  45    bool dynamic_timeout_enabled = true,
  46    bool no_mig_atomic = true
  47 {
  48
  49   // From this node's L1 cache TO the network
  50
  51   // a local L1 -> this L2 bank
  52   MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false";
  53   MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true";
  54   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  55   MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false";
  56
  57
  58   // To this node's L1 cache FROM the network
  59   // a L2 bank -> this L1
  60   MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false";
  61   MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true";
  62   // a L2 bank -> this L1
  63   MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
  64
  65   // STATES
  66   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  67     // Base states
  68     NP,   "NP",   desc="Not Present";
  69     I,    "I",    desc="Idle";
  70     S,    "S",    desc="Shared";
  71     O,    "O",    desc="Owned";
  72     M,    "M",    desc="Modified (dirty)";
  73     MM,   "MM",   desc="Modified (dirty and locally modified)";
  74     M_W,  "M^W",  desc="Modified (dirty), waiting";
  75     MM_W, "MM^W", desc="Modified (dirty and locally modified), waiting";
  76
  77     // Transient States
  78     IM, "IM", desc="Issued GetX";
  79     SM, "SM", desc="Issued GetX, we still have an old copy of the line";
  80     OM, "OM", desc="Issued GetX, received data";
  81     IS, "IS", desc="Issued GetS";
  82
  83     // Locked states
  84     I_L,  "I^L",   desc="Invalid, Locked";
  85     S_L,  "S^L",   desc="Shared, Locked";
  86     IM_L, "IM^L",  desc="Invalid, Locked, trying to go to Modified";
  87     SM_L, "SM^L",  desc="Shared, Locked, trying to go to Modified";
  88     IS_L, "IS^L",  desc="Invalid, Locked, trying to go to Shared";
  89   }
  90
  91   // EVENTS
  92   enumeration(Event, desc="Cache events") {
  93     Load,            desc="Load request from the processor";
  94     Ifetch,          desc="I-fetch request from the processor";
  95     Store,           desc="Store request from the processor";
  96     Atomic,          desc="Atomic request from the processor";
  97     L1_Replacement,  desc="L1 Replacement";
  98
  99     // Responses
 100     Data_Shared,             desc="Received a data message, we are now a sharer";
 101     Data_Owner,              desc="Received a data message, we are now the owner";
 102     Data_All_Tokens,   desc="Received a data message, we are now the owner, we now have all the tokens";
 103     Ack,                     desc="Received an ack message";
 104     Ack_All_Tokens,          desc="Received an ack message, we now have all the tokens";
 105
 106     // Requests
 107     Transient_GETX,  desc="A GetX from another processor";
 108     Transient_Local_GETX,  desc="A GetX from another processor";
 109     Transient_GETS,  desc="A GetS from another processor";
 110     Transient_Local_GETS,  desc="A GetS from another processor";
 111     Transient_GETS_Last_Token,  desc="A GetS from another processor";
 112     Transient_Local_GETS_Last_Token,  desc="A GetS from another processor";
 113
 114     // Lock/Unlock for distributed
 115     Persistent_GETX,     desc="Another processor has priority to read/write";
 116     Persistent_GETS,     desc="Another processor has priority to read";
 117     Persistent_GETS_Last_Token, desc="Another processor has priority to read, no more tokens";
 118     Own_Lock_or_Unlock,  desc="This processor now has priority";
 119
 120     // Triggers
 121     Request_Timeout,         desc="Timeout";
 122     Use_TimeoutStarverX,             desc="Timeout";
 123     Use_TimeoutStarverS,             desc="Timeout";
 124     Use_TimeoutNoStarvers,             desc="Timeout";
 125     Use_TimeoutNoStarvers_NoMig,     desc="Timeout Don't Migrate";
 126   }
 127
 128   // TYPES
 129
 130   // CacheEntry
 131   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 132     State CacheState,        desc="cache state";
 133     bool Dirty,              desc="Is the data dirty (different than memory)?";
 134     int Tokens,              desc="The number of tokens we're holding for the line";
 135     DataBlock DataBlk,       desc="data for the block";
 136   }
 137
 138
 139   // TBE fields
 140   structure(TBE, desc="...") {
 141     Address Address,                      desc="Physical address for this TBE";
 142     State TBEState,                       desc="Transient state";
 143     int IssueCount,      default="0",     desc="The number of times we've issued a request for this line.";
 144     Address PC,                           desc="Program counter of request";
 145
 146     bool WentPersistent, default="false",  desc="Request went persistent";
 147     bool ExternalResponse, default="false", desc="Response came from an external controller";
 148     bool IsAtomic, default="false",       desc="Request was an atomic request";
 149
 150     AccessType AccessType,                desc="Type of request (used for profiling)";
 151     Time IssueTime,                       desc="Time the request was issued";
 152     AccessModeType AccessMode,    desc="user/supervisor access type";
 153     PrefetchBit Prefetch,         desc="Is this a prefetch request";
 154   }
 155
 156   external_type(TBETable) {
 157     TBE lookup(Address);
 158     void allocate(Address);
 159     void deallocate(Address);
 160     bool isPresent(Address);
 161   }
 162
 163   external_type(PersistentTable) {
 164     void persistentRequestLock(Address, MachineID, AccessType);
 165     void persistentRequestUnlock(Address, MachineID);
 166     bool okToIssueStarving(Address, MachineID);
 167     MachineID findSmallest(Address);
 168     AccessType typeOfSmallest(Address);
 169     void markEntries(Address);
 170     bool isLocked(Address);
 171     int countStarvingForAddress(Address);
 172     int countReadStarvingForAddress(Address);
 173   }
 174
 175   void set_cache_entry(AbstractCacheEntry b);
 176   void unset_cache_entry();
 177   void set_tbe(TBE b);
 178   void unset_tbe();
 179
 180   TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
 181
 182   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 183
 184   bool starving, default="false";
 185   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 186
 187   PersistentTable persistentTable;
 188   TimerTable useTimerTable;
 189   TimerTable reissueTimerTable;
 190
 191   int outstandingRequests, default="0";
 192   int outstandingPersistentRequests, default="0";
 193
 194   int averageLatencyHysteresis, default="(8)"; // Constant that provides hysteresis for calculated the estimated average
 195   int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))";
 196
 197   int averageLatencyEstimate() {
 198     DPRINTF(RubySlicc, "%d\n",
 199             (averageLatencyCounter >> averageLatencyHysteresis));
 200     //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
 201     return averageLatencyCounter >> averageLatencyHysteresis;
 202   }
 203
 204   void updateAverageLatencyEstimate(int latency) {
 205     DPRINTF(RubySlicc, "%d\n", latency);
 206     assert(latency >= 0);
 207
 208     // By subtracting the current average and then adding the most
 209     // recent sample, we calculate an estimate of the recent average.
 210     // If we simply used a running sum and divided by the total number
 211     // of entries, the estimate of the average would adapt very slowly
 212     // after the execution has run for a long time.
 213     // averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
 214
 215     averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
 216   }
 217
 218   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 219     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 220     if(is_valid(L1Dcache_entry)) {
 221       return L1Dcache_entry;
 222     }
 223
 224     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 225     return L1Icache_entry;
 226   }
 227
 228   Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
 229     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 230     return L1Dcache_entry;
 231   }
 232
 233   Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
 234     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 235     return L1Icache_entry;
 236   }
 237
 238   int getTokens(Entry cache_entry) {
 239     if (is_valid(cache_entry)) {
 240       return cache_entry.Tokens;
 241     }
 242     return 0;
 243   }
 244
 245   State getState(TBE tbe, Entry cache_entry, Address addr) {
 246
 247     if (is_valid(tbe)) {
 248       return tbe.TBEState;
 249     } else if (is_valid(cache_entry)) {
 250       return cache_entry.CacheState;
 251     } else {
 252       if ((persistentTable.isLocked(addr) == true) && (persistentTable.findSmallest(addr) != machineID)) {
 253       // Not in cache, in persistent table, but this processor isn't highest priority
 254       return State:I_L;
 255       } else {
 256         return State:NP;
 257       }
 258     }
 259   }
 260
 261   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 262     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 263
 264     if (is_valid(tbe)) {
 265       assert(state != State:I);
 266       assert(state != State:S);
 267       assert(state != State:O);
 268       assert(state != State:MM);
 269       assert(state != State:M);
 270       tbe.TBEState := state;
 271     }
 272
 273     if (is_valid(cache_entry)) {
 274       // Make sure the token count is in range
 275       assert(cache_entry.Tokens >= 0);
 276       assert(cache_entry.Tokens <= max_tokens());
 277       assert(cache_entry.Tokens != (max_tokens() / 2));
 278
 279       if ((state == State:I_L) ||
 280           (state == State:IM_L) ||
 281           (state == State:IS_L)) {
 282         // Make sure we have no tokens in the "Invalid, locked" states
 283           assert(cache_entry.Tokens == 0);
 284
 285         // Make sure the line is locked
 286         // assert(persistentTable.isLocked(addr));
 287
 288         // But we shouldn't have highest priority for it
 289         // assert(persistentTable.findSmallest(addr) != id);
 290
 291       } else if ((state == State:S_L) ||
 292                  (state == State:SM_L)) {
 293         assert(cache_entry.Tokens >= 1);
 294         assert(cache_entry.Tokens < (max_tokens() / 2));
 295
 296         // Make sure the line is locked...
 297         // assert(persistentTable.isLocked(addr));
 298
 299         // ...But we shouldn't have highest priority for it...
 300         // assert(persistentTable.findSmallest(addr) != id);
 301
 302         // ...And it must be a GETS request
 303         // assert(persistentTable.typeOfSmallest(addr) == AccessType:Read);
 304
 305       } else {
 306
 307         // If there is an entry in the persistent table of this block,
 308         // this processor needs to have an entry in the table for this
 309         // block, and that entry better be the smallest (highest
 310         // priority).  Otherwise, the state should have been one of
 311         // locked states
 312
 313         //if (persistentTable.isLocked(addr)) {
 314         //  assert(persistentTable.findSmallest(addr) == id);
 315         //}
 316       }
 317
 318       // in M and E you have all the tokens
 319       if (state == State:MM || state == State:M || state == State:MM_W || state == State:M_W) {
 320         assert(cache_entry.Tokens == max_tokens());
 321       }
 322
 323       // in NP you have no tokens
 324       if (state == State:NP) {
 325         assert(cache_entry.Tokens == 0);
 326       }
 327
 328       // You have at least one token in S-like states
 329       if (state == State:S || state == State:SM) {
 330         assert(cache_entry.Tokens > 0);
 331       }
 332
 333       // You have at least half the token in O-like states
 334       if (state == State:O && state == State:OM) {
 335         assert(cache_entry.Tokens > (max_tokens() / 2));
 336       }
 337
 338       cache_entry.CacheState := state;
 339
 340       // Set permission
 341       if (state == State:MM ||
 342           state == State:MM_W) {
 343         cache_entry.changePermission(AccessPermission:Read_Write);
 344       } else if ((state == State:S) ||
 345                  (state == State:O) ||
 346                  (state == State:M) ||
 347                  (state == State:M_W) ||
 348                  (state == State:SM) ||
 349                  (state == State:S_L) ||
 350                  (state == State:SM_L) ||
 351                  (state == State:OM)) {
 352         cache_entry.changePermission(AccessPermission:Read_Only);
 353       } else {
 354         cache_entry.changePermission(AccessPermission:Invalid);
 355       }
 356     }
 357   }
 358
 359   Event mandatory_request_type_to_event(CacheRequestType type) {
 360     if (type == CacheRequestType:LD) {
 361       return Event:Load;
 362     } else if (type == CacheRequestType:IFETCH) {
 363       return Event:Ifetch;
 364     } else if (type == CacheRequestType:ST) {
 365       return Event:Store;
 366     } else if (type == CacheRequestType:ATOMIC) {
 367       if (no_mig_atomic) {
 368         return Event:Atomic;
 369       } else {
 370         return Event:Store;
 371       }
 372     } else {
 373       error("Invalid CacheRequestType");
 374     }
 375   }
 376
 377   AccessType cache_request_type_to_access_type(CacheRequestType type) {
 378     if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) {
 379       return AccessType:Read;
 380     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 381       return AccessType:Write;
 382     } else {
 383       error("Invalid CacheRequestType");
 384     }
 385   }
 386
 387   GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
 388     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
 389       //
 390       // NOTE direct local hits should not call this
 391       //
 392       return GenericMachineType:L1Cache_wCC;
 393     } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
 394
 395       if (sender == (mapAddressToRange(addr,
 396                                        MachineType:L2Cache,
 397                                        l2_select_low_bit,
 398                                        l2_select_num_bits))) {
 399
 400         return GenericMachineType:L2Cache;
 401       } else {
 402         return GenericMachineType:L2Cache_wCC;
 403       }
 404     } else {
 405       return ConvertMachToGenericMach(machineIDToMachineType(sender));
 406     }
 407   }
 408
 409   bool okToIssueStarving(Address addr, MachineID machinID) {
 410     return persistentTable.okToIssueStarving(addr, machineID);
 411   }
 412
 413   void markPersistentEntries(Address addr) {
 414     persistentTable.markEntries(addr);
 415   }
 416
 417   void setExternalResponse(TBE tbe) {
 418     assert(is_valid(tbe));
 419     tbe.ExternalResponse := true;
 420   }
 421
 422   bool IsAtomic(TBE tbe) {
 423     assert(is_valid(tbe));
 424     return tbe.IsAtomic;
 425   }
 426
 427   // ** OUT_PORTS **
 428   out_port(persistentNetwork_out, PersistentMsg, persistentFromL1Cache);
 429   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 430   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 431   out_port(requestRecycle_out, RequestMsg, requestToL1Cache);
 432
 433   // ** IN_PORTS **
 434
 435   // Use Timer
 436   in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
 437     if (useTimerTable_in.isReady()) {
 438       TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
 439
 440       if (persistentTable.isLocked(useTimerTable.readyAddress()) &&
 441           (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
 442         if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
 443           trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress(),
 444                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 445         } else {
 446           trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress(),
 447                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 448         }
 449       } else {
 450         if (no_mig_atomic && IsAtomic(tbe)) {
 451           trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress(),
 452                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 453         } else {
 454           trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress(),
 455                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 456         }
 457       }
 458     }
 459   }
 460
 461   // Reissue Timer
 462   in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
 463     if (reissueTimerTable_in.isReady()) {
 464       trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
 465               getCacheEntry(reissueTimerTable.readyAddress()),
 466               L1_TBEs[reissueTimerTable.readyAddress()]);
 467     }
 468   }
 469
 470   // Persistent Network
 471   in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
 472     if (persistentNetwork_in.isReady()) {
 473       peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
 474         assert(in_msg.Destination.isElement(machineID));
 475
 476         // Apply the lockdown or unlockdown message to the table
 477         if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
 478           persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
 479         } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
 480           persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
 481         } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
 482           persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
 483         } else {
 484           error("Unexpected message");
 485         }
 486
 487         // React to the message based on the current state of the table
 488         Entry cache_entry := getCacheEntry(in_msg.Address);
 489         TBE tbe := L1_TBEs[in_msg.Address];
 490
 491         if (persistentTable.isLocked(in_msg.Address)) {
 492           if (persistentTable.findSmallest(in_msg.Address) == machineID) {
 493             // Our Own Lock - this processor is highest priority
 494             trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 495                     cache_entry, tbe);
 496           } else {
 497             if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
 498               if (getTokens(cache_entry) == 1 ||
 499                   getTokens(cache_entry) == (max_tokens() / 2) + 1) {
 500                 trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
 501                         cache_entry, tbe);
 502               } else {
 503                 trigger(Event:Persistent_GETS, in_msg.Address,
 504                         cache_entry, tbe);
 505               }
 506             } else {
 507               trigger(Event:Persistent_GETX, in_msg.Address,
 508                       cache_entry, tbe);
 509             }
 510           }
 511         } else {
 512           // Unlock case - no entries in the table
 513           trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 514                   cache_entry, tbe);
 515         }
 516       }
 517     }
 518   }
 519
 520   // Response Network
 521   in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
 522     if (responseNetwork_in.isReady()) {
 523       peek(responseNetwork_in, ResponseMsg, block_on="Address") {
 524         assert(in_msg.Destination.isElement(machineID));
 525
 526         Entry cache_entry := getCacheEntry(in_msg.Address);
 527         TBE tbe := L1_TBEs[in_msg.Address];
 528
 529         // Mark TBE flag if response received off-chip.  Use this to update average latency estimate
 530         if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
 531
 532           if (in_msg.Sender == mapAddressToRange(in_msg.Address,
 533                                                  MachineType:L2Cache,
 534                                                  l2_select_low_bit,
 535                                                  l2_select_num_bits)) {
 536
 537             // came from an off-chip L2 cache
 538             if (is_valid(tbe)) {
 539                // L1_TBEs[in_msg.Address].ExternalResponse := true;
 540                // profile_offchipL2_response(in_msg.Address);
 541             }
 542           }
 543           else {
 544                // profile_onchipL2_response(in_msg.Address );
 545           }
 546         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
 547           if (is_valid(tbe)) {
 548             setExternalResponse(tbe);
 549             // profile_memory_response( in_msg.Address);
 550           }
 551         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 552           //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
 553             //if (is_valid(tbe)) {
 554                // tbe.ExternalResponse := true;
 555                // profile_offchipL1_response(in_msg.Address );
 556             //}
 557           //}
 558           //else {
 559                // profile_onchipL1_response(in_msg.Address );
 560           //}
 561         } else {
 562           error("unexpected SenderMachine");
 563         }
 564
 565
 566         if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
 567           if (in_msg.Type == CoherenceResponseType:ACK) {
 568             assert(in_msg.Tokens < (max_tokens() / 2));
 569             trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
 570           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
 571             trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
 572           } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 573             assert(in_msg.Tokens < (max_tokens() / 2));
 574             trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
 575           } else {
 576             error("Unexpected message");
 577           }
 578         } else {
 579           if (in_msg.Type == CoherenceResponseType:ACK) {
 580             assert(in_msg.Tokens < (max_tokens() / 2));
 581             trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
 582           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 583             trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
 584           } else {
 585             error("Unexpected message");
 586           }
 587         }
 588       }
 589     }
 590   }
 591
 592   // Request Network
 593   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 594     if (requestNetwork_in.isReady()) {
 595       peek(requestNetwork_in, RequestMsg, block_on="Address") {
 596         assert(in_msg.Destination.isElement(machineID));
 597
 598         Entry cache_entry := getCacheEntry(in_msg.Address);
 599         TBE tbe := L1_TBEs[in_msg.Address];
 600
 601         if (in_msg.Type == CoherenceRequestType:GETX) {
 602           if (in_msg.isLocal) {
 603             trigger(Event:Transient_Local_GETX, in_msg.Address,
 604                     cache_entry, tbe);
 605           }
 606           else {
 607             trigger(Event:Transient_GETX, in_msg.Address,
 608                     cache_entry, tbe);
 609           }
 610         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 611           if (getTokens(cache_entry) == 1 ||
 612               getTokens(cache_entry) == (max_tokens() / 2) + 1) {
 613             if (in_msg.isLocal) {
 614               trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
 615                       cache_entry, tbe);
 616             }
 617             else {
 618               trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
 619                       cache_entry, tbe);
 620             }
 621           }
 622           else {
 623             if (in_msg.isLocal) {
 624               trigger(Event:Transient_Local_GETS, in_msg.Address,
 625                       cache_entry, tbe);
 626             }
 627             else {
 628               trigger(Event:Transient_GETS, in_msg.Address,
 629                       cache_entry, tbe);
 630             }
 631           }
 632         } else {
 633           error("Unexpected message");
 634         }
 635       }
 636     }
 637   }
 638
 639   // Mandatory Queue
 640   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
 641     if (mandatoryQueue_in.isReady()) {
 642       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 643         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 644
 645         TBE tbe := L1_TBEs[in_msg.LineAddress];
 646
 647         if (in_msg.Type == CacheRequestType:IFETCH) {
 648           // ** INSTRUCTION ACCESS ***
 649
 650           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 651           if (is_valid(L1Icache_entry)) {
 652             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 653             trigger(mandatory_request_type_to_event(in_msg.Type),
 654                     in_msg.LineAddress, L1Icache_entry, tbe);
 655           } else {
 656
 657             // Check to see if it is in the OTHER L1
 658             Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 659             if (is_valid(L1Dcache_entry)) {
 660               // The block is in the wrong L1, try to write it to the L2
 661                 trigger(Event:L1_Replacement, in_msg.LineAddress,
 662                         L1Dcache_entry, tbe);
 663             }
 664
 665             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 666               // L1 does't have the line, but we have space for it in the L1
 667               trigger(mandatory_request_type_to_event(in_msg.Type),
 668                       in_msg.LineAddress, L1Icache_entry, tbe);
 669             } else {
 670               // No room in the L1, so we need to make room
 671               trigger(Event:L1_Replacement,
 672                       L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 673                       getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 674                       L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 675             }
 676           }
 677         } else {
 678           // *** DATA ACCESS ***
 679
 680           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 681           if (is_valid(L1Dcache_entry)) {
 682             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 683             trigger(mandatory_request_type_to_event(in_msg.Type),
 684                     in_msg.LineAddress, L1Dcache_entry, tbe);
 685           } else {
 686
 687             // Check to see if it is in the OTHER L1
 688             Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 689             if (is_valid(L1Icache_entry)) {
 690               // The block is in the wrong L1, try to write it to the L2
 691               trigger(Event:L1_Replacement, in_msg.LineAddress,
 692                       L1Icache_entry, tbe);
 693             }
 694
 695             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 696               // L1 does't have the line, but we have space for it in the L1
 697               trigger(mandatory_request_type_to_event(in_msg.Type),
 698                       in_msg.LineAddress, L1Dcache_entry, tbe);
 699             } else {
 700               // No room in the L1, so we need to make room
 701               trigger(Event:L1_Replacement,
 702                       L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 703                       getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 704                       L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 705             }
 706           }
 707         }
 708       }
 709     }
 710   }
 711
 712   // ACTIONS
 713
 714   action(a_issueReadRequest, "a", desc="Issue GETS") {
 715       assert(is_valid(tbe));
 716       if (tbe.IssueCount == 0) {
 717         // Update outstanding requests
 718         //profile_outstanding_request(outstandingRequests);
 719         outstandingRequests := outstandingRequests + 1;
 720       }
 721
 722       if (tbe.IssueCount >= retry_threshold) {
 723         // Issue a persistent request if possible
 724         if (okToIssueStarving(address, machineID) && (starving == false)) {
 725           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
 726             out_msg.Address := address;
 727             out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
 728             out_msg.Requestor := machineID;
 729             out_msg.Destination.broadcast(MachineType:L1Cache);
 730
 731             //
 732             // Currently the configuration system limits the system to only one
 733             // chip.  Therefore, if we assume one shared L2 cache, then only one
 734             // pertinent L2 cache exist.
 735             //
 736             //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 737
 738             out_msg.Destination.add(mapAddressToRange(address,
 739                                                       MachineType:L2Cache,
 740                                                       l2_select_low_bit,
 741                                                       l2_select_num_bits));
 742
 743             out_msg.Destination.add(map_Address_to_Directory(address));
 744             out_msg.MessageSize := MessageSizeType:Persistent_Control;
 745             out_msg.Prefetch := tbe.Prefetch;
 746             out_msg.AccessMode := tbe.AccessMode;
 747           }
 748           markPersistentEntries(address);
 749           starving := true;
 750
 751           if (tbe.IssueCount == 0) {
 752             //profile_persistent_prediction(address, tbe.AccessType);
 753           }
 754
 755           // Update outstanding requests
 756           //profile_outstanding_persistent_request(outstandingPersistentRequests);
 757           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 758
 759           // Increment IssueCount
 760           tbe.IssueCount := tbe.IssueCount + 1;
 761
 762           tbe.WentPersistent := true;
 763
 764           // Do not schedule a wakeup, a persistent requests will always complete
 765         }
 766         else {
 767
 768           // We'd like to issue a persistent request, but are not allowed
 769           // to issue a P.R. right now.  This, we do not increment the
 770           // IssueCount.
 771
 772           // Set a wakeup timer
 773           reissueTimerTable.set(address, 10);
 774
 775         }
 776       } else {
 777         // Make a normal request
 778         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 779           out_msg.Address := address;
 780           out_msg.Type := CoherenceRequestType:GETS;
 781           out_msg.Requestor := machineID;
 782           out_msg.Destination.add(mapAddressToRange(address,
 783                                                     MachineType:L2Cache,
 784                                                     l2_select_low_bit,
 785                                                     l2_select_num_bits));
 786
 787           out_msg.RetryNum := tbe.IssueCount;
 788           if (tbe.IssueCount == 0) {
 789             out_msg.MessageSize := MessageSizeType:Request_Control;
 790           } else {
 791             out_msg.MessageSize := MessageSizeType:Reissue_Control;
 792           }
 793           out_msg.Prefetch := tbe.Prefetch;
 794           out_msg.AccessMode := tbe.AccessMode;
 795         }
 796
 797         // send to other local L1s, with local bit set
 798         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 799           out_msg.Address := address;
 800           out_msg.Type := CoherenceRequestType:GETS;
 801           out_msg.Requestor := machineID;
 802           //
 803           // Since only one chip, assuming all L1 caches are local
 804           //
 805           //out_msg.Destination := getOtherLocalL1IDs(machineID);
 806           out_msg.Destination.broadcast(MachineType:L1Cache);
 807           out_msg.Destination.remove(machineID);
 808
 809           out_msg.RetryNum := tbe.IssueCount;
 810           out_msg.isLocal := true;
 811           if (tbe.IssueCount == 0) {
 812             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 813           } else {
 814             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 815           }
 816           out_msg.Prefetch := tbe.Prefetch;
 817           out_msg.AccessMode := tbe.AccessMode;
 818         }
 819
 820         // Increment IssueCount
 821         tbe.IssueCount := tbe.IssueCount + 1;
 822
 823         // Set a wakeup timer
 824
 825         if (dynamic_timeout_enabled) {
 826           reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
 827         } else {
 828           reissueTimerTable.set(address, fixed_timeout_latency);
 829         }
 830
 831       }
 832   }
 833
 834   action(b_issueWriteRequest, "b", desc="Issue GETX") {
 835
 836       assert(is_valid(tbe));
 837       if (tbe.IssueCount == 0) {
 838         // Update outstanding requests
 839         //profile_outstanding_request(outstandingRequests);
 840         outstandingRequests := outstandingRequests + 1;
 841       }
 842
 843       if (tbe.IssueCount >= retry_threshold) {
 844         // Issue a persistent request if possible
 845         if ( okToIssueStarving(address, machineID) && (starving == false)) {
 846           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
 847             out_msg.Address := address;
 848             out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
 849             out_msg.Requestor := machineID;
 850             out_msg.Destination.broadcast(MachineType:L1Cache);
 851
 852             //
 853             // Currently the configuration system limits the system to only one
 854             // chip.  Therefore, if we assume one shared L2 cache, then only one
 855             // pertinent L2 cache exist.
 856             //
 857             //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 858
 859             out_msg.Destination.add(mapAddressToRange(address,
 860                                                       MachineType:L2Cache,
 861                                                       l2_select_low_bit,
 862                                                       l2_select_num_bits));
 863
 864             out_msg.Destination.add(map_Address_to_Directory(address));
 865             out_msg.MessageSize := MessageSizeType:Persistent_Control;
 866             out_msg.Prefetch := tbe.Prefetch;
 867             out_msg.AccessMode := tbe.AccessMode;
 868           }
 869           markPersistentEntries(address);
 870           starving := true;
 871
 872           // Update outstanding requests
 873           //profile_outstanding_persistent_request(outstandingPersistentRequests);
 874           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 875
 876           if (tbe.IssueCount == 0) {
 877             //profile_persistent_prediction(address, tbe.AccessType);
 878           }
 879
 880           // Increment IssueCount
 881           tbe.IssueCount := tbe.IssueCount + 1;
 882
 883           tbe.WentPersistent := true;
 884
 885           // Do not schedule a wakeup, a persistent requests will always complete
 886         }
 887         else {
 888
 889           // We'd like to issue a persistent request, but are not allowed
 890           // to issue a P.R. right now.  This, we do not increment the
 891           // IssueCount.
 892
 893           // Set a wakeup timer
 894           reissueTimerTable.set(address, 10);
 895         }
 896
 897
 898       } else  {
 899         // Make a normal request
 900         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 901           out_msg.Address := address;
 902           out_msg.Type := CoherenceRequestType:GETX;
 903           out_msg.Requestor := machineID;
 904
 905           out_msg.Destination.add(mapAddressToRange(address,
 906                                                     MachineType:L2Cache,
 907                                                     l2_select_low_bit,
 908                                                     l2_select_num_bits));
 909
 910           out_msg.RetryNum := tbe.IssueCount;
 911
 912           if (tbe.IssueCount == 0) {
 913             out_msg.MessageSize := MessageSizeType:Request_Control;
 914           } else {
 915             out_msg.MessageSize := MessageSizeType:Reissue_Control;
 916           }
 917           out_msg.Prefetch := tbe.Prefetch;
 918           out_msg.AccessMode := tbe.AccessMode;
 919         }
 920
 921         // send to other local L1s too
 922         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 923           out_msg.Address := address;
 924           out_msg.Type := CoherenceRequestType:GETX;
 925           out_msg.Requestor := machineID;
 926           out_msg.isLocal := true;
 927
 928           //
 929           // Since only one chip, assuming all L1 caches are local
 930           //
 931           //out_msg.Destination := getOtherLocalL1IDs(machineID);
 932           out_msg.Destination.broadcast(MachineType:L1Cache);
 933           out_msg.Destination.remove(machineID);
 934
 935           out_msg.RetryNum := tbe.IssueCount;
 936           if (tbe.IssueCount == 0) {
 937             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 938           } else {
 939             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 940           }
 941           out_msg.Prefetch := tbe.Prefetch;
 942           out_msg.AccessMode := tbe.AccessMode;
 943         }
 944
 945         // Increment IssueCount
 946         tbe.IssueCount := tbe.IssueCount + 1;
 947
 948         DPRINTF(RubySlicc, "incremented issue count to %d\n",
 949                 tbe.IssueCount);
 950
 951         // Set a wakeup timer
 952         if (dynamic_timeout_enabled) {
 953           reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
 954         } else {
 955           reissueTimerTable.set(address, fixed_timeout_latency);
 956         }
 957       }
 958   }
 959
 960   action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") {
 961     peek(responseNetwork_in, ResponseMsg) {
 962       // FIXME, should use a 3rd vnet
 963       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 964         out_msg.Address := address;
 965         out_msg.Type := in_msg.Type;
 966         out_msg.Sender := machineID;
 967         out_msg.Destination.add(map_Address_to_Directory(address));
 968         out_msg.Tokens := in_msg.Tokens;
 969         out_msg.MessageSize := in_msg.MessageSize;
 970         out_msg.DataBlk := in_msg.DataBlk;
 971         out_msg.Dirty := in_msg.Dirty;
 972       }
 973     }
 974   }
 975
 976   action(c_ownedReplacement, "c", desc="Issue writeback") {
 977     assert(is_valid(cache_entry));
 978     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
 979       out_msg.Address := address;
 980       out_msg.Sender := machineID;
 981
 982       out_msg.Destination.add(mapAddressToRange(address,
 983                                                 MachineType:L2Cache,
 984                                                 l2_select_low_bit,
 985                                                 l2_select_num_bits));
 986
 987       out_msg.Tokens := cache_entry.Tokens;
 988       out_msg.DataBlk := cache_entry.DataBlk;
 989       out_msg.Dirty := cache_entry.Dirty;
 990       out_msg.Type := CoherenceResponseType:WB_OWNED;
 991
 992       // always send the data?
 993       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 994     }
 995     cache_entry.Tokens := 0;
 996   }
 997
 998   action(cc_sharedReplacement, "\c", desc="Issue shared writeback") {
 999
1000     // don't send writeback if replacing block with no tokens
1001     assert(is_valid(cache_entry));
1002     assert (cache_entry.Tokens > 0);
1003     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1004         out_msg.Address := address;
1005         out_msg.Sender := machineID;
1006
1007         out_msg.Destination.add(mapAddressToRange(address,
1008                                                   MachineType:L2Cache,
1009                                                   l2_select_low_bit,
1010                                                   l2_select_num_bits));
1011
1012         out_msg.Tokens := cache_entry.Tokens;
1013         out_msg.DataBlk := cache_entry.DataBlk;
1014         // assert(cache_entry.Dirty == false);
1015         out_msg.Dirty := false;
1016
1017         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1018         out_msg.Type := CoherenceResponseType:WB_SHARED_DATA;
1019     }
1020     cache_entry.Tokens := 0;
1021   }
1022
1023   action(tr_tokenReplacement, "tr", desc="Issue token writeback") {
1024     assert(is_valid(cache_entry));
1025     if (cache_entry.Tokens > 0) {
1026       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1027         out_msg.Address := address;
1028         out_msg.Sender := machineID;
1029
1030         out_msg.Destination.add(mapAddressToRange(address,
1031                                                   MachineType:L2Cache,
1032                                                   l2_select_low_bit,
1033                                                   l2_select_num_bits));
1034
1035         out_msg.Tokens := cache_entry.Tokens;
1036         out_msg.DataBlk := cache_entry.DataBlk;
1037         // assert(cache_entry.Dirty == false);
1038         out_msg.Dirty := false;
1039
1040         // always send the data?
1041         out_msg.MessageSize := MessageSizeType:Writeback_Control;
1042         out_msg.Type := CoherenceResponseType:WB_TOKENS;
1043       }
1044     }
1045     cache_entry.Tokens := 0;
1046   }
1047
1048
1049   action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") {
1050     assert(is_valid(cache_entry));
1051     peek(requestNetwork_in, RequestMsg) {
1052       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1053         out_msg.Address := address;
1054         out_msg.Type := CoherenceResponseType:DATA_SHARED;
1055         out_msg.Sender := machineID;
1056         out_msg.Destination.add(in_msg.Requestor);
1057         out_msg.Tokens := 1;
1058         out_msg.DataBlk := cache_entry.DataBlk;
1059         // out_msg.Dirty := cache_entry.Dirty;
1060         out_msg.Dirty := false;
1061         if (in_msg.isLocal) {
1062           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1063         } else {
1064           out_msg.MessageSize := MessageSizeType:Response_Data;
1065         }
1066       }
1067     }
1068     cache_entry.Tokens := cache_entry.Tokens - 1;
1069     assert(cache_entry.Tokens >= 1);
1070   }
1071
1072   action(d_sendDataWithNTokenIfAvail, "\dd", desc="Send data and a token from cache to requestor") {
1073     assert(is_valid(cache_entry));
1074     peek(requestNetwork_in, RequestMsg) {
1075       if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1076         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1077           out_msg.Address := address;
1078           out_msg.Type := CoherenceResponseType:DATA_SHARED;
1079           out_msg.Sender := machineID;
1080           out_msg.Destination.add(in_msg.Requestor);
1081           out_msg.Tokens := N_tokens;
1082           out_msg.DataBlk := cache_entry.DataBlk;
1083           // out_msg.Dirty := cache_entry.Dirty;
1084           out_msg.Dirty := false;
1085           if (in_msg.isLocal) {
1086             out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1087           } else {
1088             out_msg.MessageSize := MessageSizeType:Response_Data;
1089           }
1090         }
1091         cache_entry.Tokens := cache_entry.Tokens - N_tokens;
1092       }
1093       else if (cache_entry.Tokens > 1) {
1094         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1095           out_msg.Address := address;
1096           out_msg.Type := CoherenceResponseType:DATA_SHARED;
1097           out_msg.Sender := machineID;
1098           out_msg.Destination.add(in_msg.Requestor);
1099           out_msg.Tokens := 1;
1100           out_msg.DataBlk := cache_entry.DataBlk;
1101           // out_msg.Dirty := cache_entry.Dirty;
1102           out_msg.Dirty := false;
1103           if (in_msg.isLocal) {
1104             out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1105           } else {
1106             out_msg.MessageSize := MessageSizeType:Response_Data;
1107           }
1108         }
1109         cache_entry.Tokens := cache_entry.Tokens - 1;
1110       }
1111     }
1112 //    assert(cache_entry.Tokens >= 1);
1113   }
1114
1115   action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") {
1116     peek(requestNetwork_in, RequestMsg) {
1117     assert(is_valid(cache_entry));
1118       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1119         out_msg.Address := address;
1120         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1121         out_msg.Sender := machineID;
1122         out_msg.Destination.add(in_msg.Requestor);
1123         assert(cache_entry.Tokens > (max_tokens() / 2));
1124         out_msg.Tokens := cache_entry.Tokens;
1125         out_msg.DataBlk := cache_entry.DataBlk;
1126         out_msg.Dirty := cache_entry.Dirty;
1127         if (in_msg.isLocal) {
1128           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1129         } else {
1130           out_msg.MessageSize := MessageSizeType:Response_Data;
1131         }
1132       }
1133     }
1134     cache_entry.Tokens := 0;
1135   }
1136
1137   action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") {
1138     // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1139     assert(is_valid(cache_entry));
1140     if (cache_entry.Tokens > 0) {
1141       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1142         out_msg.Address := address;
1143         if (cache_entry.Tokens > (max_tokens() / 2)) {
1144           out_msg.Type := CoherenceResponseType:DATA_OWNER;
1145         } else {
1146           out_msg.Type := CoherenceResponseType:ACK;
1147         }
1148         out_msg.Sender := machineID;
1149         out_msg.Destination.add(persistentTable.findSmallest(address));
1150         assert(cache_entry.Tokens >= 1);
1151         out_msg.Tokens := cache_entry.Tokens;
1152         out_msg.DataBlk := cache_entry.DataBlk;
1153         out_msg.MessageSize := MessageSizeType:Response_Control;
1154       }
1155     }
1156     cache_entry.Tokens := 0;
1157   }
1158
1159   action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
1160     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1161     assert(is_valid(cache_entry));
1162     assert(cache_entry.Tokens > 0);
1163     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1164       out_msg.Address := address;
1165       out_msg.Type := CoherenceResponseType:DATA_OWNER;
1166       out_msg.Sender := machineID;
1167       out_msg.Destination.add(persistentTable.findSmallest(address));
1168       assert(cache_entry.Tokens > (max_tokens() / 2));
1169       out_msg.Tokens := cache_entry.Tokens;
1170       out_msg.DataBlk := cache_entry.DataBlk;
1171       out_msg.Dirty := cache_entry.Dirty;
1172       out_msg.MessageSize := MessageSizeType:Response_Data;
1173     }
1174     cache_entry.Tokens := 0;
1175   }
1176
1177   action(f_sendAckWithAllButNorOneTokens, "f", desc="Send ack with all our tokens but one to starver.") {
1178     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1179     assert(is_valid(cache_entry));
1180     assert(cache_entry.Tokens > 0);
1181     if (cache_entry.Tokens > 1) {
1182       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1183         out_msg.Address := address;
1184         if (cache_entry.Tokens > (max_tokens() / 2)) {
1185           out_msg.Type := CoherenceResponseType:DATA_OWNER;
1186         } else {
1187           out_msg.Type := CoherenceResponseType:ACK;
1188         }
1189         out_msg.Sender := machineID;
1190         out_msg.Destination.add(persistentTable.findSmallest(address));
1191         assert(cache_entry.Tokens >= 1);
1192         if (cache_entry.Tokens > N_tokens) {
1193           out_msg.Tokens := cache_entry.Tokens - N_tokens;
1194         } else {
1195           out_msg.Tokens := cache_entry.Tokens - 1;
1196         }
1197         out_msg.DataBlk := cache_entry.DataBlk;
1198         out_msg.MessageSize := MessageSizeType:Response_Control;
1199       }
1200     }
1201     if (cache_entry.Tokens > N_tokens) {
1202       cache_entry.Tokens := N_tokens;
1203     } else {
1204       cache_entry.Tokens := 1;
1205     }
1206   }
1207
1208   action(ff_sendDataWithAllButNorOneTokens, "\f", desc="Send data and out tokens but one to starver") {
1209     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1210     assert(is_valid(cache_entry));
1211     assert(cache_entry.Tokens > ((max_tokens() / 2) + 1));
1212     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1213         out_msg.Address := address;
1214         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1215         out_msg.Sender := machineID;
1216         out_msg.Destination.add(persistentTable.findSmallest(address));
1217         if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1218           out_msg.Tokens := cache_entry.Tokens - N_tokens;
1219         } else {
1220           out_msg.Tokens := cache_entry.Tokens - 1;
1221         }
1222         assert(out_msg.Tokens > (max_tokens() / 2));
1223         out_msg.DataBlk := cache_entry.DataBlk;
1224         out_msg.Dirty := cache_entry.Dirty;
1225         out_msg.MessageSize := MessageSizeType:Response_Data;
1226     }
1227     if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1228       cache_entry.Tokens := N_tokens;
1229     } else {
1230       cache_entry.Tokens := 1;
1231     }
1232   }
1233
1234   action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") {
1235     assert(is_valid(cache_entry));
1236     assert(cache_entry.Tokens == ((max_tokens() / 2) + 1));
1237     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1238         out_msg.Address := address;
1239         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1240         out_msg.Sender := machineID;
1241         out_msg.Destination.add(persistentTable.findSmallest(address));
1242         out_msg.Tokens := cache_entry.Tokens;
1243         assert(out_msg.Tokens > (max_tokens() / 2));
1244         out_msg.DataBlk := cache_entry.DataBlk;
1245         out_msg.Dirty := cache_entry.Dirty;
1246         out_msg.MessageSize := MessageSizeType:Response_Data;
1247     }
1248     cache_entry.Tokens := 0;
1249   }
1250
1251   action(g_bounceResponseToStarver, "g", desc="Redirect response to starving processor") {
1252     // assert(persistentTable.isLocked(address));
1253
1254     peek(responseNetwork_in, ResponseMsg) {
1255       // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1256       // FIXME, should use a 3rd vnet in some cases
1257       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
1258         out_msg.Address := address;
1259         out_msg.Type := in_msg.Type;
1260         out_msg.Sender := machineID;
1261         out_msg.Destination.add(persistentTable.findSmallest(address));
1262         out_msg.Tokens := in_msg.Tokens;
1263         out_msg.DataBlk := in_msg.DataBlk;
1264         out_msg.Dirty := in_msg.Dirty;
1265         out_msg.MessageSize := in_msg.MessageSize;
1266       }
1267     }
1268   }
1269
1270
1271   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
1272     assert(is_valid(cache_entry));
1273     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1274             address, cache_entry.DataBlk);
1275
1276     sequencer.readCallback(address,
1277                            GenericMachineType:L1Cache,
1278                            cache_entry.DataBlk);
1279
1280   }
1281
1282   action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
1283     assert(is_valid(cache_entry));
1284     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1285             address, cache_entry.DataBlk);
1286     peek(responseNetwork_in, ResponseMsg) {
1287
1288       sequencer.readCallback(address,
1289                              getNondirectHitMachType(address, in_msg.Sender),
1290                              cache_entry.DataBlk);
1291
1292     }
1293   }
1294
1295   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
1296     assert(is_valid(cache_entry));
1297     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1298             address, cache_entry.DataBlk);
1299
1300     sequencer.writeCallback(address,
1301                             GenericMachineType:L1Cache,
1302                             cache_entry.DataBlk);
1303
1304     cache_entry.Dirty := true;
1305     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1306   }
1307
1308   action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
1309     assert(is_valid(cache_entry));
1310     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1311             address, cache_entry.DataBlk);
1312     peek(responseNetwork_in, ResponseMsg) {
1313
1314       sequencer.writeCallback(address,
1315                               getNondirectHitMachType(address, in_msg.Sender),
1316                               cache_entry.DataBlk);
1317
1318     }
1319     cache_entry.Dirty := true;
1320     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1321   }
1322
1323   action(i_allocateTBE, "i", desc="Allocate TBE") {
1324     check_allocate(L1_TBEs);
1325     L1_TBEs.allocate(address);
1326     set_tbe(L1_TBEs[address]);
1327     tbe.IssueCount := 0;
1328     peek(mandatoryQueue_in, CacheMsg) {
1329       tbe.PC := in_msg.ProgramCounter;
1330       tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
1331       if (in_msg.Type == CacheRequestType:ATOMIC) {
1332         tbe.IsAtomic := true;
1333       }
1334       tbe.Prefetch := in_msg.Prefetch;
1335       tbe.AccessMode := in_msg.AccessMode;
1336     }
1337     tbe.IssueTime := get_time();
1338   }
1339
1340   action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
1341     peek(mandatoryQueue_in, CacheMsg) {
1342       APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1343     }
1344   }
1345
1346   action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
1347     if (reissueTimerTable.isSet(address)) {
1348       reissueTimerTable.unset(address);
1349     }
1350   }
1351
1352   action(jj_unsetUseTimer, "\j", desc="Unset use timer.") {
1353     useTimerTable.unset(address);
1354   }
1355
1356   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
1357     mandatoryQueue_in.dequeue();
1358   }
1359
1360   action(l_popPersistentQueue, "l", desc="Pop persistent queue.") {
1361     persistentNetwork_in.dequeue();
1362   }
1363
1364   action(m_popRequestQueue, "m", desc="Pop request queue.") {
1365     requestNetwork_in.dequeue();
1366   }
1367
1368   action(n_popResponseQueue, "n", desc="Pop response queue") {
1369     responseNetwork_in.dequeue();
1370   }
1371
1372   action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
1373     useTimerTable.set(address, 50);
1374   }
1375
1376   action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
1377     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1378        out_msg.Address := address;
1379        out_msg.Type := CoherenceResponseType:INV;
1380        out_msg.Tokens := 0;
1381        out_msg.Sender := machineID;
1382
1383        out_msg.Destination.add(mapAddressToRange(address,
1384                                                  MachineType:L2Cache,
1385                                                  l2_select_low_bit,
1386                                                  l2_select_num_bits));
1387
1388        out_msg.MessageSize := MessageSizeType:Response_Control;
1389     }
1390   }
1391
1392
1393   action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
1394     peek(responseNetwork_in, ResponseMsg) {
1395       assert(is_valid(cache_entry));
1396       assert(in_msg.Tokens != 0);
1397       DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
1398               in_msg.Address, in_msg.Tokens);
1399       cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
1400       DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
1401
1402       if (cache_entry.Dirty == false && in_msg.Dirty) {
1403         cache_entry.Dirty := true;
1404       }
1405     }
1406   }
1407
1408   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1409
1410     assert(is_valid(tbe));
1411     if (tbe.WentPersistent) {
1412       // assert(starving == true);
1413       outstandingRequests := outstandingRequests - 1;
1414       enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
1415         out_msg.Address := address;
1416         out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
1417         out_msg.Requestor := machineID;
1418         out_msg.Destination.broadcast(MachineType:L1Cache);
1419
1420         //
1421         // Currently the configuration system limits the system to only one
1422         // chip.  Therefore, if we assume one shared L2 cache, then only one
1423         // pertinent L2 cache exist.
1424         //
1425         //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
1426
1427         out_msg.Destination.add(mapAddressToRange(address,
1428                                                   MachineType:L2Cache,
1429                                                   l2_select_low_bit,
1430                                                   l2_select_num_bits));
1431
1432         out_msg.Destination.add(map_Address_to_Directory(address));
1433         out_msg.MessageSize := MessageSizeType:Persistent_Control;
1434       }
1435       starving := false;
1436     }
1437
1438     // Update average latency
1439     if (tbe.IssueCount <= 1) {
1440       if (tbe.ExternalResponse == true) {
1441         updateAverageLatencyEstimate(time_to_int(get_time()) - time_to_int(tbe.IssueTime));
1442       }
1443     }
1444
1445     // Profile
1446     //if (tbe.WentPersistent) {
1447     //  profile_token_retry(address, tbe.AccessType, 2);
1448     //}
1449     //else {
1450     //  profile_token_retry(address, tbe.AccessType, 1);
1451     //}
1452
1453     //profile_token_retry(address, tbe.AccessType, tbe.IssueCount);
1454     L1_TBEs.deallocate(address);
1455     unset_tbe();
1456   }
1457
1458   action(t_sendAckWithCollectedTokens, "t", desc="Send ack with the tokens we've collected thus far.") {
1459     assert(is_valid(cache_entry));
1460     if (cache_entry.Tokens > 0) {
1461       peek(requestNetwork_in, RequestMsg) {
1462         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1463           out_msg.Address := address;
1464           if (cache_entry.Tokens > (max_tokens() / 2)) {
1465             out_msg.Type := CoherenceResponseType:DATA_OWNER;
1466           } else {
1467             out_msg.Type := CoherenceResponseType:ACK;
1468           }
1469           out_msg.Sender := machineID;
1470           out_msg.Destination.add(in_msg.Requestor);
1471           assert(cache_entry.Tokens >= 1);
1472           out_msg.Tokens := cache_entry.Tokens;
1473           out_msg.DataBlk := cache_entry.DataBlk;
1474           out_msg.MessageSize := MessageSizeType:Response_Control;
1475         }
1476       }
1477     }
1478     cache_entry.Tokens := 0;
1479   }
1480
1481   action(u_writeDataToCache, "u", desc="Write data to cache") {
1482     peek(responseNetwork_in, ResponseMsg) {
1483       assert(is_valid(cache_entry));
1484       cache_entry.DataBlk := in_msg.DataBlk;
1485       if (cache_entry.Dirty == false && in_msg.Dirty) {
1486         cache_entry.Dirty := in_msg.Dirty;
1487       }
1488
1489     }
1490   }
1491
1492   action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1493     assert(getTokens(cache_entry) == 0);
1494     if (L1DcacheMemory.isTagPresent(address)) {
1495       L1DcacheMemory.deallocate(address);
1496     } else {
1497       L1IcacheMemory.deallocate(address);
1498     }
1499     unset_cache_entry();
1500   }
1501
1502   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1503     if (is_valid(cache_entry)) {
1504     } else {
1505       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
1506     }
1507   }
1508
1509   action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
1510     if (is_valid(cache_entry)) {
1511     } else {
1512       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
1513     }
1514   }
1515
1516   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1517     peek(mandatoryQueue_in, CacheMsg) {
1518       if (L1DcacheMemory.isTagPresent(address)) {
1519         L1DcacheMemory.profileMiss(in_msg);
1520       } else {
1521         L1IcacheMemory.profileMiss(in_msg);
1522       }
1523     }
1524   }
1525
1526   action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
1527     peek(responseNetwork_in, ResponseMsg) {
1528       assert(is_valid(cache_entry));
1529       assert(cache_entry.DataBlk == in_msg.DataBlk);
1530     }
1531   }
1532
1533   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1534     peek(mandatoryQueue_in, CacheMsg) {
1535       APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1536     }
1537     stall_and_wait(mandatoryQueue_in, address);
1538   }
1539
1540   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1541     wake_up_dependents(address);
1542   }
1543
1544   action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1545     wake_up_all_dependents();
1546   }
1547
1548   //*****************************************************
1549   // TRANSITIONS
1550   //*****************************************************
1551
1552   // Transitions for Load/Store/L2_Replacement from transient states
1553   transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
1554     ta_traceStalledAddress;
1555     zz_stallAndWaitMandatoryQueue;
1556   }
1557
1558   transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
1559     zz_stallAndWaitMandatoryQueue;
1560   }
1561
1562   transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
1563     zz_stallAndWaitMandatoryQueue;
1564   }
1565
1566
1567   // Lockdowns
1568   transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
1569     l_popPersistentQueue;
1570   }
1571
1572   // Transitions from NP
1573   transition(NP, Load, IS) {
1574     ii_allocateL1DCacheBlock;
1575     i_allocateTBE;
1576     a_issueReadRequest;
1577     uu_profileMiss;
1578     k_popMandatoryQueue;
1579   }
1580
1581   transition(NP, Ifetch, IS) {
1582     pp_allocateL1ICacheBlock;
1583     i_allocateTBE;
1584     a_issueReadRequest;
1585     uu_profileMiss;
1586     k_popMandatoryQueue;
1587   }
1588
1589   transition(NP, {Store, Atomic}, IM) {
1590     ii_allocateL1DCacheBlock;
1591     i_allocateTBE;
1592     b_issueWriteRequest;
1593     uu_profileMiss;
1594     k_popMandatoryQueue;
1595   }
1596
1597   transition(NP, {Ack, Data_Shared, Data_Owner, Data_All_Tokens}) {
1598     bb_bounceResponse;
1599     n_popResponseQueue;
1600   }
1601
1602   transition(NP, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) {
1603     m_popRequestQueue;
1604   }
1605
1606   transition(NP, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1607     l_popPersistentQueue;
1608   }
1609
1610   // Transitions from Idle
1611   transition(I, Load, IS) {
1612     i_allocateTBE;
1613     a_issueReadRequest;
1614     uu_profileMiss;
1615     k_popMandatoryQueue;
1616   }
1617
1618   transition(I, Ifetch, IS) {
1619     i_allocateTBE;
1620     a_issueReadRequest;
1621     uu_profileMiss;
1622     k_popMandatoryQueue;
1623   }
1624
1625   transition(I, {Store, Atomic}, IM) {
1626     i_allocateTBE;
1627     b_issueWriteRequest;
1628     uu_profileMiss;
1629     k_popMandatoryQueue;
1630   }
1631
1632   transition(I, L1_Replacement) {
1633     ta_traceStalledAddress;
1634     tr_tokenReplacement;
1635     gg_deallocateL1CacheBlock;
1636     ka_wakeUpAllDependents;
1637   }
1638
1639   transition(I, {Transient_GETX, Transient_Local_GETX}) {
1640     t_sendAckWithCollectedTokens;
1641     m_popRequestQueue;
1642   }
1643
1644   transition(I, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1645     m_popRequestQueue;
1646   }
1647
1648   transition(I, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1649     e_sendAckWithCollectedTokens;
1650     l_popPersistentQueue;
1651   }
1652
1653   transition(I_L, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}) {
1654     l_popPersistentQueue;
1655   }
1656
1657   transition(I, Ack) {
1658     q_updateTokensFromResponse;
1659     n_popResponseQueue;
1660   }
1661
1662   transition(I, Data_Shared, S) {
1663     u_writeDataToCache;
1664     q_updateTokensFromResponse;
1665     n_popResponseQueue;
1666   }
1667
1668   transition(I, Data_Owner, O) {
1669     u_writeDataToCache;
1670     q_updateTokensFromResponse;
1671     n_popResponseQueue;
1672   }
1673
1674   transition(I, Data_All_Tokens, M) {
1675     u_writeDataToCache;
1676     q_updateTokensFromResponse;
1677     n_popResponseQueue;
1678   }
1679
1680   // Transitions from Shared
1681   transition({S, SM, S_L, SM_L}, {Load, Ifetch}) {
1682     h_load_hit;
1683     k_popMandatoryQueue;
1684   }
1685
1686   transition(S, {Store, Atomic}, SM) {
1687     i_allocateTBE;
1688     b_issueWriteRequest;
1689     uu_profileMiss;
1690     k_popMandatoryQueue;
1691   }
1692
1693   transition(S, L1_Replacement, I) {
1694     ta_traceStalledAddress;
1695     cc_sharedReplacement; // Only needed in some cases
1696     gg_deallocateL1CacheBlock;
1697     ka_wakeUpAllDependents;
1698   }
1699
1700   transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
1701     t_sendAckWithCollectedTokens;
1702     p_informL2AboutTokenLoss;
1703     m_popRequestQueue;
1704   }
1705
1706   // only owner responds to non-local requests
1707   transition(S, Transient_GETS) {
1708     m_popRequestQueue;
1709   }
1710
1711   transition(S, Transient_Local_GETS) {
1712     d_sendDataWithToken;
1713     m_popRequestQueue;
1714   }
1715
1716   transition(S, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1717     m_popRequestQueue;
1718   }
1719
1720   transition({S, S_L}, Persistent_GETX, I_L) {
1721     e_sendAckWithCollectedTokens;
1722     p_informL2AboutTokenLoss;
1723     l_popPersistentQueue;
1724   }
1725
1726   transition(S, {Persistent_GETS, Persistent_GETS_Last_Token}, S_L) {
1727     f_sendAckWithAllButNorOneTokens;
1728     l_popPersistentQueue;
1729   }
1730
1731   transition(S_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1732     l_popPersistentQueue;
1733   }
1734
1735   transition(S, Ack) {
1736     q_updateTokensFromResponse;
1737     n_popResponseQueue;
1738   }
1739
1740   transition(S, Data_Shared) {
1741     w_assertIncomingDataAndCacheDataMatch;
1742     q_updateTokensFromResponse;
1743     n_popResponseQueue;
1744   }
1745
1746   transition(S, Data_Owner, O) {
1747     w_assertIncomingDataAndCacheDataMatch;
1748     q_updateTokensFromResponse;
1749     n_popResponseQueue;
1750   }
1751
1752   transition(S, Data_All_Tokens, M) {
1753     w_assertIncomingDataAndCacheDataMatch;
1754     q_updateTokensFromResponse;
1755     n_popResponseQueue;
1756   }
1757
1758   // Transitions from Owned
1759   transition({O, OM}, {Load, Ifetch}) {
1760     h_load_hit;
1761     k_popMandatoryQueue;
1762   }
1763
1764   transition(O, {Store, Atomic}, OM) {
1765     i_allocateTBE;
1766     b_issueWriteRequest;
1767     uu_profileMiss;
1768     k_popMandatoryQueue;
1769   }
1770
1771   transition(O, L1_Replacement, I) {
1772     ta_traceStalledAddress;
1773     c_ownedReplacement;
1774     gg_deallocateL1CacheBlock;
1775     ka_wakeUpAllDependents;
1776   }
1777
1778   transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
1779     dd_sendDataWithAllTokens;
1780     p_informL2AboutTokenLoss;
1781     m_popRequestQueue;
1782   }
1783
1784   transition(O, Persistent_GETX, I_L) {
1785     ee_sendDataWithAllTokens;
1786     p_informL2AboutTokenLoss;
1787     l_popPersistentQueue;
1788   }
1789
1790   transition(O, Persistent_GETS, S_L) {
1791     ff_sendDataWithAllButNorOneTokens;
1792     l_popPersistentQueue;
1793   }
1794
1795   transition(O, Persistent_GETS_Last_Token, I_L) {
1796     fo_sendDataWithOwnerToken;
1797     l_popPersistentQueue;
1798   }
1799
1800   transition(O, Transient_GETS) {
1801     d_sendDataWithToken;
1802     m_popRequestQueue;
1803   }
1804
1805   transition(O, Transient_Local_GETS) {
1806     d_sendDataWithToken;
1807     m_popRequestQueue;
1808   }
1809
1810   // ran out of tokens, wait for it to go persistent
1811   transition(O, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1812     m_popRequestQueue;
1813   }
1814
1815   transition(O, Ack) {
1816     q_updateTokensFromResponse;
1817     n_popResponseQueue;
1818   }
1819
1820   transition(O, Ack_All_Tokens, M) {
1821     q_updateTokensFromResponse;
1822     n_popResponseQueue;
1823   }
1824
1825   transition(O, Data_Shared) {
1826     w_assertIncomingDataAndCacheDataMatch;
1827     q_updateTokensFromResponse;
1828     n_popResponseQueue;
1829   }
1830
1831   transition(O, Data_All_Tokens, M) {
1832     w_assertIncomingDataAndCacheDataMatch;
1833     q_updateTokensFromResponse;
1834     n_popResponseQueue;
1835   }
1836
1837   // Transitions from Modified
1838   transition({MM, MM_W}, {Load, Ifetch}) {
1839     h_load_hit;
1840     k_popMandatoryQueue;
1841   }
1842
1843   transition({MM_W}, {Store, Atomic}) {
1844     hh_store_hit;
1845     k_popMandatoryQueue;
1846   }
1847
1848   transition(MM, Store) {
1849     hh_store_hit;
1850     k_popMandatoryQueue;
1851   }
1852
1853   transition(MM, Atomic, M) {
1854     hh_store_hit;
1855     k_popMandatoryQueue;
1856   }
1857
1858   transition(MM, L1_Replacement, I) {
1859     ta_traceStalledAddress;
1860     c_ownedReplacement;
1861     gg_deallocateL1CacheBlock;
1862     ka_wakeUpAllDependents;
1863   }
1864
1865   transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
1866     dd_sendDataWithAllTokens;
1867     p_informL2AboutTokenLoss;
1868     m_popRequestQueue;
1869   }
1870
1871   transition({MM_W}, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1872     m_popRequestQueue;
1873   }
1874
1875   // Implement the migratory sharing optimization, even for persistent requests
1876   transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
1877     ee_sendDataWithAllTokens;
1878     p_informL2AboutTokenLoss;
1879     l_popPersistentQueue;
1880   }
1881
1882   // ignore persistent requests in lockout period
1883   transition(MM_W, {Persistent_GETX, Persistent_GETS}) {
1884     l_popPersistentQueue;
1885   }
1886
1887   transition(MM_W, Use_TimeoutNoStarvers, MM) {
1888     s_deallocateTBE;
1889     jj_unsetUseTimer;
1890     kd_wakeUpDependents;
1891   }
1892
1893   transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
1894     s_deallocateTBE;
1895     jj_unsetUseTimer;
1896     kd_wakeUpDependents;
1897   }
1898
1899   // Transitions from Dirty Exclusive
1900   transition({M, M_W}, {Load, Ifetch}) {
1901     h_load_hit;
1902     k_popMandatoryQueue;
1903   }
1904
1905   transition(M, Store, MM) {
1906     hh_store_hit;
1907     k_popMandatoryQueue;
1908   }
1909
1910   transition(M, Atomic) {
1911     hh_store_hit;
1912     k_popMandatoryQueue;
1913   }
1914
1915   transition(M_W, Store, MM_W) {
1916     hh_store_hit;
1917     k_popMandatoryQueue;
1918   }
1919
1920   transition(M_W, Atomic) {
1921     hh_store_hit;
1922     k_popMandatoryQueue;
1923   }
1924
1925   transition(M, L1_Replacement, I) {
1926     ta_traceStalledAddress;
1927     c_ownedReplacement;
1928     gg_deallocateL1CacheBlock;
1929     ka_wakeUpAllDependents;
1930   }
1931
1932   transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
1933     dd_sendDataWithAllTokens;
1934     p_informL2AboutTokenLoss;
1935     m_popRequestQueue;
1936   }
1937
1938   transition(M, Transient_Local_GETS, O) {
1939     d_sendDataWithToken;
1940     m_popRequestQueue;
1941   }
1942
1943   transition(M, Transient_GETS, O) {
1944     d_sendDataWithNTokenIfAvail;
1945     m_popRequestQueue;
1946   }
1947
1948   transition(M_W, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1949     m_popRequestQueue;
1950   }
1951
1952   transition(M, Persistent_GETX, I_L) {
1953     ee_sendDataWithAllTokens;
1954     p_informL2AboutTokenLoss;
1955     l_popPersistentQueue;
1956   }
1957
1958   transition(M, Persistent_GETS, S_L) {
1959     ff_sendDataWithAllButNorOneTokens;
1960     l_popPersistentQueue;
1961   }
1962
1963   // ignore persistent requests in lockout period
1964   transition(M_W, {Persistent_GETX, Persistent_GETS}) {
1965     l_popPersistentQueue;
1966   }
1967
1968   transition(M_W, Use_TimeoutStarverS, S_L) {
1969     s_deallocateTBE;
1970     ff_sendDataWithAllButNorOneTokens;
1971     jj_unsetUseTimer;
1972   }
1973
1974   // someone unlocked during timeout
1975   transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
1976     s_deallocateTBE;
1977     jj_unsetUseTimer;
1978     kd_wakeUpDependents;
1979   }
1980
1981   transition(M_W, Use_TimeoutStarverX, I_L) {
1982     s_deallocateTBE;
1983     ee_sendDataWithAllTokens;
1984     p_informL2AboutTokenLoss;
1985     jj_unsetUseTimer;
1986   }
1987
1988
1989
1990   // migratory
1991   transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
1992     s_deallocateTBE;
1993     ee_sendDataWithAllTokens;
1994     p_informL2AboutTokenLoss;
1995     jj_unsetUseTimer;
1996
1997   }
1998
1999
2000   // Transient_GETX and Transient_GETS in transient states
2001   transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2002     m_popRequestQueue;  // Even if we have the data, we can pretend we don't have it yet.
2003   }
2004
2005   transition(IS, {Transient_GETX, Transient_Local_GETX}) {
2006     t_sendAckWithCollectedTokens;
2007     m_popRequestQueue;
2008   }
2009
2010   transition(IS, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2011     m_popRequestQueue;
2012   }
2013
2014   transition(IS, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IS_L) {
2015     e_sendAckWithCollectedTokens;
2016     l_popPersistentQueue;
2017   }
2018
2019   transition(IS_L, {Persistent_GETX, Persistent_GETS}) {
2020     l_popPersistentQueue;
2021   }
2022
2023   transition(IM, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IM_L) {
2024     e_sendAckWithCollectedTokens;
2025     l_popPersistentQueue;
2026   }
2027
2028   transition(IM_L, {Persistent_GETX, Persistent_GETS}) {
2029     l_popPersistentQueue;
2030   }
2031
2032   transition({SM, SM_L}, Persistent_GETX, IM_L) {
2033     e_sendAckWithCollectedTokens;
2034     l_popPersistentQueue;
2035   }
2036
2037   transition(SM, {Persistent_GETS, Persistent_GETS_Last_Token}, SM_L) {
2038     f_sendAckWithAllButNorOneTokens;
2039     l_popPersistentQueue;
2040   }
2041
2042   transition(SM_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
2043     l_popPersistentQueue;
2044   }
2045
2046   transition(OM, Persistent_GETX, IM_L) {
2047     ee_sendDataWithAllTokens;
2048     l_popPersistentQueue;
2049   }
2050
2051   transition(OM, Persistent_GETS, SM_L) {
2052     ff_sendDataWithAllButNorOneTokens;
2053     l_popPersistentQueue;
2054   }
2055
2056   transition(OM, Persistent_GETS_Last_Token, IM_L) {
2057     fo_sendDataWithOwnerToken;
2058     l_popPersistentQueue;
2059   }
2060
2061   // Transitions from IM/SM
2062
2063   transition({IM, SM}, Ack) {
2064     q_updateTokensFromResponse;
2065     n_popResponseQueue;
2066   }
2067
2068   transition(IM, Data_Shared, SM) {
2069     u_writeDataToCache;
2070     q_updateTokensFromResponse;
2071     n_popResponseQueue;
2072   }
2073
2074   transition(IM, Data_Owner, OM) {
2075     u_writeDataToCache;
2076     q_updateTokensFromResponse;
2077     n_popResponseQueue;
2078   }
2079
2080   transition(IM, Data_All_Tokens, MM_W) {
2081     u_writeDataToCache;
2082     q_updateTokensFromResponse;
2083     xx_external_store_hit;
2084     o_scheduleUseTimeout;
2085     j_unsetReissueTimer;
2086     n_popResponseQueue;
2087     kd_wakeUpDependents;
2088   }
2089
2090   transition(SM, Data_Shared) {
2091     w_assertIncomingDataAndCacheDataMatch;
2092     q_updateTokensFromResponse;
2093     n_popResponseQueue;
2094   }
2095
2096   transition(SM, Data_Owner, OM) {
2097     w_assertIncomingDataAndCacheDataMatch;
2098     q_updateTokensFromResponse;
2099     n_popResponseQueue;
2100   }
2101
2102   transition(SM, Data_All_Tokens, MM_W) {
2103     w_assertIncomingDataAndCacheDataMatch;
2104     q_updateTokensFromResponse;
2105     xx_external_store_hit;
2106     o_scheduleUseTimeout;
2107     j_unsetReissueTimer;
2108     n_popResponseQueue;
2109     kd_wakeUpDependents;
2110   }
2111
2112   transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens.  We give them up here to avoid livelock
2113     t_sendAckWithCollectedTokens;
2114     m_popRequestQueue;
2115   }
2116
2117   transition({IM, SM}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2118     m_popRequestQueue;
2119   }
2120
2121   transition({IM, SM}, Request_Timeout) {
2122     j_unsetReissueTimer;
2123     b_issueWriteRequest;
2124   }
2125
2126   // Transitions from OM
2127
2128   transition(OM, Ack) {
2129     q_updateTokensFromResponse;
2130     n_popResponseQueue;
2131   }
2132
2133   transition(OM, Ack_All_Tokens, MM_W) {
2134     q_updateTokensFromResponse;
2135     xx_external_store_hit;
2136     o_scheduleUseTimeout;
2137     j_unsetReissueTimer;
2138     n_popResponseQueue;
2139     kd_wakeUpDependents;
2140   }
2141
2142   transition(OM, Data_Shared) {
2143     w_assertIncomingDataAndCacheDataMatch;
2144     q_updateTokensFromResponse;
2145     n_popResponseQueue;
2146   }
2147
2148   transition(OM, Data_All_Tokens, MM_W) {
2149     w_assertIncomingDataAndCacheDataMatch;
2150     q_updateTokensFromResponse;
2151     xx_external_store_hit;
2152     o_scheduleUseTimeout;
2153     j_unsetReissueTimer;
2154     n_popResponseQueue;
2155     kd_wakeUpDependents;
2156   }
2157
2158   transition(OM, Request_Timeout) {
2159     j_unsetReissueTimer;
2160     b_issueWriteRequest;
2161   }
2162
2163   // Transitions from IS
2164
2165   transition(IS, Ack) {
2166     q_updateTokensFromResponse;
2167     n_popResponseQueue;
2168   }
2169
2170   transition(IS, Data_Shared, S) {
2171     u_writeDataToCache;
2172     q_updateTokensFromResponse;
2173     x_external_load_hit;
2174     s_deallocateTBE;
2175     j_unsetReissueTimer;
2176     n_popResponseQueue;
2177     kd_wakeUpDependents;
2178   }
2179
2180   transition(IS, Data_Owner, O) {
2181     u_writeDataToCache;
2182     q_updateTokensFromResponse;
2183     x_external_load_hit;
2184     s_deallocateTBE;
2185     j_unsetReissueTimer;
2186     n_popResponseQueue;
2187     kd_wakeUpDependents;
2188   }
2189
2190   transition(IS, Data_All_Tokens, M_W) {
2191     u_writeDataToCache;
2192     q_updateTokensFromResponse;
2193     x_external_load_hit;
2194     o_scheduleUseTimeout;
2195     j_unsetReissueTimer;
2196     n_popResponseQueue;
2197     kd_wakeUpDependents;
2198   }
2199
2200   transition(IS, Request_Timeout) {
2201     j_unsetReissueTimer;
2202     a_issueReadRequest;
2203   }
2204
2205   // Transitions from I_L
2206
2207   transition(I_L, Load, IS_L) {
2208     ii_allocateL1DCacheBlock;
2209     i_allocateTBE;
2210     a_issueReadRequest;
2211     uu_profileMiss;
2212     k_popMandatoryQueue;
2213   }
2214
2215   transition(I_L, Ifetch, IS_L) {
2216     pp_allocateL1ICacheBlock;
2217     i_allocateTBE;
2218     a_issueReadRequest;
2219     uu_profileMiss;
2220     k_popMandatoryQueue;
2221   }
2222
2223   transition(I_L, {Store, Atomic}, IM_L) {
2224     ii_allocateL1DCacheBlock;
2225     i_allocateTBE;
2226     b_issueWriteRequest;
2227     uu_profileMiss;
2228     k_popMandatoryQueue;
2229   }
2230
2231
2232   // Transitions from S_L
2233
2234   transition(S_L, {Store, Atomic}, SM_L) {
2235     i_allocateTBE;
2236     b_issueWriteRequest;
2237     uu_profileMiss;
2238     k_popMandatoryQueue;
2239   }
2240
2241   // Other transitions from *_L states
2242
2243   transition({I_L, IM_L, IS_L, S_L, SM_L}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS, Transient_GETX, Transient_Local_GETX}) {
2244     m_popRequestQueue;
2245   }
2246
2247   transition({I_L, IM_L, IS_L, S_L, SM_L}, Ack) {
2248     g_bounceResponseToStarver;
2249     n_popResponseQueue;
2250   }
2251
2252   transition({I_L, IM_L, S_L, SM_L}, {Data_Shared, Data_Owner}) {
2253     g_bounceResponseToStarver;
2254     n_popResponseQueue;
2255   }
2256
2257   transition({I_L, S_L}, Data_All_Tokens) {
2258     g_bounceResponseToStarver;
2259     n_popResponseQueue;
2260   }
2261
2262   transition(IS_L, Request_Timeout) {
2263     j_unsetReissueTimer;
2264     a_issueReadRequest;
2265   }
2266
2267   transition({IM_L, SM_L}, Request_Timeout) {
2268     j_unsetReissueTimer;
2269     b_issueWriteRequest;
2270   }
2271
2272   // Opportunisticly Complete the memory operation in the following
2273   // cases.  Note: these transitions could just use
2274   // g_bounceResponseToStarver, but if we have the data and tokens, we
2275   // might as well complete the memory request while we have the
2276   // chance (and then immediately forward on the data)
2277
2278   transition(IM_L, Data_All_Tokens, MM_W) {
2279     u_writeDataToCache;
2280     q_updateTokensFromResponse;
2281     xx_external_store_hit;
2282     j_unsetReissueTimer;
2283     o_scheduleUseTimeout;
2284     n_popResponseQueue;
2285     kd_wakeUpDependents;
2286   }
2287
2288   transition(SM_L, Data_All_Tokens, S_L) {
2289     u_writeDataToCache;
2290     q_updateTokensFromResponse;
2291     xx_external_store_hit;
2292     ff_sendDataWithAllButNorOneTokens;
2293     s_deallocateTBE;
2294     j_unsetReissueTimer;
2295     n_popResponseQueue;
2296   }
2297
2298   transition(IS_L, Data_Shared, I_L) {
2299     u_writeDataToCache;
2300     q_updateTokensFromResponse;
2301     x_external_load_hit;
2302     s_deallocateTBE;
2303     e_sendAckWithCollectedTokens;
2304     p_informL2AboutTokenLoss;
2305     j_unsetReissueTimer;
2306     n_popResponseQueue;
2307   }
2308
2309   transition(IS_L, Data_Owner, I_L) {
2310     u_writeDataToCache;
2311     q_updateTokensFromResponse;
2312     x_external_load_hit;
2313     ee_sendDataWithAllTokens;
2314     s_deallocateTBE;
2315     p_informL2AboutTokenLoss;
2316     j_unsetReissueTimer;
2317     n_popResponseQueue;
2318   }
2319
2320   transition(IS_L, Data_All_Tokens, M_W) {
2321     u_writeDataToCache;
2322     q_updateTokensFromResponse;
2323     x_external_load_hit;
2324     j_unsetReissueTimer;
2325     o_scheduleUseTimeout;
2326     n_popResponseQueue;
2327     kd_wakeUpDependents;
2328   }
2329
2330
2331   // Own_Lock_or_Unlock
2332
2333   transition(I_L, Own_Lock_or_Unlock, I) {
2334     l_popPersistentQueue;
2335     kd_wakeUpDependents;
2336   }
2337
2338   transition(S_L, Own_Lock_or_Unlock, S) {
2339     l_popPersistentQueue;
2340     kd_wakeUpDependents;
2341   }
2342
2343   transition(IM_L, Own_Lock_or_Unlock, IM) {
2344     l_popPersistentQueue;
2345     kd_wakeUpDependents;
2346   }
2347
2348   transition(IS_L, Own_Lock_or_Unlock, IS) {
2349     l_popPersistentQueue;
2350     kd_wakeUpDependents;
2351   }
2352
2353   transition(SM_L, Own_Lock_or_Unlock, SM) {
2354     l_popPersistentQueue;
2355     kd_wakeUpDependents;
2356   }
2357 }
2358