3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $Id: MOESI_CMP_token-L1cache.sm 1.22 05/01/19 15:55:39-06:00 beckmann@s0-28.cs.wisc.edu $
35 machine(L1Cache, "Token protocol")
36 : Sequencer * sequencer,
37 CacheMemory * L1IcacheMemory,
38 CacheMemory * L1DcacheMemory,
39 int l2_select_num_bits,
42 Cycles l1_request_latency = 2,
43 Cycles l1_response_latency = 2,
44 int retry_threshold = 1,
45 Cycles fixed_timeout_latency = 100,
46 Cycles reissue_wakeup_latency = 10,
47 Cycles use_timeout_latency = 50,
49 bool dynamic_timeout_enabled = true,
50 bool no_mig_atomic = true,
54 // From this node's L1 cache TO the network
56 // a local L1 -> this L2 bank
57 MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false", vnet_type="response";
58 MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true", vnet_type="persistent";
59 // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
60 MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="request";
63 // To this node's L1 cache FROM the network
64 // a L2 bank -> this L1
65 MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false", vnet_type="response";
66 MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true", vnet_type="persistent";
67 // a L2 bank -> this L1
68 MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="request";
71 state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
73 NP, AccessPermission:Invalid, "NP", desc="Not Present";
74 I, AccessPermission:Invalid, "I", desc="Idle";
75 S, AccessPermission:Read_Only, "S", desc="Shared";
76 O, AccessPermission:Read_Only, "O", desc="Owned";
77 M, AccessPermission:Read_Only, "M", desc="Modified (dirty)";
78 MM, AccessPermission:Read_Write, "MM", desc="Modified (dirty and locally modified)";
79 M_W, AccessPermission:Read_Only, "M^W", desc="Modified (dirty), waiting";
80 MM_W, AccessPermission:Read_Write, "MM^W", desc="Modified (dirty and locally modified), waiting";
83 IM, AccessPermission:Busy, "IM", desc="Issued GetX";
84 SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have an old copy of the line";
85 OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
86 IS, AccessPermission:Busy, "IS", desc="Issued GetS";
89 I_L, AccessPermission:Busy, "I^L", desc="Invalid, Locked";
90 S_L, AccessPermission:Busy, "S^L", desc="Shared, Locked";
91 IM_L, AccessPermission:Busy, "IM^L", desc="Invalid, Locked, trying to go to Modified";
92 SM_L, AccessPermission:Busy, "SM^L", desc="Shared, Locked, trying to go to Modified";
93 IS_L, AccessPermission:Busy, "IS^L", desc="Invalid, Locked, trying to go to Shared";
97 enumeration(Event, desc="Cache events") {
98 Load, desc="Load request from the processor";
99 Ifetch, desc="I-fetch request from the processor";
100 Store, desc="Store request from the processor";
101 Atomic, desc="Atomic request from the processor";
102 L1_Replacement, desc="L1 Replacement";
105 Data_Shared, desc="Received a data message, we are now a sharer";
106 Data_Owner, desc="Received a data message, we are now the owner";
107 Data_All_Tokens, desc="Received a data message, we are now the owner, we now have all the tokens";
108 Ack, desc="Received an ack message";
109 Ack_All_Tokens, desc="Received an ack message, we now have all the tokens";
112 Transient_GETX, desc="A GetX from another processor";
113 Transient_Local_GETX, desc="A GetX from another processor";
114 Transient_GETS, desc="A GetS from another processor";
115 Transient_Local_GETS, desc="A GetS from another processor";
116 Transient_GETS_Last_Token, desc="A GetS from another processor";
117 Transient_Local_GETS_Last_Token, desc="A GetS from another processor";
119 // Lock/Unlock for distributed
120 Persistent_GETX, desc="Another processor has priority to read/write";
121 Persistent_GETS, desc="Another processor has priority to read";
122 Persistent_GETS_Last_Token, desc="Another processor has priority to read, no more tokens";
123 Own_Lock_or_Unlock, desc="This processor now has priority";
126 Request_Timeout, desc="Timeout";
127 Use_TimeoutStarverX, desc="Timeout";
128 Use_TimeoutStarverS, desc="Timeout";
129 Use_TimeoutNoStarvers, desc="Timeout";
130 Use_TimeoutNoStarvers_NoMig, desc="Timeout Don't Migrate";
136 structure(Entry, desc="...", interface="AbstractCacheEntry") {
137 State CacheState, desc="cache state";
138 bool Dirty, desc="Is the data dirty (different than memory)?";
139 int Tokens, desc="The number of tokens we're holding for the line";
140 DataBlock DataBlk, desc="data for the block";
145 structure(TBE, desc="...") {
146 Address address, desc="Physical address for this TBE";
147 State TBEState, desc="Transient state";
148 int IssueCount, default="0", desc="The number of times we've issued a request for this line.";
149 Address PC, desc="Program counter of request";
151 bool WentPersistent, default="false", desc="Request went persistent";
152 bool ExternalResponse, default="false", desc="Response came from an external controller";
153 bool IsAtomic, default="false", desc="Request was an atomic request";
155 AccessType AccessType, desc="Type of request (used for profiling)";
156 Time IssueTime, desc="Time the request was issued";
157 RubyAccessMode AccessMode, desc="user/supervisor access type";
158 PrefetchBit Prefetch, desc="Is this a prefetch request";
161 structure(TBETable, external="yes") {
163 void allocate(Address);
164 void deallocate(Address);
165 bool isPresent(Address);
168 structure(PersistentTable, external="yes") {
169 void persistentRequestLock(Address, MachineID, AccessType);
170 void persistentRequestUnlock(Address, MachineID);
171 bool okToIssueStarving(Address, MachineID);
172 MachineID findSmallest(Address);
173 AccessType typeOfSmallest(Address);
174 void markEntries(Address);
175 bool isLocked(Address);
176 int countStarvingForAddress(Address);
177 int countReadStarvingForAddress(Address);
180 void set_cache_entry(AbstractCacheEntry b);
181 void unset_cache_entry();
184 void wakeUpAllBuffers();
185 void wakeUpBuffers(Address a);
188 TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
190 MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
192 bool starving, default="false";
193 int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
195 PersistentTable persistentTable;
196 TimerTable useTimerTable;
197 TimerTable reissueTimerTable;
199 int outstandingRequests, default="0";
200 int outstandingPersistentRequests, default="0";
202 // Constant that provides hysteresis for calculated the estimated average
203 int averageLatencyHysteresis, default="(8)";
204 Cycles averageLatencyCounter,
205 default="(Cycles(500) << (*m_L1Cache_averageLatencyHysteresis_ptr))";
207 Cycles averageLatencyEstimate() {
208 DPRINTF(RubySlicc, "%d\n",
209 (averageLatencyCounter >> averageLatencyHysteresis));
210 //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
211 return averageLatencyCounter >> averageLatencyHysteresis;
214 void updateAverageLatencyEstimate(Cycles latency) {
215 DPRINTF(RubySlicc, "%d\n", latency);
217 // By subtracting the current average and then adding the most
218 // recent sample, we calculate an estimate of the recent average.
219 // If we simply used a running sum and divided by the total number
220 // of entries, the estimate of the average would adapt very slowly
221 // after the execution has run for a long time.
222 // averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
224 averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
227 Entry getCacheEntry(Address addr), return_by_pointer="yes" {
228 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
229 if(is_valid(L1Dcache_entry)) {
230 return L1Dcache_entry;
233 Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
234 return L1Icache_entry;
237 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
238 return getCacheEntry(addr).DataBlk;
241 Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
242 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
243 return L1Dcache_entry;
246 Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
247 Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
248 return L1Icache_entry;
251 int getTokens(Entry cache_entry) {
252 if (is_valid(cache_entry)) {
253 return cache_entry.Tokens;
258 State getState(TBE tbe, Entry cache_entry, Address addr) {
262 } else if (is_valid(cache_entry)) {
263 return cache_entry.CacheState;
265 if ((persistentTable.isLocked(addr) == true) && (persistentTable.findSmallest(addr) != machineID)) {
266 // Not in cache, in persistent table, but this processor isn't highest priority
274 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
275 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
278 assert(state != State:I);
279 assert(state != State:S);
280 assert(state != State:O);
281 assert(state != State:MM);
282 assert(state != State:M);
283 tbe.TBEState := state;
286 if (is_valid(cache_entry)) {
287 // Make sure the token count is in range
288 assert(cache_entry.Tokens >= 0);
289 assert(cache_entry.Tokens <= max_tokens());
290 assert(cache_entry.Tokens != (max_tokens() / 2));
292 if ((state == State:I_L) ||
293 (state == State:IM_L) ||
294 (state == State:IS_L)) {
295 // Make sure we have no tokens in the "Invalid, locked" states
296 assert(cache_entry.Tokens == 0);
298 // Make sure the line is locked
299 // assert(persistentTable.isLocked(addr));
301 // But we shouldn't have highest priority for it
302 // assert(persistentTable.findSmallest(addr) != id);
304 } else if ((state == State:S_L) ||
305 (state == State:SM_L)) {
306 assert(cache_entry.Tokens >= 1);
307 assert(cache_entry.Tokens < (max_tokens() / 2));
309 // Make sure the line is locked...
310 // assert(persistentTable.isLocked(addr));
312 // ...But we shouldn't have highest priority for it...
313 // assert(persistentTable.findSmallest(addr) != id);
315 // ...And it must be a GETS request
316 // assert(persistentTable.typeOfSmallest(addr) == AccessType:Read);
320 // If there is an entry in the persistent table of this block,
321 // this processor needs to have an entry in the table for this
322 // block, and that entry better be the smallest (highest
323 // priority). Otherwise, the state should have been one of
326 //if (persistentTable.isLocked(addr)) {
327 // assert(persistentTable.findSmallest(addr) == id);
331 // in M and E you have all the tokens
332 if (state == State:MM || state == State:M || state == State:MM_W || state == State:M_W) {
333 assert(cache_entry.Tokens == max_tokens());
336 // in NP you have no tokens
337 if (state == State:NP) {
338 assert(cache_entry.Tokens == 0);
341 // You have at least one token in S-like states
342 if (state == State:S || state == State:SM) {
343 assert(cache_entry.Tokens > 0);
346 // You have at least half the token in O-like states
347 if (state == State:O && state == State:OM) {
348 assert(cache_entry.Tokens > (max_tokens() / 2));
351 cache_entry.CacheState := state;
355 AccessPermission getAccessPermission(Address addr) {
356 TBE tbe := L1_TBEs[addr];
358 return L1Cache_State_to_permission(tbe.TBEState);
361 Entry cache_entry := getCacheEntry(addr);
362 if(is_valid(cache_entry)) {
363 return L1Cache_State_to_permission(cache_entry.CacheState);
366 return AccessPermission:NotPresent;
369 void setAccessPermission(Entry cache_entry, Address addr, State state) {
370 if (is_valid(cache_entry)) {
371 cache_entry.changePermission(L1Cache_State_to_permission(state));
375 Event mandatory_request_type_to_event(RubyRequestType type) {
376 if (type == RubyRequestType:LD) {
378 } else if (type == RubyRequestType:IFETCH) {
380 } else if (type == RubyRequestType:ST) {
382 } else if (type == RubyRequestType:ATOMIC) {
389 error("Invalid RubyRequestType");
393 AccessType cache_request_type_to_access_type(RubyRequestType type) {
394 if ((type == RubyRequestType:LD) || (type == RubyRequestType:IFETCH)) {
395 return AccessType:Read;
396 } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
397 return AccessType:Write;
399 error("Invalid RubyRequestType");
403 GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
404 if (machineIDToMachineType(sender) == MachineType:L1Cache) {
406 // NOTE direct local hits should not call this
408 return GenericMachineType:L1Cache_wCC;
409 } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
411 if (sender == (mapAddressToRange(addr,
414 l2_select_num_bits))) {
416 return GenericMachineType:L2Cache;
418 return GenericMachineType:L2Cache_wCC;
421 return ConvertMachToGenericMach(machineIDToMachineType(sender));
425 bool okToIssueStarving(Address addr, MachineID machinID) {
426 return persistentTable.okToIssueStarving(addr, machineID);
429 void markPersistentEntries(Address addr) {
430 persistentTable.markEntries(addr);
433 void setExternalResponse(TBE tbe) {
434 assert(is_valid(tbe));
435 tbe.ExternalResponse := true;
438 bool IsAtomic(TBE tbe) {
439 assert(is_valid(tbe));
444 out_port(persistentNetwork_out, PersistentMsg, persistentFromL1Cache);
445 out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
446 out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
447 out_port(requestRecycle_out, RequestMsg, requestToL1Cache);
452 in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
453 if (useTimerTable_in.isReady()) {
454 TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
456 if (persistentTable.isLocked(useTimerTable.readyAddress()) &&
457 (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
458 if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
459 trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress(),
460 getCacheEntry(useTimerTable.readyAddress()), tbe);
462 trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress(),
463 getCacheEntry(useTimerTable.readyAddress()), tbe);
466 if (no_mig_atomic && IsAtomic(tbe)) {
467 trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress(),
468 getCacheEntry(useTimerTable.readyAddress()), tbe);
470 trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress(),
471 getCacheEntry(useTimerTable.readyAddress()), tbe);
478 in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
479 if (reissueTimerTable_in.isReady()) {
480 trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
481 getCacheEntry(reissueTimerTable.readyAddress()),
482 L1_TBEs[reissueTimerTable.readyAddress()]);
486 // Persistent Network
487 in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
488 if (persistentNetwork_in.isReady()) {
489 peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
490 assert(in_msg.Destination.isElement(machineID));
492 // Apply the lockdown or unlockdown message to the table
493 if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
494 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
495 } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
496 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
497 } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
498 persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
500 error("Unexpected message");
503 // React to the message based on the current state of the table
504 Entry cache_entry := getCacheEntry(in_msg.Address);
505 TBE tbe := L1_TBEs[in_msg.Address];
507 if (persistentTable.isLocked(in_msg.Address)) {
508 if (persistentTable.findSmallest(in_msg.Address) == machineID) {
509 // Our Own Lock - this processor is highest priority
510 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
513 if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
514 if (getTokens(cache_entry) == 1 ||
515 getTokens(cache_entry) == (max_tokens() / 2) + 1) {
516 trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
519 trigger(Event:Persistent_GETS, in_msg.Address,
523 trigger(Event:Persistent_GETX, in_msg.Address,
528 // Unlock case - no entries in the table
529 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
537 in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
538 if (responseNetwork_in.isReady()) {
539 peek(responseNetwork_in, ResponseMsg, block_on="Address") {
540 assert(in_msg.Destination.isElement(machineID));
542 Entry cache_entry := getCacheEntry(in_msg.Address);
543 TBE tbe := L1_TBEs[in_msg.Address];
545 // Mark TBE flag if response received off-chip. Use this to update average latency estimate
546 if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
548 if (in_msg.Sender == mapAddressToRange(in_msg.Address,
551 l2_select_num_bits)) {
553 // came from an off-chip L2 cache
555 // L1_TBEs[in_msg.Address].ExternalResponse := true;
556 // profile_offchipL2_response(in_msg.Address);
560 // profile_onchipL2_response(in_msg.Address );
562 } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
564 setExternalResponse(tbe);
565 // profile_memory_response( in_msg.Address);
567 } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
568 //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
569 //if (is_valid(tbe)) {
570 // tbe.ExternalResponse := true;
571 // profile_offchipL1_response(in_msg.Address );
575 // profile_onchipL1_response(in_msg.Address );
578 error("unexpected SenderMachine");
582 if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
583 if (in_msg.Type == CoherenceResponseType:ACK) {
584 assert(in_msg.Tokens < (max_tokens() / 2));
585 trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
586 } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
587 trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
588 } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
589 assert(in_msg.Tokens < (max_tokens() / 2));
590 trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
592 error("Unexpected message");
595 if (in_msg.Type == CoherenceResponseType:ACK) {
596 assert(in_msg.Tokens < (max_tokens() / 2));
597 trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
598 } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
599 trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
601 error("Unexpected message");
609 in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
610 if (requestNetwork_in.isReady()) {
611 peek(requestNetwork_in, RequestMsg, block_on="Address") {
612 assert(in_msg.Destination.isElement(machineID));
614 Entry cache_entry := getCacheEntry(in_msg.Address);
615 TBE tbe := L1_TBEs[in_msg.Address];
617 if (in_msg.Type == CoherenceRequestType:GETX) {
618 if (in_msg.isLocal) {
619 trigger(Event:Transient_Local_GETX, in_msg.Address,
623 trigger(Event:Transient_GETX, in_msg.Address,
626 } else if (in_msg.Type == CoherenceRequestType:GETS) {
627 if (getTokens(cache_entry) == 1 ||
628 getTokens(cache_entry) == (max_tokens() / 2) + 1) {
629 if (in_msg.isLocal) {
630 trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
634 trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
639 if (in_msg.isLocal) {
640 trigger(Event:Transient_Local_GETS, in_msg.Address,
644 trigger(Event:Transient_GETS, in_msg.Address,
649 error("Unexpected message");
656 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
657 if (mandatoryQueue_in.isReady()) {
658 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
659 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
661 TBE tbe := L1_TBEs[in_msg.LineAddress];
663 if (in_msg.Type == RubyRequestType:IFETCH) {
664 // ** INSTRUCTION ACCESS ***
666 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
667 if (is_valid(L1Icache_entry)) {
668 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
669 trigger(mandatory_request_type_to_event(in_msg.Type),
670 in_msg.LineAddress, L1Icache_entry, tbe);
673 // Check to see if it is in the OTHER L1
674 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
675 if (is_valid(L1Dcache_entry)) {
676 // The block is in the wrong L1, try to write it to the L2
677 trigger(Event:L1_Replacement, in_msg.LineAddress,
678 L1Dcache_entry, tbe);
681 if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
682 // L1 does't have the line, but we have space for it in the L1
683 trigger(mandatory_request_type_to_event(in_msg.Type),
684 in_msg.LineAddress, L1Icache_entry, tbe);
686 // No room in the L1, so we need to make room
687 trigger(Event:L1_Replacement,
688 L1IcacheMemory.cacheProbe(in_msg.LineAddress),
689 getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
690 L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
694 // *** DATA ACCESS ***
696 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
697 if (is_valid(L1Dcache_entry)) {
698 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
699 trigger(mandatory_request_type_to_event(in_msg.Type),
700 in_msg.LineAddress, L1Dcache_entry, tbe);
703 // Check to see if it is in the OTHER L1
704 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
705 if (is_valid(L1Icache_entry)) {
706 // The block is in the wrong L1, try to write it to the L2
707 trigger(Event:L1_Replacement, in_msg.LineAddress,
708 L1Icache_entry, tbe);
711 if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
712 // L1 does't have the line, but we have space for it in the L1
713 trigger(mandatory_request_type_to_event(in_msg.Type),
714 in_msg.LineAddress, L1Dcache_entry, tbe);
716 // No room in the L1, so we need to make room
717 trigger(Event:L1_Replacement,
718 L1DcacheMemory.cacheProbe(in_msg.LineAddress),
719 getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
720 L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
730 action(a_issueReadRequest, "a", desc="Issue GETS") {
731 assert(is_valid(tbe));
732 if (tbe.IssueCount == 0) {
733 // Update outstanding requests
734 //profile_outstanding_request(outstandingRequests);
735 outstandingRequests := outstandingRequests + 1;
738 if (tbe.IssueCount >= retry_threshold) {
739 // Issue a persistent request if possible
740 if (okToIssueStarving(address, machineID) && (starving == false)) {
741 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
742 out_msg.Address := address;
743 out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
744 out_msg.Requestor := machineID;
745 out_msg.Destination.broadcast(MachineType:L1Cache);
748 // Currently the configuration system limits the system to only one
749 // chip. Therefore, if we assume one shared L2 cache, then only one
750 // pertinent L2 cache exist.
752 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
754 out_msg.Destination.add(mapAddressToRange(address,
757 l2_select_num_bits));
759 out_msg.Destination.add(map_Address_to_Directory(address));
760 out_msg.MessageSize := MessageSizeType:Persistent_Control;
761 out_msg.Prefetch := tbe.Prefetch;
762 out_msg.AccessMode := tbe.AccessMode;
764 markPersistentEntries(address);
767 if (tbe.IssueCount == 0) {
768 //profile_persistent_prediction(address, tbe.AccessType);
771 // Update outstanding requests
772 //profile_outstanding_persistent_request(outstandingPersistentRequests);
773 outstandingPersistentRequests := outstandingPersistentRequests + 1;
775 // Increment IssueCount
776 tbe.IssueCount := tbe.IssueCount + 1;
778 tbe.WentPersistent := true;
780 // Do not schedule a wakeup, a persistent requests will always complete
784 // We'd like to issue a persistent request, but are not allowed
785 // to issue a P.R. right now. This, we do not increment the
788 // Set a wakeup timer
789 reissueTimerTable.set(address, reissue_wakeup_latency);
793 // Make a normal request
794 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
795 out_msg.Address := address;
796 out_msg.Type := CoherenceRequestType:GETS;
797 out_msg.Requestor := machineID;
798 out_msg.Destination.add(mapAddressToRange(address,
801 l2_select_num_bits));
803 out_msg.RetryNum := tbe.IssueCount;
804 if (tbe.IssueCount == 0) {
805 out_msg.MessageSize := MessageSizeType:Request_Control;
807 out_msg.MessageSize := MessageSizeType:Reissue_Control;
809 out_msg.Prefetch := tbe.Prefetch;
810 out_msg.AccessMode := tbe.AccessMode;
813 // send to other local L1s, with local bit set
814 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
815 out_msg.Address := address;
816 out_msg.Type := CoherenceRequestType:GETS;
817 out_msg.Requestor := machineID;
819 // Since only one chip, assuming all L1 caches are local
821 //out_msg.Destination := getOtherLocalL1IDs(machineID);
822 out_msg.Destination.broadcast(MachineType:L1Cache);
823 out_msg.Destination.remove(machineID);
825 out_msg.RetryNum := tbe.IssueCount;
826 out_msg.isLocal := true;
827 if (tbe.IssueCount == 0) {
828 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
830 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
832 out_msg.Prefetch := tbe.Prefetch;
833 out_msg.AccessMode := tbe.AccessMode;
836 // Increment IssueCount
837 tbe.IssueCount := tbe.IssueCount + 1;
839 // Set a wakeup timer
841 if (dynamic_timeout_enabled) {
842 reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4);
844 reissueTimerTable.set(address, fixed_timeout_latency);
850 action(b_issueWriteRequest, "b", desc="Issue GETX") {
852 assert(is_valid(tbe));
853 if (tbe.IssueCount == 0) {
854 // Update outstanding requests
855 //profile_outstanding_request(outstandingRequests);
856 outstandingRequests := outstandingRequests + 1;
859 if (tbe.IssueCount >= retry_threshold) {
860 // Issue a persistent request if possible
861 if ( okToIssueStarving(address, machineID) && (starving == false)) {
862 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
863 out_msg.Address := address;
864 out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
865 out_msg.Requestor := machineID;
866 out_msg.Destination.broadcast(MachineType:L1Cache);
869 // Currently the configuration system limits the system to only one
870 // chip. Therefore, if we assume one shared L2 cache, then only one
871 // pertinent L2 cache exist.
873 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
875 out_msg.Destination.add(mapAddressToRange(address,
878 l2_select_num_bits));
880 out_msg.Destination.add(map_Address_to_Directory(address));
881 out_msg.MessageSize := MessageSizeType:Persistent_Control;
882 out_msg.Prefetch := tbe.Prefetch;
883 out_msg.AccessMode := tbe.AccessMode;
885 markPersistentEntries(address);
888 // Update outstanding requests
889 //profile_outstanding_persistent_request(outstandingPersistentRequests);
890 outstandingPersistentRequests := outstandingPersistentRequests + 1;
892 if (tbe.IssueCount == 0) {
893 //profile_persistent_prediction(address, tbe.AccessType);
896 // Increment IssueCount
897 tbe.IssueCount := tbe.IssueCount + 1;
899 tbe.WentPersistent := true;
901 // Do not schedule a wakeup, a persistent requests will always complete
905 // We'd like to issue a persistent request, but are not allowed
906 // to issue a P.R. right now. This, we do not increment the
909 // Set a wakeup timer
910 reissueTimerTable.set(address, reissue_wakeup_latency);
914 // Make a normal request
915 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
916 out_msg.Address := address;
917 out_msg.Type := CoherenceRequestType:GETX;
918 out_msg.Requestor := machineID;
920 out_msg.Destination.add(mapAddressToRange(address,
923 l2_select_num_bits));
925 out_msg.RetryNum := tbe.IssueCount;
927 if (tbe.IssueCount == 0) {
928 out_msg.MessageSize := MessageSizeType:Request_Control;
930 out_msg.MessageSize := MessageSizeType:Reissue_Control;
932 out_msg.Prefetch := tbe.Prefetch;
933 out_msg.AccessMode := tbe.AccessMode;
936 // send to other local L1s too
937 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
938 out_msg.Address := address;
939 out_msg.Type := CoherenceRequestType:GETX;
940 out_msg.Requestor := machineID;
941 out_msg.isLocal := true;
944 // Since only one chip, assuming all L1 caches are local
946 //out_msg.Destination := getOtherLocalL1IDs(machineID);
947 out_msg.Destination.broadcast(MachineType:L1Cache);
948 out_msg.Destination.remove(machineID);
950 out_msg.RetryNum := tbe.IssueCount;
951 if (tbe.IssueCount == 0) {
952 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
954 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
956 out_msg.Prefetch := tbe.Prefetch;
957 out_msg.AccessMode := tbe.AccessMode;
960 // Increment IssueCount
961 tbe.IssueCount := tbe.IssueCount + 1;
963 DPRINTF(RubySlicc, "incremented issue count to %d\n",
966 // Set a wakeup timer
967 if (dynamic_timeout_enabled) {
968 reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4);
970 reissueTimerTable.set(address, fixed_timeout_latency);
975 action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") {
976 peek(responseNetwork_in, ResponseMsg) {
977 // FIXME, should use a 3rd vnet
978 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
979 out_msg.Address := address;
980 out_msg.Type := in_msg.Type;
981 out_msg.Sender := machineID;
982 out_msg.Destination.add(map_Address_to_Directory(address));
983 out_msg.Tokens := in_msg.Tokens;
984 out_msg.MessageSize := in_msg.MessageSize;
985 out_msg.DataBlk := in_msg.DataBlk;
986 out_msg.Dirty := in_msg.Dirty;
991 action(c_ownedReplacement, "c", desc="Issue writeback") {
992 assert(is_valid(cache_entry));
993 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
994 out_msg.Address := address;
995 out_msg.Sender := machineID;
997 out_msg.Destination.add(mapAddressToRange(address,
1000 l2_select_num_bits));
1002 out_msg.Tokens := cache_entry.Tokens;
1003 out_msg.DataBlk := cache_entry.DataBlk;
1004 out_msg.Dirty := cache_entry.Dirty;
1005 out_msg.Type := CoherenceResponseType:WB_OWNED;
1007 // always send the data?
1008 out_msg.MessageSize := MessageSizeType:Writeback_Data;
1010 cache_entry.Tokens := 0;
1013 action(cc_sharedReplacement, "\c", desc="Issue shared writeback") {
1015 // don't send writeback if replacing block with no tokens
1016 assert(is_valid(cache_entry));
1017 assert (cache_entry.Tokens > 0);
1018 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1019 out_msg.Address := address;
1020 out_msg.Sender := machineID;
1022 out_msg.Destination.add(mapAddressToRange(address,
1023 MachineType:L2Cache,
1025 l2_select_num_bits));
1027 out_msg.Tokens := cache_entry.Tokens;
1028 out_msg.DataBlk := cache_entry.DataBlk;
1029 // assert(cache_entry.Dirty == false);
1030 out_msg.Dirty := false;
1032 out_msg.MessageSize := MessageSizeType:Writeback_Data;
1033 out_msg.Type := CoherenceResponseType:WB_SHARED_DATA;
1035 cache_entry.Tokens := 0;
1038 action(tr_tokenReplacement, "tr", desc="Issue token writeback") {
1039 assert(is_valid(cache_entry));
1040 if (cache_entry.Tokens > 0) {
1041 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1042 out_msg.Address := address;
1043 out_msg.Sender := machineID;
1045 out_msg.Destination.add(mapAddressToRange(address,
1046 MachineType:L2Cache,
1048 l2_select_num_bits));
1050 out_msg.Tokens := cache_entry.Tokens;
1051 out_msg.DataBlk := cache_entry.DataBlk;
1052 // assert(cache_entry.Dirty == false);
1053 out_msg.Dirty := false;
1055 // always send the data?
1056 out_msg.MessageSize := MessageSizeType:Writeback_Control;
1057 out_msg.Type := CoherenceResponseType:WB_TOKENS;
1060 cache_entry.Tokens := 0;
1064 action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") {
1065 assert(is_valid(cache_entry));
1066 peek(requestNetwork_in, RequestMsg) {
1067 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1068 out_msg.Address := address;
1069 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1070 out_msg.Sender := machineID;
1071 out_msg.Destination.add(in_msg.Requestor);
1072 out_msg.Tokens := 1;
1073 out_msg.DataBlk := cache_entry.DataBlk;
1074 // out_msg.Dirty := cache_entry.Dirty;
1075 out_msg.Dirty := false;
1076 if (in_msg.isLocal) {
1077 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1079 out_msg.MessageSize := MessageSizeType:Response_Data;
1083 cache_entry.Tokens := cache_entry.Tokens - 1;
1084 assert(cache_entry.Tokens >= 1);
1087 action(d_sendDataWithNTokenIfAvail, "\dd", desc="Send data and a token from cache to requestor") {
1088 assert(is_valid(cache_entry));
1089 peek(requestNetwork_in, RequestMsg) {
1090 if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1091 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1092 out_msg.Address := address;
1093 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1094 out_msg.Sender := machineID;
1095 out_msg.Destination.add(in_msg.Requestor);
1096 out_msg.Tokens := N_tokens;
1097 out_msg.DataBlk := cache_entry.DataBlk;
1098 // out_msg.Dirty := cache_entry.Dirty;
1099 out_msg.Dirty := false;
1100 if (in_msg.isLocal) {
1101 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1103 out_msg.MessageSize := MessageSizeType:Response_Data;
1106 cache_entry.Tokens := cache_entry.Tokens - N_tokens;
1108 else if (cache_entry.Tokens > 1) {
1109 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1110 out_msg.Address := address;
1111 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1112 out_msg.Sender := machineID;
1113 out_msg.Destination.add(in_msg.Requestor);
1114 out_msg.Tokens := 1;
1115 out_msg.DataBlk := cache_entry.DataBlk;
1116 // out_msg.Dirty := cache_entry.Dirty;
1117 out_msg.Dirty := false;
1118 if (in_msg.isLocal) {
1119 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1121 out_msg.MessageSize := MessageSizeType:Response_Data;
1124 cache_entry.Tokens := cache_entry.Tokens - 1;
1127 // assert(cache_entry.Tokens >= 1);
1130 action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") {
1131 peek(requestNetwork_in, RequestMsg) {
1132 assert(is_valid(cache_entry));
1133 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1134 out_msg.Address := address;
1135 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1136 out_msg.Sender := machineID;
1137 out_msg.Destination.add(in_msg.Requestor);
1138 assert(cache_entry.Tokens > (max_tokens() / 2));
1139 out_msg.Tokens := cache_entry.Tokens;
1140 out_msg.DataBlk := cache_entry.DataBlk;
1141 out_msg.Dirty := cache_entry.Dirty;
1142 if (in_msg.isLocal) {
1143 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1145 out_msg.MessageSize := MessageSizeType:Response_Data;
1149 cache_entry.Tokens := 0;
1152 action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") {
1153 // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1154 assert(is_valid(cache_entry));
1155 if (cache_entry.Tokens > 0) {
1156 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1157 out_msg.Address := address;
1158 if (cache_entry.Tokens > (max_tokens() / 2)) {
1159 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1161 out_msg.Type := CoherenceResponseType:ACK;
1163 out_msg.Sender := machineID;
1164 out_msg.Destination.add(persistentTable.findSmallest(address));
1165 assert(cache_entry.Tokens >= 1);
1166 out_msg.Tokens := cache_entry.Tokens;
1167 out_msg.DataBlk := cache_entry.DataBlk;
1168 out_msg.MessageSize := MessageSizeType:Response_Control;
1171 cache_entry.Tokens := 0;
1174 action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
1175 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1176 assert(is_valid(cache_entry));
1177 assert(cache_entry.Tokens > 0);
1178 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1179 out_msg.Address := address;
1180 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1181 out_msg.Sender := machineID;
1182 out_msg.Destination.add(persistentTable.findSmallest(address));
1183 assert(cache_entry.Tokens > (max_tokens() / 2));
1184 out_msg.Tokens := cache_entry.Tokens;
1185 out_msg.DataBlk := cache_entry.DataBlk;
1186 out_msg.Dirty := cache_entry.Dirty;
1187 out_msg.MessageSize := MessageSizeType:Response_Data;
1189 cache_entry.Tokens := 0;
1192 action(f_sendAckWithAllButNorOneTokens, "f", desc="Send ack with all our tokens but one to starver.") {
1193 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1194 assert(is_valid(cache_entry));
1195 assert(cache_entry.Tokens > 0);
1196 if (cache_entry.Tokens > 1) {
1197 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1198 out_msg.Address := address;
1199 if (cache_entry.Tokens > (max_tokens() / 2)) {
1200 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1202 out_msg.Type := CoherenceResponseType:ACK;
1204 out_msg.Sender := machineID;
1205 out_msg.Destination.add(persistentTable.findSmallest(address));
1206 assert(cache_entry.Tokens >= 1);
1207 if (cache_entry.Tokens > N_tokens) {
1208 out_msg.Tokens := cache_entry.Tokens - N_tokens;
1210 out_msg.Tokens := cache_entry.Tokens - 1;
1212 out_msg.DataBlk := cache_entry.DataBlk;
1213 out_msg.MessageSize := MessageSizeType:Response_Control;
1216 if (cache_entry.Tokens > N_tokens) {
1217 cache_entry.Tokens := N_tokens;
1219 cache_entry.Tokens := 1;
1223 action(ff_sendDataWithAllButNorOneTokens, "\f", desc="Send data and out tokens but one to starver") {
1224 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1225 assert(is_valid(cache_entry));
1226 assert(cache_entry.Tokens > ((max_tokens() / 2) + 1));
1227 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1228 out_msg.Address := address;
1229 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1230 out_msg.Sender := machineID;
1231 out_msg.Destination.add(persistentTable.findSmallest(address));
1232 if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1233 out_msg.Tokens := cache_entry.Tokens - N_tokens;
1235 out_msg.Tokens := cache_entry.Tokens - 1;
1237 assert(out_msg.Tokens > (max_tokens() / 2));
1238 out_msg.DataBlk := cache_entry.DataBlk;
1239 out_msg.Dirty := cache_entry.Dirty;
1240 out_msg.MessageSize := MessageSizeType:Response_Data;
1242 if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1243 cache_entry.Tokens := N_tokens;
1245 cache_entry.Tokens := 1;
1249 action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") {
1250 assert(is_valid(cache_entry));
1251 assert(cache_entry.Tokens == ((max_tokens() / 2) + 1));
1252 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1253 out_msg.Address := address;
1254 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1255 out_msg.Sender := machineID;
1256 out_msg.Destination.add(persistentTable.findSmallest(address));
1257 out_msg.Tokens := cache_entry.Tokens;
1258 assert(out_msg.Tokens > (max_tokens() / 2));
1259 out_msg.DataBlk := cache_entry.DataBlk;
1260 out_msg.Dirty := cache_entry.Dirty;
1261 out_msg.MessageSize := MessageSizeType:Response_Data;
1263 cache_entry.Tokens := 0;
1266 action(g_bounceResponseToStarver, "g", desc="Redirect response to starving processor") {
1267 // assert(persistentTable.isLocked(address));
1269 peek(responseNetwork_in, ResponseMsg) {
1270 // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1271 // FIXME, should use a 3rd vnet in some cases
1272 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
1273 out_msg.Address := address;
1274 out_msg.Type := in_msg.Type;
1275 out_msg.Sender := machineID;
1276 out_msg.Destination.add(persistentTable.findSmallest(address));
1277 out_msg.Tokens := in_msg.Tokens;
1278 out_msg.DataBlk := in_msg.DataBlk;
1279 out_msg.Dirty := in_msg.Dirty;
1280 out_msg.MessageSize := in_msg.MessageSize;
1286 action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
1287 assert(is_valid(cache_entry));
1288 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1289 address, cache_entry.DataBlk);
1291 sequencer.readCallback(address,
1292 GenericMachineType:L1Cache,
1293 cache_entry.DataBlk);
1297 action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
1298 assert(is_valid(cache_entry));
1299 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1300 address, cache_entry.DataBlk);
1301 peek(responseNetwork_in, ResponseMsg) {
1303 sequencer.readCallback(address,
1304 getNondirectHitMachType(address, in_msg.Sender),
1305 cache_entry.DataBlk);
1310 action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
1311 assert(is_valid(cache_entry));
1312 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1313 address, cache_entry.DataBlk);
1315 sequencer.writeCallback(address,
1316 GenericMachineType:L1Cache,
1317 cache_entry.DataBlk);
1319 cache_entry.Dirty := true;
1320 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1323 action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
1324 assert(is_valid(cache_entry));
1325 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1326 address, cache_entry.DataBlk);
1327 peek(responseNetwork_in, ResponseMsg) {
1329 sequencer.writeCallback(address,
1330 getNondirectHitMachType(address, in_msg.Sender),
1331 cache_entry.DataBlk);
1334 cache_entry.Dirty := true;
1335 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1338 action(i_allocateTBE, "i", desc="Allocate TBE") {
1339 check_allocate(L1_TBEs);
1340 L1_TBEs.allocate(address);
1341 set_tbe(L1_TBEs[address]);
1342 tbe.IssueCount := 0;
1343 peek(mandatoryQueue_in, RubyRequest) {
1344 tbe.PC := in_msg.ProgramCounter;
1345 tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
1346 if (in_msg.Type == RubyRequestType:ATOMIC) {
1347 tbe.IsAtomic := true;
1349 tbe.Prefetch := in_msg.Prefetch;
1350 tbe.AccessMode := in_msg.AccessMode;
1352 tbe.IssueTime := curCycle();
1355 action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
1356 peek(mandatoryQueue_in, RubyRequest) {
1357 APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1361 action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
1362 if (reissueTimerTable.isSet(address)) {
1363 reissueTimerTable.unset(address);
1367 action(jj_unsetUseTimer, "\j", desc="Unset use timer.") {
1368 useTimerTable.unset(address);
1371 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
1372 mandatoryQueue_in.dequeue();
1375 action(l_popPersistentQueue, "l", desc="Pop persistent queue.") {
1376 persistentNetwork_in.dequeue();
1379 action(m_popRequestQueue, "m", desc="Pop request queue.") {
1380 requestNetwork_in.dequeue();
1383 action(n_popResponseQueue, "n", desc="Pop response queue") {
1384 responseNetwork_in.dequeue();
1387 action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
1388 useTimerTable.set(address, use_timeout_latency);
1391 action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
1392 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1393 out_msg.Address := address;
1394 out_msg.Type := CoherenceResponseType:INV;
1395 out_msg.Tokens := 0;
1396 out_msg.Sender := machineID;
1398 out_msg.Destination.add(mapAddressToRange(address,
1399 MachineType:L2Cache,
1401 l2_select_num_bits));
1403 out_msg.MessageSize := MessageSizeType:Response_Control;
1407 action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
1408 peek(responseNetwork_in, ResponseMsg) {
1409 assert(is_valid(cache_entry));
1410 assert(in_msg.Tokens != 0);
1411 DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
1412 in_msg.Address, in_msg.Tokens);
1413 cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
1414 DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
1416 if (cache_entry.Dirty == false && in_msg.Dirty) {
1417 cache_entry.Dirty := true;
1422 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1424 assert(is_valid(tbe));
1425 if (tbe.WentPersistent) {
1426 // assert(starving == true);
1427 outstandingRequests := outstandingRequests - 1;
1428 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
1429 out_msg.Address := address;
1430 out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
1431 out_msg.Requestor := machineID;
1432 out_msg.Destination.broadcast(MachineType:L1Cache);
1435 // Currently the configuration system limits the system to only one
1436 // chip. Therefore, if we assume one shared L2 cache, then only one
1437 // pertinent L2 cache exist.
1439 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
1441 out_msg.Destination.add(mapAddressToRange(address,
1442 MachineType:L2Cache,
1444 l2_select_num_bits));
1446 out_msg.Destination.add(map_Address_to_Directory(address));
1447 out_msg.MessageSize := MessageSizeType:Persistent_Control;
1452 // Update average latency
1453 if (tbe.IssueCount <= 1) {
1454 if (tbe.ExternalResponse == true) {
1455 updateAverageLatencyEstimate(TimeToCycles(curCycle() - tbe.IssueTime));
1460 //if (tbe.WentPersistent) {
1461 // profile_token_retry(address, tbe.AccessType, 2);
1464 // profile_token_retry(address, tbe.AccessType, 1);
1467 //profile_token_retry(address, tbe.AccessType, tbe.IssueCount);
1468 L1_TBEs.deallocate(address);
1472 action(t_sendAckWithCollectedTokens, "t", desc="Send ack with the tokens we've collected thus far.") {
1473 assert(is_valid(cache_entry));
1474 if (cache_entry.Tokens > 0) {
1475 peek(requestNetwork_in, RequestMsg) {
1476 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1477 out_msg.Address := address;
1478 if (cache_entry.Tokens > (max_tokens() / 2)) {
1479 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1481 out_msg.Type := CoherenceResponseType:ACK;
1483 out_msg.Sender := machineID;
1484 out_msg.Destination.add(in_msg.Requestor);
1485 assert(cache_entry.Tokens >= 1);
1486 out_msg.Tokens := cache_entry.Tokens;
1487 out_msg.DataBlk := cache_entry.DataBlk;
1488 out_msg.MessageSize := MessageSizeType:Response_Control;
1492 cache_entry.Tokens := 0;
1495 action(u_writeDataToCache, "u", desc="Write data to cache") {
1496 peek(responseNetwork_in, ResponseMsg) {
1497 assert(is_valid(cache_entry));
1498 cache_entry.DataBlk := in_msg.DataBlk;
1499 if (cache_entry.Dirty == false && in_msg.Dirty) {
1500 cache_entry.Dirty := in_msg.Dirty;
1506 action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1507 assert(getTokens(cache_entry) == 0);
1508 if (L1DcacheMemory.isTagPresent(address)) {
1509 L1DcacheMemory.deallocate(address);
1511 L1IcacheMemory.deallocate(address);
1513 unset_cache_entry();
1516 action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1517 if (is_valid(cache_entry)) {
1519 set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
1523 action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
1524 if (is_valid(cache_entry)) {
1526 set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
1530 action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
1531 if (send_evictions) {
1532 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1533 sequencer.evictionCallback(address);
1537 action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1538 peek(mandatoryQueue_in, RubyRequest) {
1539 if (L1DcacheMemory.isTagPresent(address)) {
1540 L1DcacheMemory.profileMiss(in_msg);
1542 L1IcacheMemory.profileMiss(in_msg);
1547 action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
1548 peek(responseNetwork_in, ResponseMsg) {
1549 assert(is_valid(cache_entry));
1550 assert(cache_entry.DataBlk == in_msg.DataBlk);
1554 action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1555 peek(mandatoryQueue_in, RubyRequest) {
1556 APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1558 stall_and_wait(mandatoryQueue_in, address);
1561 action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1562 wakeUpBuffers(address);
1565 action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1569 //*****************************************************
1571 //*****************************************************
1573 // Transitions for Load/Store/L2_Replacement from transient states
1574 transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
1575 ta_traceStalledAddress;
1576 zz_stallAndWaitMandatoryQueue;
1579 transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
1580 zz_stallAndWaitMandatoryQueue;
1583 transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
1584 zz_stallAndWaitMandatoryQueue;
1588 transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
1589 l_popPersistentQueue;
1592 // Transitions from NP
1593 transition(NP, Load, IS) {
1594 ii_allocateL1DCacheBlock;
1598 k_popMandatoryQueue;
1601 transition(NP, Ifetch, IS) {
1602 pp_allocateL1ICacheBlock;
1606 k_popMandatoryQueue;
1609 transition(NP, {Store, Atomic}, IM) {
1610 ii_allocateL1DCacheBlock;
1612 b_issueWriteRequest;
1614 k_popMandatoryQueue;
1617 transition(NP, {Ack, Data_Shared, Data_Owner, Data_All_Tokens}) {
1622 transition(NP, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) {
1626 transition(NP, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1627 l_popPersistentQueue;
1630 // Transitions from Idle
1631 transition(I, Load, IS) {
1635 k_popMandatoryQueue;
1638 transition(I, Ifetch, IS) {
1642 k_popMandatoryQueue;
1645 transition(I, {Store, Atomic}, IM) {
1647 b_issueWriteRequest;
1649 k_popMandatoryQueue;
1652 transition(I, L1_Replacement) {
1653 ta_traceStalledAddress;
1654 tr_tokenReplacement;
1655 gg_deallocateL1CacheBlock;
1656 ka_wakeUpAllDependents;
1659 transition(I, {Transient_GETX, Transient_Local_GETX}) {
1660 t_sendAckWithCollectedTokens;
1664 transition(I, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1668 transition(I, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1669 e_sendAckWithCollectedTokens;
1670 l_popPersistentQueue;
1673 transition(I_L, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}) {
1674 l_popPersistentQueue;
1677 transition(I, Ack) {
1678 q_updateTokensFromResponse;
1682 transition(I, Data_Shared, S) {
1684 q_updateTokensFromResponse;
1688 transition(I, Data_Owner, O) {
1690 q_updateTokensFromResponse;
1694 transition(I, Data_All_Tokens, M) {
1696 q_updateTokensFromResponse;
1700 // Transitions from Shared
1701 transition({S, SM, S_L, SM_L}, {Load, Ifetch}) {
1703 k_popMandatoryQueue;
1706 transition(S, {Store, Atomic}, SM) {
1708 b_issueWriteRequest;
1710 k_popMandatoryQueue;
1713 transition(S, L1_Replacement, I) {
1714 ta_traceStalledAddress;
1715 cc_sharedReplacement; // Only needed in some cases
1716 forward_eviction_to_cpu;
1717 gg_deallocateL1CacheBlock;
1718 ka_wakeUpAllDependents;
1721 transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
1722 t_sendAckWithCollectedTokens;
1723 p_informL2AboutTokenLoss;
1724 forward_eviction_to_cpu
1728 // only owner responds to non-local requests
1729 transition(S, Transient_GETS) {
1733 transition(S, Transient_Local_GETS) {
1734 d_sendDataWithToken;
1738 transition(S, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1742 transition({S, S_L}, Persistent_GETX, I_L) {
1743 e_sendAckWithCollectedTokens;
1744 p_informL2AboutTokenLoss;
1745 forward_eviction_to_cpu
1746 l_popPersistentQueue;
1749 transition(S, {Persistent_GETS, Persistent_GETS_Last_Token}, S_L) {
1750 f_sendAckWithAllButNorOneTokens;
1751 l_popPersistentQueue;
1754 transition(S_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1755 l_popPersistentQueue;
1758 transition(S, Ack) {
1759 q_updateTokensFromResponse;
1763 transition(S, Data_Shared) {
1764 w_assertIncomingDataAndCacheDataMatch;
1765 q_updateTokensFromResponse;
1769 transition(S, Data_Owner, O) {
1770 w_assertIncomingDataAndCacheDataMatch;
1771 q_updateTokensFromResponse;
1775 transition(S, Data_All_Tokens, M) {
1776 w_assertIncomingDataAndCacheDataMatch;
1777 q_updateTokensFromResponse;
1781 // Transitions from Owned
1782 transition({O, OM}, {Load, Ifetch}) {
1784 k_popMandatoryQueue;
1787 transition(O, {Store, Atomic}, OM) {
1789 b_issueWriteRequest;
1791 k_popMandatoryQueue;
1794 transition(O, L1_Replacement, I) {
1795 ta_traceStalledAddress;
1797 forward_eviction_to_cpu
1798 gg_deallocateL1CacheBlock;
1799 ka_wakeUpAllDependents;
1802 transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
1803 dd_sendDataWithAllTokens;
1804 p_informL2AboutTokenLoss;
1805 forward_eviction_to_cpu
1809 transition(O, Persistent_GETX, I_L) {
1810 ee_sendDataWithAllTokens;
1811 p_informL2AboutTokenLoss;
1812 forward_eviction_to_cpu
1813 l_popPersistentQueue;
1816 transition(O, Persistent_GETS, S_L) {
1817 ff_sendDataWithAllButNorOneTokens;
1818 l_popPersistentQueue;
1821 transition(O, Persistent_GETS_Last_Token, I_L) {
1822 fo_sendDataWithOwnerToken;
1823 forward_eviction_to_cpu
1824 l_popPersistentQueue;
1827 transition(O, Transient_GETS) {
1828 d_sendDataWithToken;
1832 transition(O, Transient_Local_GETS) {
1833 d_sendDataWithToken;
1837 // ran out of tokens, wait for it to go persistent
1838 transition(O, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1842 transition(O, Ack) {
1843 q_updateTokensFromResponse;
1847 transition(O, Ack_All_Tokens, M) {
1848 q_updateTokensFromResponse;
1852 transition(O, Data_Shared) {
1853 w_assertIncomingDataAndCacheDataMatch;
1854 q_updateTokensFromResponse;
1858 transition(O, Data_All_Tokens, M) {
1859 w_assertIncomingDataAndCacheDataMatch;
1860 q_updateTokensFromResponse;
1864 // Transitions from Modified
1865 transition({MM, MM_W}, {Load, Ifetch}) {
1867 k_popMandatoryQueue;
1870 transition({MM_W}, {Store, Atomic}) {
1872 k_popMandatoryQueue;
1875 transition(MM, Store) {
1877 k_popMandatoryQueue;
1880 transition(MM, Atomic, M) {
1882 k_popMandatoryQueue;
1885 transition(MM, L1_Replacement, I) {
1886 ta_traceStalledAddress;
1888 forward_eviction_to_cpu
1889 gg_deallocateL1CacheBlock;
1890 ka_wakeUpAllDependents;
1893 transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
1894 dd_sendDataWithAllTokens;
1895 p_informL2AboutTokenLoss;
1896 forward_eviction_to_cpu
1900 transition({MM_W}, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1904 // Implement the migratory sharing optimization, even for persistent requests
1905 transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
1906 ee_sendDataWithAllTokens;
1907 p_informL2AboutTokenLoss;
1908 forward_eviction_to_cpu
1909 l_popPersistentQueue;
1912 // ignore persistent requests in lockout period
1913 transition(MM_W, {Persistent_GETX, Persistent_GETS}) {
1914 l_popPersistentQueue;
1917 transition(MM_W, Use_TimeoutNoStarvers, MM) {
1920 kd_wakeUpDependents;
1923 transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
1926 kd_wakeUpDependents;
1929 // Transitions from Dirty Exclusive
1930 transition({M, M_W}, {Load, Ifetch}) {
1932 k_popMandatoryQueue;
1935 transition(M, Store, MM) {
1937 k_popMandatoryQueue;
1940 transition(M, Atomic) {
1942 k_popMandatoryQueue;
1945 transition(M_W, Store, MM_W) {
1947 k_popMandatoryQueue;
1950 transition(M_W, Atomic) {
1952 k_popMandatoryQueue;
1955 transition(M, L1_Replacement, I) {
1956 ta_traceStalledAddress;
1958 forward_eviction_to_cpu
1959 gg_deallocateL1CacheBlock;
1960 ka_wakeUpAllDependents;
1963 transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
1964 dd_sendDataWithAllTokens;
1965 p_informL2AboutTokenLoss;
1966 forward_eviction_to_cpu
1970 transition(M, Transient_Local_GETS, O) {
1971 d_sendDataWithToken;
1975 transition(M, Transient_GETS, O) {
1976 d_sendDataWithNTokenIfAvail;
1980 transition(M_W, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1984 transition(M, Persistent_GETX, I_L) {
1985 ee_sendDataWithAllTokens;
1986 p_informL2AboutTokenLoss;
1987 forward_eviction_to_cpu
1988 l_popPersistentQueue;
1991 transition(M, Persistent_GETS, S_L) {
1992 ff_sendDataWithAllButNorOneTokens;
1993 l_popPersistentQueue;
1996 // ignore persistent requests in lockout period
1997 transition(M_W, {Persistent_GETX, Persistent_GETS}) {
1998 l_popPersistentQueue;
2001 transition(M_W, Use_TimeoutStarverS, S_L) {
2003 ff_sendDataWithAllButNorOneTokens;
2007 // someone unlocked during timeout
2008 transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
2011 kd_wakeUpDependents;
2014 transition(M_W, Use_TimeoutStarverX, I_L) {
2016 ee_sendDataWithAllTokens;
2017 forward_eviction_to_cpu;
2018 p_informL2AboutTokenLoss;
2023 transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
2025 ee_sendDataWithAllTokens;
2026 forward_eviction_to_cpu;
2027 p_informL2AboutTokenLoss;
2032 // Transient_GETX and Transient_GETS in transient states
2033 transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2034 m_popRequestQueue; // Even if we have the data, we can pretend we don't have it yet.
2037 transition(IS, {Transient_GETX, Transient_Local_GETX}) {
2038 t_sendAckWithCollectedTokens;
2042 transition(IS, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2046 transition(IS, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IS_L) {
2047 e_sendAckWithCollectedTokens;
2048 l_popPersistentQueue;
2051 transition(IS_L, {Persistent_GETX, Persistent_GETS}) {
2052 l_popPersistentQueue;
2055 transition(IM, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IM_L) {
2056 e_sendAckWithCollectedTokens;
2057 l_popPersistentQueue;
2060 transition(IM_L, {Persistent_GETX, Persistent_GETS}) {
2061 l_popPersistentQueue;
2064 transition({SM, SM_L}, Persistent_GETX, IM_L) {
2065 e_sendAckWithCollectedTokens;
2066 forward_eviction_to_cpu
2067 l_popPersistentQueue;
2070 transition(SM, {Persistent_GETS, Persistent_GETS_Last_Token}, SM_L) {
2071 f_sendAckWithAllButNorOneTokens;
2072 l_popPersistentQueue;
2075 transition(SM_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
2076 l_popPersistentQueue;
2079 transition(OM, Persistent_GETX, IM_L) {
2080 ee_sendDataWithAllTokens;
2081 forward_eviction_to_cpu
2082 l_popPersistentQueue;
2085 transition(OM, Persistent_GETS, SM_L) {
2086 ff_sendDataWithAllButNorOneTokens;
2087 l_popPersistentQueue;
2090 transition(OM, Persistent_GETS_Last_Token, IM_L) {
2091 fo_sendDataWithOwnerToken;
2092 l_popPersistentQueue;
2095 // Transitions from IM/SM
2097 transition({IM, SM}, Ack) {
2098 q_updateTokensFromResponse;
2102 transition(IM, Data_Shared, SM) {
2104 q_updateTokensFromResponse;
2108 transition(IM, Data_Owner, OM) {
2110 q_updateTokensFromResponse;
2114 transition(IM, Data_All_Tokens, MM_W) {
2116 q_updateTokensFromResponse;
2117 xx_external_store_hit;
2118 o_scheduleUseTimeout;
2119 j_unsetReissueTimer;
2121 kd_wakeUpDependents;
2124 transition(SM, Data_Shared) {
2125 w_assertIncomingDataAndCacheDataMatch;
2126 q_updateTokensFromResponse;
2130 transition(SM, Data_Owner, OM) {
2131 w_assertIncomingDataAndCacheDataMatch;
2132 q_updateTokensFromResponse;
2136 transition(SM, Data_All_Tokens, MM_W) {
2137 w_assertIncomingDataAndCacheDataMatch;
2138 q_updateTokensFromResponse;
2139 xx_external_store_hit;
2140 o_scheduleUseTimeout;
2141 j_unsetReissueTimer;
2143 kd_wakeUpDependents;
2146 transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens. We give them up here to avoid livelock
2147 t_sendAckWithCollectedTokens;
2148 forward_eviction_to_cpu;
2152 transition({IM, SM}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2156 transition({IM, SM}, Request_Timeout) {
2157 j_unsetReissueTimer;
2158 b_issueWriteRequest;
2161 // Transitions from OM
2163 transition(OM, Ack) {
2164 q_updateTokensFromResponse;
2168 transition(OM, Ack_All_Tokens, MM_W) {
2169 q_updateTokensFromResponse;
2170 xx_external_store_hit;
2171 o_scheduleUseTimeout;
2172 j_unsetReissueTimer;
2174 kd_wakeUpDependents;
2177 transition(OM, Data_Shared) {
2178 w_assertIncomingDataAndCacheDataMatch;
2179 q_updateTokensFromResponse;
2183 transition(OM, Data_All_Tokens, MM_W) {
2184 w_assertIncomingDataAndCacheDataMatch;
2185 q_updateTokensFromResponse;
2186 xx_external_store_hit;
2187 o_scheduleUseTimeout;
2188 j_unsetReissueTimer;
2190 kd_wakeUpDependents;
2193 transition(OM, Request_Timeout) {
2194 j_unsetReissueTimer;
2195 b_issueWriteRequest;
2198 // Transitions from IS
2200 transition(IS, Ack) {
2201 q_updateTokensFromResponse;
2205 transition(IS, Data_Shared, S) {
2207 q_updateTokensFromResponse;
2208 x_external_load_hit;
2210 j_unsetReissueTimer;
2212 kd_wakeUpDependents;
2215 transition(IS, Data_Owner, O) {
2217 q_updateTokensFromResponse;
2218 x_external_load_hit;
2220 j_unsetReissueTimer;
2222 kd_wakeUpDependents;
2225 transition(IS, Data_All_Tokens, M_W) {
2227 q_updateTokensFromResponse;
2228 x_external_load_hit;
2229 o_scheduleUseTimeout;
2230 j_unsetReissueTimer;
2232 kd_wakeUpDependents;
2235 transition(IS, Request_Timeout) {
2236 j_unsetReissueTimer;
2240 // Transitions from I_L
2242 transition(I_L, Load, IS_L) {
2243 ii_allocateL1DCacheBlock;
2247 k_popMandatoryQueue;
2250 transition(I_L, Ifetch, IS_L) {
2251 pp_allocateL1ICacheBlock;
2255 k_popMandatoryQueue;
2258 transition(I_L, {Store, Atomic}, IM_L) {
2259 ii_allocateL1DCacheBlock;
2261 b_issueWriteRequest;
2263 k_popMandatoryQueue;
2267 // Transitions from S_L
2269 transition(S_L, {Store, Atomic}, SM_L) {
2271 b_issueWriteRequest;
2273 k_popMandatoryQueue;
2276 // Other transitions from *_L states
2278 transition({I_L, IM_L, IS_L, S_L, SM_L}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS, Transient_GETX, Transient_Local_GETX}) {
2282 transition({I_L, IM_L, IS_L, S_L, SM_L}, Ack) {
2283 g_bounceResponseToStarver;
2287 transition({I_L, IM_L, S_L, SM_L}, {Data_Shared, Data_Owner}) {
2288 g_bounceResponseToStarver;
2292 transition({I_L, S_L}, Data_All_Tokens) {
2293 g_bounceResponseToStarver;
2297 transition(IS_L, Request_Timeout) {
2298 j_unsetReissueTimer;
2302 transition({IM_L, SM_L}, Request_Timeout) {
2303 j_unsetReissueTimer;
2304 b_issueWriteRequest;
2307 // Opportunisticly Complete the memory operation in the following
2308 // cases. Note: these transitions could just use
2309 // g_bounceResponseToStarver, but if we have the data and tokens, we
2310 // might as well complete the memory request while we have the
2311 // chance (and then immediately forward on the data)
2313 transition(IM_L, Data_All_Tokens, MM_W) {
2315 q_updateTokensFromResponse;
2316 xx_external_store_hit;
2317 j_unsetReissueTimer;
2318 o_scheduleUseTimeout;
2320 kd_wakeUpDependents;
2323 transition(SM_L, Data_All_Tokens, S_L) {
2325 q_updateTokensFromResponse;
2326 xx_external_store_hit;
2327 ff_sendDataWithAllButNorOneTokens;
2329 j_unsetReissueTimer;
2333 transition(IS_L, Data_Shared, I_L) {
2335 q_updateTokensFromResponse;
2336 x_external_load_hit;
2338 e_sendAckWithCollectedTokens;
2339 p_informL2AboutTokenLoss;
2340 j_unsetReissueTimer;
2344 transition(IS_L, Data_Owner, I_L) {
2346 q_updateTokensFromResponse;
2347 x_external_load_hit;
2348 ee_sendDataWithAllTokens;
2350 p_informL2AboutTokenLoss;
2351 j_unsetReissueTimer;
2355 transition(IS_L, Data_All_Tokens, M_W) {
2357 q_updateTokensFromResponse;
2358 x_external_load_hit;
2359 j_unsetReissueTimer;
2360 o_scheduleUseTimeout;
2362 kd_wakeUpDependents;
2365 // Own_Lock_or_Unlock
2367 transition(I_L, Own_Lock_or_Unlock, I) {
2368 l_popPersistentQueue;
2369 kd_wakeUpDependents;
2372 transition(S_L, Own_Lock_or_Unlock, S) {
2373 l_popPersistentQueue;
2374 kd_wakeUpDependents;
2377 transition(IM_L, Own_Lock_or_Unlock, IM) {
2378 l_popPersistentQueue;
2379 kd_wakeUpDependents;
2382 transition(IS_L, Own_Lock_or_Unlock, IS) {
2383 l_popPersistentQueue;
2384 kd_wakeUpDependents;
2387 transition(SM_L, Own_Lock_or_Unlock, SM) {
2388 l_popPersistentQueue;
2389 kd_wakeUpDependents;