src/mem/protocol/MOESI_CMP_token-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id: MOESI_CMP_token-L1cache.sm 1.22 05/01/19 15:55:39-06:00 beckmann@s0-28.cs.wisc.edu $
  32  *
  33  */
  34
  35 machine(L1Cache, "Token protocol")
  36  : Sequencer * sequencer,
  37    CacheMemory * L1IcacheMemory,
  38    CacheMemory * L1DcacheMemory,
  39    int l2_select_num_bits,
  40    int N_tokens,
  41    int l1_request_latency = 2,
  42    int l1_response_latency = 2,
  43    int retry_threshold = 1,
  44    int fixed_timeout_latency = 100,
  45    bool dynamic_timeout_enabled = true,
  46    bool no_mig_atomic = true
  47 {
  48
  49   // From this node's L1 cache TO the network
  50
  51   // a local L1 -> this L2 bank
  52   MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false";
  53   MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true";
  54   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  55   MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false";
  56
  57
  58   // To this node's L1 cache FROM the network
  59   // a L2 bank -> this L1
  60   MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false";
  61   MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true";
  62   // a L2 bank -> this L1
  63   MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
  64
  65   // STATES
  66   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  67     // Base states
  68     NP,   "NP",   desc="Not Present";
  69     I,    "I",    desc="Idle";
  70     S,    "S",    desc="Shared";
  71     O,    "O",    desc="Owned";
  72     M,    "M",    desc="Modified (dirty)";
  73     MM,   "MM",   desc="Modified (dirty and locally modified)";
  74     M_W,  "M^W",  desc="Modified (dirty), waiting";
  75     MM_W, "MM^W", desc="Modified (dirty and locally modified), waiting";
  76
  77     // Transient States
  78     IM, "IM", desc="Issued GetX";
  79     SM, "SM", desc="Issued GetX, we still have an old copy of the line";
  80     OM, "OM", desc="Issued GetX, received data";
  81     IS, "IS", desc="Issued GetS";
  82
  83     // Locked states
  84     I_L,  "I^L",   desc="Invalid, Locked";
  85     S_L,  "S^L",   desc="Shared, Locked";
  86     IM_L, "IM^L",  desc="Invalid, Locked, trying to go to Modified";
  87     SM_L, "SM^L",  desc="Shared, Locked, trying to go to Modified";
  88     IS_L, "IS^L",  desc="Invalid, Locked, trying to go to Shared";
  89   }
  90
  91   // EVENTS
  92   enumeration(Event, desc="Cache events") {
  93     Load,            desc="Load request from the processor";
  94     Ifetch,          desc="I-fetch request from the processor";
  95     Store,           desc="Store request from the processor";
  96     Atomic,          desc="Atomic request from the processor";
  97     L1_Replacement,  desc="L1 Replacement";
  98
  99     // Responses
 100     Data_Shared,             desc="Received a data message, we are now a sharer";
 101     Data_Owner,              desc="Received a data message, we are now the owner";
 102     Data_All_Tokens,   desc="Received a data message, we are now the owner, we now have all the tokens";
 103     Ack,                     desc="Received an ack message";
 104     Ack_All_Tokens,          desc="Received an ack message, we now have all the tokens";
 105
 106     // Requests
 107     Transient_GETX,  desc="A GetX from another processor";
 108     Transient_Local_GETX,  desc="A GetX from another processor";
 109     Transient_GETS,  desc="A GetS from another processor";
 110     Transient_Local_GETS,  desc="A GetS from another processor";
 111     Transient_GETS_Last_Token,  desc="A GetS from another processor";
 112     Transient_Local_GETS_Last_Token,  desc="A GetS from another processor";
 113
 114     // Lock/Unlock for distributed
 115     Persistent_GETX,     desc="Another processor has priority to read/write";
 116     Persistent_GETS,     desc="Another processor has priority to read";
 117     Persistent_GETS_Last_Token, desc="Another processor has priority to read, no more tokens";
 118     Own_Lock_or_Unlock,  desc="This processor now has priority";
 119
 120     // Triggers
 121     Request_Timeout,         desc="Timeout";
 122     Use_TimeoutStarverX,             desc="Timeout";
 123     Use_TimeoutStarverS,             desc="Timeout";
 124     Use_TimeoutNoStarvers,             desc="Timeout";
 125     Use_TimeoutNoStarvers_NoMig,     desc="Timeout Don't Migrate";
 126   }
 127
 128   // TYPES
 129
 130   // CacheEntry
 131   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 132     State CacheState,        desc="cache state";
 133     bool Dirty,              desc="Is the data dirty (different than memory)?";
 134     int Tokens,              desc="The number of tokens we're holding for the line";
 135     DataBlock DataBlk,       desc="data for the block";
 136   }
 137
 138
 139   // TBE fields
 140   structure(TBE, desc="...") {
 141     Address Address,                      desc="Physical address for this TBE";
 142     State TBEState,                       desc="Transient state";
 143     int IssueCount,      default="0",     desc="The number of times we've issued a request for this line.";
 144     Address PC,                           desc="Program counter of request";
 145
 146     bool WentPersistent, default="false",  desc="Request went persistent";
 147     bool ExternalResponse, default="false", desc="Response came from an external controller";
 148     bool IsAtomic, default="false",       desc="Request was an atomic request";
 149
 150     AccessType AccessType,                desc="Type of request (used for profiling)";
 151     Time IssueTime,                       desc="Time the request was issued";
 152     AccessModeType AccessMode,    desc="user/supervisor access type";
 153     PrefetchBit Prefetch,         desc="Is this a prefetch request";
 154   }
 155
 156   external_type(TBETable) {
 157     TBE lookup(Address);
 158     void allocate(Address);
 159     void deallocate(Address);
 160     bool isPresent(Address);
 161   }
 162
 163   external_type(PersistentTable) {
 164     void persistentRequestLock(Address, MachineID, AccessType);
 165     void persistentRequestUnlock(Address, MachineID);
 166     bool okToIssueStarving(Address, MachineID);
 167     MachineID findSmallest(Address);
 168     AccessType typeOfSmallest(Address);
 169     void markEntries(Address);
 170     bool isLocked(Address);
 171     int countStarvingForAddress(Address);
 172     int countReadStarvingForAddress(Address);
 173   }
 174
 175   void set_cache_entry(AbstractCacheEntry b);
 176   void unset_cache_entry();
 177   void set_tbe(TBE b);
 178   void unset_tbe();
 179
 180   TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
 181
 182   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 183
 184   bool starving, default="false";
 185   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 186
 187   PersistentTable persistentTable;
 188   TimerTable useTimerTable;
 189   TimerTable reissueTimerTable;
 190
 191   int outstandingRequests, default="0";
 192   int outstandingPersistentRequests, default="0";
 193
 194   int averageLatencyHysteresis, default="(8)"; // Constant that provides hysteresis for calculated the estimated average
 195   int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))";
 196
 197   int averageLatencyEstimate() {
 198     DPRINTF(RubySlicc, "%d\n",
 199             (averageLatencyCounter >> averageLatencyHysteresis));
 200     //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
 201     return averageLatencyCounter >> averageLatencyHysteresis;
 202   }
 203
 204   void updateAverageLatencyEstimate(int latency) {
 205     DPRINTF(RubySlicc, "%d\n", latency);
 206     assert(latency >= 0);
 207
 208     // By subtracting the current average and then adding the most
 209     // recent sample, we calculate an estimate of the recent average.
 210     // If we simply used a running sum and divided by the total number
 211     // of entries, the estimate of the average would adapt very slowly
 212     // after the execution has run for a long time.
 213     // averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
 214
 215     averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
 216   }
 217
 218   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 219     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 220     if(is_valid(L1Dcache_entry)) {
 221       return L1Dcache_entry;
 222     }
 223
 224     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 225     return L1Icache_entry;
 226   }
 227
 228   Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
 229     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 230     return L1Dcache_entry;
 231   }
 232
 233   Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
 234     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 235     return L1Icache_entry;
 236   }
 237
 238   int getTokens(Entry cache_entry) {
 239     if (is_valid(cache_entry)) {
 240       return cache_entry.Tokens;
 241     }
 242     return 0;
 243   }
 244
 245   State getState(TBE tbe, Entry cache_entry, Address addr) {
 246
 247     if (is_valid(tbe)) {
 248       return tbe.TBEState;
 249     } else if (is_valid(cache_entry)) {
 250       return cache_entry.CacheState;
 251     } else {
 252       if ((persistentTable.isLocked(addr) == true) && (persistentTable.findSmallest(addr) != machineID)) {
 253       // Not in cache, in persistent table, but this processor isn't highest priority
 254       return State:I_L;
 255       } else {
 256         return State:NP;
 257       }
 258     }
 259   }
 260
 261   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 262     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 263
 264     if (is_valid(tbe)) {
 265       assert(state != State:I);
 266       assert(state != State:S);
 267       assert(state != State:O);
 268       assert(state != State:MM);
 269       assert(state != State:M);
 270       tbe.TBEState := state;
 271     }
 272
 273     if (is_valid(cache_entry)) {
 274       // Make sure the token count is in range
 275       assert(cache_entry.Tokens >= 0);
 276       assert(cache_entry.Tokens <= max_tokens());
 277       assert(cache_entry.Tokens != (max_tokens() / 2));
 278
 279       if ((state == State:I_L) ||
 280           (state == State:IM_L) ||
 281           (state == State:IS_L)) {
 282         // Make sure we have no tokens in the "Invalid, locked" states
 283           assert(cache_entry.Tokens == 0);
 284
 285         // Make sure the line is locked
 286         // assert(persistentTable.isLocked(addr));
 287
 288         // But we shouldn't have highest priority for it
 289         // assert(persistentTable.findSmallest(addr) != id);
 290
 291       } else if ((state == State:S_L) ||
 292                  (state == State:SM_L)) {
 293         assert(cache_entry.Tokens >= 1);
 294         assert(cache_entry.Tokens < (max_tokens() / 2));
 295
 296         // Make sure the line is locked...
 297         // assert(persistentTable.isLocked(addr));
 298
 299         // ...But we shouldn't have highest priority for it...
 300         // assert(persistentTable.findSmallest(addr) != id);
 301
 302         // ...And it must be a GETS request
 303         // assert(persistentTable.typeOfSmallest(addr) == AccessType:Read);
 304
 305       } else {
 306
 307         // If there is an entry in the persistent table of this block,
 308         // this processor needs to have an entry in the table for this
 309         // block, and that entry better be the smallest (highest
 310         // priority).  Otherwise, the state should have been one of
 311         // locked states
 312
 313         //if (persistentTable.isLocked(addr)) {
 314         //  assert(persistentTable.findSmallest(addr) == id);
 315         //}
 316       }
 317
 318       // in M and E you have all the tokens
 319       if (state == State:MM || state == State:M || state == State:MM_W || state == State:M_W) {
 320         assert(cache_entry.Tokens == max_tokens());
 321       }
 322
 323       // in NP you have no tokens
 324       if (state == State:NP) {
 325         assert(cache_entry.Tokens == 0);
 326       }
 327
 328       // You have at least one token in S-like states
 329       if (state == State:S || state == State:SM) {
 330         assert(cache_entry.Tokens > 0);
 331       }
 332
 333       // You have at least half the token in O-like states
 334       if (state == State:O && state == State:OM) {
 335         assert(cache_entry.Tokens > (max_tokens() / 2));
 336       }
 337
 338       cache_entry.CacheState := state;
 339
 340       // Set permission
 341       if (state == State:MM ||
 342           state == State:MM_W) {
 343         cache_entry.changePermission(AccessPermission:Read_Write);
 344       } else if ((state == State:S) ||
 345                  (state == State:O) ||
 346                  (state == State:M) ||
 347                  (state == State:M_W) ||
 348                  (state == State:SM) ||
 349                  (state == State:S_L) ||
 350                  (state == State:SM_L) ||
 351                  (state == State:OM)) {
 352         cache_entry.changePermission(AccessPermission:Read_Only);
 353       } else {
 354         cache_entry.changePermission(AccessPermission:Invalid);
 355       }
 356     }
 357   }
 358
 359   Event mandatory_request_type_to_event(CacheRequestType type) {
 360     if (type == CacheRequestType:LD) {
 361       return Event:Load;
 362     } else if (type == CacheRequestType:IFETCH) {
 363       return Event:Ifetch;
 364     } else if (type == CacheRequestType:ST) {
 365       return Event:Store;
 366     } else if (type == CacheRequestType:ATOMIC) {
 367       if (no_mig_atomic) {
 368         return Event:Atomic;
 369       } else {
 370         return Event:Store;
 371       }
 372     } else {
 373       error("Invalid CacheRequestType");
 374     }
 375   }
 376
 377   AccessType cache_request_type_to_access_type(CacheRequestType type) {
 378     if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) {
 379       return AccessType:Read;
 380     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 381       return AccessType:Write;
 382     } else {
 383       error("Invalid CacheRequestType");
 384     }
 385   }
 386
 387   GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
 388     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
 389       //
 390       // NOTE direct local hits should not call this
 391       //
 392       return GenericMachineType:L1Cache_wCC;
 393     } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
 394
 395       if (sender == (mapAddressToRange(addr,
 396                                        MachineType:L2Cache,
 397                                        l2_select_low_bit,
 398                                        l2_select_num_bits))) {
 399
 400         return GenericMachineType:L2Cache;
 401       } else {
 402         return GenericMachineType:L2Cache_wCC;
 403       }
 404     } else {
 405       return ConvertMachToGenericMach(machineIDToMachineType(sender));
 406     }
 407   }
 408
 409   bool okToIssueStarving(Address addr, MachineID machinID) {
 410     return persistentTable.okToIssueStarving(addr, machineID);
 411   }
 412
 413   void markPersistentEntries(Address addr) {
 414     persistentTable.markEntries(addr);
 415   }
 416
 417   void setExternalResponse(TBE tbe) {
 418     assert(is_valid(tbe));
 419     tbe.ExternalResponse := true;
 420   }
 421
 422   bool IsAtomic(TBE tbe) {
 423     assert(is_valid(tbe));
 424     return tbe.IsAtomic;
 425   }
 426
 427   // ** OUT_PORTS **
 428   out_port(persistentNetwork_out, PersistentMsg, persistentFromL1Cache);
 429   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 430   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 431   out_port(requestRecycle_out, RequestMsg, requestToL1Cache);
 432
 433   // ** IN_PORTS **
 434
 435   // Use Timer
 436   in_port(useTimerTable_in, Address, useTimerTable) {
 437     if (useTimerTable_in.isReady()) {
 438       TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
 439
 440       if (persistentTable.isLocked(useTimerTable.readyAddress()) &&
 441           (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
 442         if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
 443           trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress(),
 444                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 445         } else {
 446           trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress(),
 447                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 448         }
 449       } else {
 450         if (no_mig_atomic && IsAtomic(tbe)) {
 451           trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress(),
 452                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 453         } else {
 454           trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress(),
 455                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 456         }
 457       }
 458     }
 459   }
 460
 461   // Reissue Timer
 462   in_port(reissueTimerTable_in, Address, reissueTimerTable) {
 463     if (reissueTimerTable_in.isReady()) {
 464       trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
 465               getCacheEntry(reissueTimerTable.readyAddress()),
 466               L1_TBEs[reissueTimerTable.readyAddress()]);
 467     }
 468   }
 469
 470
 471
 472   // Persistent Network
 473   in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache) {
 474     if (persistentNetwork_in.isReady()) {
 475       peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
 476         assert(in_msg.Destination.isElement(machineID));
 477
 478         // Apply the lockdown or unlockdown message to the table
 479         if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
 480           persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
 481         } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
 482           persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
 483         } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
 484           persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
 485         } else {
 486           error("Unexpected message");
 487         }
 488
 489         // React to the message based on the current state of the table
 490         Entry cache_entry := getCacheEntry(in_msg.Address);
 491         TBE tbe := L1_TBEs[in_msg.Address];
 492
 493         if (persistentTable.isLocked(in_msg.Address)) {
 494           if (persistentTable.findSmallest(in_msg.Address) == machineID) {
 495             // Our Own Lock - this processor is highest priority
 496             trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 497                     cache_entry, tbe);
 498           } else {
 499             if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
 500               if (getTokens(cache_entry) == 1 ||
 501                   getTokens(cache_entry) == (max_tokens() / 2) + 1) {
 502                 trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
 503                         cache_entry, tbe);
 504               } else {
 505                 trigger(Event:Persistent_GETS, in_msg.Address,
 506                         cache_entry, tbe);
 507               }
 508             } else {
 509               trigger(Event:Persistent_GETX, in_msg.Address,
 510                       cache_entry, tbe);
 511             }
 512           }
 513         } else {
 514           // Unlock case - no entries in the table
 515           trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 516                   cache_entry, tbe);
 517         }
 518       }
 519     }
 520   }
 521
 522
 523   // Request Network
 524   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 525     if (requestNetwork_in.isReady()) {
 526       peek(requestNetwork_in, RequestMsg, block_on="Address") {
 527         assert(in_msg.Destination.isElement(machineID));
 528
 529         Entry cache_entry := getCacheEntry(in_msg.Address);
 530         TBE tbe := L1_TBEs[in_msg.Address];
 531
 532         if (in_msg.Type == CoherenceRequestType:GETX) {
 533           if (in_msg.isLocal) {
 534             trigger(Event:Transient_Local_GETX, in_msg.Address,
 535                     cache_entry, tbe);
 536           }
 537           else {
 538             trigger(Event:Transient_GETX, in_msg.Address,
 539                     cache_entry, tbe);
 540           }
 541         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 542           if (getTokens(cache_entry) == 1 ||
 543               getTokens(cache_entry) == (max_tokens() / 2) + 1) {
 544             if (in_msg.isLocal) {
 545               trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
 546                       cache_entry, tbe);
 547             }
 548             else {
 549               trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
 550                       cache_entry, tbe);
 551             }
 552           }
 553           else {
 554             if (in_msg.isLocal) {
 555               trigger(Event:Transient_Local_GETS, in_msg.Address,
 556                       cache_entry, tbe);
 557             }
 558             else {
 559               trigger(Event:Transient_GETS, in_msg.Address,
 560                       cache_entry, tbe);
 561             }
 562           }
 563         } else {
 564           error("Unexpected message");
 565         }
 566       }
 567     }
 568   }
 569
 570   // Response Network
 571   in_port(responseNetwork_in, ResponseMsg, responseToL1Cache) {
 572     if (responseNetwork_in.isReady()) {
 573       peek(responseNetwork_in, ResponseMsg, block_on="Address") {
 574         assert(in_msg.Destination.isElement(machineID));
 575
 576         Entry cache_entry := getCacheEntry(in_msg.Address);
 577         TBE tbe := L1_TBEs[in_msg.Address];
 578
 579         // Mark TBE flag if response received off-chip.  Use this to update average latency estimate
 580         if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
 581
 582           if (in_msg.Sender == mapAddressToRange(in_msg.Address,
 583                                                  MachineType:L2Cache,
 584                                                  l2_select_low_bit,
 585                                                  l2_select_num_bits)) {
 586
 587             // came from an off-chip L2 cache
 588             if (is_valid(tbe)) {
 589                // L1_TBEs[in_msg.Address].ExternalResponse := true;
 590                // profile_offchipL2_response(in_msg.Address);
 591             }
 592           }
 593           else {
 594                // profile_onchipL2_response(in_msg.Address );
 595           }
 596         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
 597           if (is_valid(tbe)) {
 598             setExternalResponse(tbe);
 599             // profile_memory_response( in_msg.Address);
 600           }
 601         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 602           //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
 603             //if (is_valid(tbe)) {
 604                // tbe.ExternalResponse := true;
 605                // profile_offchipL1_response(in_msg.Address );
 606             //}
 607           //}
 608           //else {
 609                // profile_onchipL1_response(in_msg.Address );
 610           //}
 611         } else {
 612           error("unexpected SenderMachine");
 613         }
 614
 615
 616         if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
 617           if (in_msg.Type == CoherenceResponseType:ACK) {
 618             assert(in_msg.Tokens < (max_tokens() / 2));
 619             trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
 620           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
 621             trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
 622           } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 623             assert(in_msg.Tokens < (max_tokens() / 2));
 624             trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
 625           } else {
 626             error("Unexpected message");
 627           }
 628         } else {
 629           if (in_msg.Type == CoherenceResponseType:ACK) {
 630             assert(in_msg.Tokens < (max_tokens() / 2));
 631             trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
 632           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 633             trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
 634           } else {
 635             error("Unexpected message");
 636           }
 637         }
 638       }
 639     }
 640   }
 641
 642   // Mandatory Queue
 643   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 644     if (mandatoryQueue_in.isReady()) {
 645       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 646         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 647
 648         TBE tbe := L1_TBEs[in_msg.LineAddress];
 649
 650         if (in_msg.Type == CacheRequestType:IFETCH) {
 651           // ** INSTRUCTION ACCESS ***
 652
 653           // Check to see if it is in the OTHER L1
 654           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 655           if (is_valid(L1Dcache_entry)) {
 656             // The block is in the wrong L1, try to write it to the L2
 657               trigger(Event:L1_Replacement, in_msg.LineAddress,
 658                       L1Dcache_entry, tbe);
 659           }
 660
 661           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 662           if (is_valid(L1Icache_entry)) {
 663             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 664             trigger(mandatory_request_type_to_event(in_msg.Type),
 665                     in_msg.LineAddress, L1Icache_entry, tbe);
 666           } else {
 667             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 668               // L1 does't have the line, but we have space for it in the L1
 669               trigger(mandatory_request_type_to_event(in_msg.Type),
 670                       in_msg.LineAddress, L1Icache_entry, tbe);
 671             } else {
 672               // No room in the L1, so we need to make room
 673               trigger(Event:L1_Replacement,
 674                       L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 675                       getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 676                       L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 677             }
 678           }
 679         } else {
 680           // *** DATA ACCESS ***
 681
 682             // Check to see if it is in the OTHER L1
 683           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 684
 685           if (is_valid(L1Icache_entry)) {
 686             // The block is in the wrong L1, try to write it to the L2
 687             trigger(Event:L1_Replacement, in_msg.LineAddress,
 688                     L1Icache_entry, tbe);
 689           }
 690
 691           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 692           if (is_valid(L1Dcache_entry)) {
 693             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 694             trigger(mandatory_request_type_to_event(in_msg.Type),
 695                     in_msg.LineAddress, L1Dcache_entry, tbe);
 696           } else {
 697             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 698               // L1 does't have the line, but we have space for it in the L1
 699               trigger(mandatory_request_type_to_event(in_msg.Type),
 700                       in_msg.LineAddress, L1Dcache_entry, tbe);
 701             } else {
 702               // No room in the L1, so we need to make room
 703               trigger(Event:L1_Replacement,
 704                       L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 705                       getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 706                       L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 707             }
 708           }
 709         }
 710       }
 711     }
 712   }
 713
 714   // ACTIONS
 715
 716   action(a_issueReadRequest, "a", desc="Issue GETS") {
 717       assert(is_valid(tbe));
 718       if (tbe.IssueCount == 0) {
 719         // Update outstanding requests
 720         //profile_outstanding_request(outstandingRequests);
 721         outstandingRequests := outstandingRequests + 1;
 722       }
 723
 724       if (tbe.IssueCount >= retry_threshold) {
 725         // Issue a persistent request if possible
 726         if (okToIssueStarving(address, machineID) && (starving == false)) {
 727           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
 728             out_msg.Address := address;
 729             out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
 730             out_msg.Requestor := machineID;
 731             out_msg.Destination.broadcast(MachineType:L1Cache);
 732
 733             //
 734             // Currently the configuration system limits the system to only one
 735             // chip.  Therefore, if we assume one shared L2 cache, then only one
 736             // pertinent L2 cache exist.
 737             //
 738             //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 739
 740             out_msg.Destination.add(mapAddressToRange(address,
 741                                                       MachineType:L2Cache,
 742                                                       l2_select_low_bit,
 743                                                       l2_select_num_bits));
 744
 745             out_msg.Destination.add(map_Address_to_Directory(address));
 746             out_msg.MessageSize := MessageSizeType:Persistent_Control;
 747             out_msg.Prefetch := tbe.Prefetch;
 748             out_msg.AccessMode := tbe.AccessMode;
 749           }
 750           markPersistentEntries(address);
 751           starving := true;
 752
 753           if (tbe.IssueCount == 0) {
 754             //profile_persistent_prediction(address, tbe.AccessType);
 755           }
 756
 757           // Update outstanding requests
 758           //profile_outstanding_persistent_request(outstandingPersistentRequests);
 759           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 760
 761           // Increment IssueCount
 762           tbe.IssueCount := tbe.IssueCount + 1;
 763
 764           tbe.WentPersistent := true;
 765
 766           // Do not schedule a wakeup, a persistent requests will always complete
 767         }
 768         else {
 769
 770           // We'd like to issue a persistent request, but are not allowed
 771           // to issue a P.R. right now.  This, we do not increment the
 772           // IssueCount.
 773
 774           // Set a wakeup timer
 775           reissueTimerTable.set(address, 10);
 776
 777         }
 778       } else {
 779         // Make a normal request
 780         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 781           out_msg.Address := address;
 782           out_msg.Type := CoherenceRequestType:GETS;
 783           out_msg.Requestor := machineID;
 784           out_msg.Destination.add(mapAddressToRange(address,
 785                                                     MachineType:L2Cache,
 786                                                     l2_select_low_bit,
 787                                                     l2_select_num_bits));
 788
 789           out_msg.RetryNum := tbe.IssueCount;
 790           if (tbe.IssueCount == 0) {
 791             out_msg.MessageSize := MessageSizeType:Request_Control;
 792           } else {
 793             out_msg.MessageSize := MessageSizeType:Reissue_Control;
 794           }
 795           out_msg.Prefetch := tbe.Prefetch;
 796           out_msg.AccessMode := tbe.AccessMode;
 797         }
 798
 799         // send to other local L1s, with local bit set
 800         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 801           out_msg.Address := address;
 802           out_msg.Type := CoherenceRequestType:GETS;
 803           out_msg.Requestor := machineID;
 804           //
 805           // Since only one chip, assuming all L1 caches are local
 806           //
 807           //out_msg.Destination := getOtherLocalL1IDs(machineID);
 808           out_msg.Destination.broadcast(MachineType:L1Cache);
 809           out_msg.Destination.remove(machineID);
 810
 811           out_msg.RetryNum := tbe.IssueCount;
 812           out_msg.isLocal := true;
 813           if (tbe.IssueCount == 0) {
 814             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 815           } else {
 816             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 817           }
 818           out_msg.Prefetch := tbe.Prefetch;
 819           out_msg.AccessMode := tbe.AccessMode;
 820         }
 821
 822         // Increment IssueCount
 823         tbe.IssueCount := tbe.IssueCount + 1;
 824
 825         // Set a wakeup timer
 826
 827         if (dynamic_timeout_enabled) {
 828           reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
 829         } else {
 830           reissueTimerTable.set(address, fixed_timeout_latency);
 831         }
 832
 833       }
 834   }
 835
 836   action(b_issueWriteRequest, "b", desc="Issue GETX") {
 837
 838       assert(is_valid(tbe));
 839       if (tbe.IssueCount == 0) {
 840         // Update outstanding requests
 841         //profile_outstanding_request(outstandingRequests);
 842         outstandingRequests := outstandingRequests + 1;
 843       }
 844
 845       if (tbe.IssueCount >= retry_threshold) {
 846         // Issue a persistent request if possible
 847         if ( okToIssueStarving(address, machineID) && (starving == false)) {
 848           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
 849             out_msg.Address := address;
 850             out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
 851             out_msg.Requestor := machineID;
 852             out_msg.Destination.broadcast(MachineType:L1Cache);
 853
 854             //
 855             // Currently the configuration system limits the system to only one
 856             // chip.  Therefore, if we assume one shared L2 cache, then only one
 857             // pertinent L2 cache exist.
 858             //
 859             //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 860
 861             out_msg.Destination.add(mapAddressToRange(address,
 862                                                       MachineType:L2Cache,
 863                                                       l2_select_low_bit,
 864                                                       l2_select_num_bits));
 865
 866             out_msg.Destination.add(map_Address_to_Directory(address));
 867             out_msg.MessageSize := MessageSizeType:Persistent_Control;
 868             out_msg.Prefetch := tbe.Prefetch;
 869             out_msg.AccessMode := tbe.AccessMode;
 870           }
 871           markPersistentEntries(address);
 872           starving := true;
 873
 874           // Update outstanding requests
 875           //profile_outstanding_persistent_request(outstandingPersistentRequests);
 876           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 877
 878           if (tbe.IssueCount == 0) {
 879             //profile_persistent_prediction(address, tbe.AccessType);
 880           }
 881
 882           // Increment IssueCount
 883           tbe.IssueCount := tbe.IssueCount + 1;
 884
 885           tbe.WentPersistent := true;
 886
 887           // Do not schedule a wakeup, a persistent requests will always complete
 888         }
 889         else {
 890
 891           // We'd like to issue a persistent request, but are not allowed
 892           // to issue a P.R. right now.  This, we do not increment the
 893           // IssueCount.
 894
 895           // Set a wakeup timer
 896           reissueTimerTable.set(address, 10);
 897         }
 898
 899
 900       } else  {
 901         // Make a normal request
 902         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 903           out_msg.Address := address;
 904           out_msg.Type := CoherenceRequestType:GETX;
 905           out_msg.Requestor := machineID;
 906
 907           out_msg.Destination.add(mapAddressToRange(address,
 908                                                     MachineType:L2Cache,
 909                                                     l2_select_low_bit,
 910                                                     l2_select_num_bits));
 911
 912           out_msg.RetryNum := tbe.IssueCount;
 913
 914           if (tbe.IssueCount == 0) {
 915             out_msg.MessageSize := MessageSizeType:Request_Control;
 916           } else {
 917             out_msg.MessageSize := MessageSizeType:Reissue_Control;
 918           }
 919           out_msg.Prefetch := tbe.Prefetch;
 920           out_msg.AccessMode := tbe.AccessMode;
 921         }
 922
 923         // send to other local L1s too
 924         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 925           out_msg.Address := address;
 926           out_msg.Type := CoherenceRequestType:GETX;
 927           out_msg.Requestor := machineID;
 928           out_msg.isLocal := true;
 929
 930           //
 931           // Since only one chip, assuming all L1 caches are local
 932           //
 933           //out_msg.Destination := getOtherLocalL1IDs(machineID);
 934           out_msg.Destination.broadcast(MachineType:L1Cache);
 935           out_msg.Destination.remove(machineID);
 936
 937           out_msg.RetryNum := tbe.IssueCount;
 938           if (tbe.IssueCount == 0) {
 939             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 940           } else {
 941             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 942           }
 943           out_msg.Prefetch := tbe.Prefetch;
 944           out_msg.AccessMode := tbe.AccessMode;
 945         }
 946
 947         // Increment IssueCount
 948         tbe.IssueCount := tbe.IssueCount + 1;
 949
 950         DPRINTF(RubySlicc, "incremented issue count to %d\n",
 951                 tbe.IssueCount);
 952
 953         // Set a wakeup timer
 954         if (dynamic_timeout_enabled) {
 955           reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
 956         } else {
 957           reissueTimerTable.set(address, fixed_timeout_latency);
 958         }
 959       }
 960   }
 961
 962   action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") {
 963     peek(responseNetwork_in, ResponseMsg) {
 964       // FIXME, should use a 3rd vnet
 965       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 966         out_msg.Address := address;
 967         out_msg.Type := in_msg.Type;
 968         out_msg.Sender := machineID;
 969         out_msg.Destination.add(map_Address_to_Directory(address));
 970         out_msg.Tokens := in_msg.Tokens;
 971         out_msg.MessageSize := in_msg.MessageSize;
 972         out_msg.DataBlk := in_msg.DataBlk;
 973         out_msg.Dirty := in_msg.Dirty;
 974       }
 975     }
 976   }
 977
 978   action(c_ownedReplacement, "c", desc="Issue writeback") {
 979     assert(is_valid(cache_entry));
 980     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
 981       out_msg.Address := address;
 982       out_msg.Sender := machineID;
 983
 984       out_msg.Destination.add(mapAddressToRange(address,
 985                                                 MachineType:L2Cache,
 986                                                 l2_select_low_bit,
 987                                                 l2_select_num_bits));
 988
 989       out_msg.Tokens := cache_entry.Tokens;
 990       out_msg.DataBlk := cache_entry.DataBlk;
 991       out_msg.Dirty := cache_entry.Dirty;
 992       out_msg.Type := CoherenceResponseType:WB_OWNED;
 993
 994       // always send the data?
 995       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 996     }
 997     cache_entry.Tokens := 0;
 998   }
 999
1000   action(cc_sharedReplacement, "\c", desc="Issue shared writeback") {
1001
1002     // don't send writeback if replacing block with no tokens
1003     assert(is_valid(cache_entry));
1004     assert (cache_entry.Tokens > 0);
1005     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1006         out_msg.Address := address;
1007         out_msg.Sender := machineID;
1008
1009         out_msg.Destination.add(mapAddressToRange(address,
1010                                                   MachineType:L2Cache,
1011                                                   l2_select_low_bit,
1012                                                   l2_select_num_bits));
1013
1014         out_msg.Tokens := cache_entry.Tokens;
1015         out_msg.DataBlk := cache_entry.DataBlk;
1016         // assert(cache_entry.Dirty == false);
1017         out_msg.Dirty := false;
1018
1019         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1020         out_msg.Type := CoherenceResponseType:WB_SHARED_DATA;
1021     }
1022     cache_entry.Tokens := 0;
1023   }
1024
1025   action(tr_tokenReplacement, "tr", desc="Issue token writeback") {
1026     assert(is_valid(cache_entry));
1027     if (cache_entry.Tokens > 0) {
1028       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1029         out_msg.Address := address;
1030         out_msg.Sender := machineID;
1031
1032         out_msg.Destination.add(mapAddressToRange(address,
1033                                                   MachineType:L2Cache,
1034                                                   l2_select_low_bit,
1035                                                   l2_select_num_bits));
1036
1037         out_msg.Tokens := cache_entry.Tokens;
1038         out_msg.DataBlk := cache_entry.DataBlk;
1039         // assert(cache_entry.Dirty == false);
1040         out_msg.Dirty := false;
1041
1042         // always send the data?
1043         out_msg.MessageSize := MessageSizeType:Writeback_Control;
1044         out_msg.Type := CoherenceResponseType:WB_TOKENS;
1045       }
1046     }
1047     cache_entry.Tokens := 0;
1048   }
1049
1050
1051   action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") {
1052     assert(is_valid(cache_entry));
1053     peek(requestNetwork_in, RequestMsg) {
1054       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1055         out_msg.Address := address;
1056         out_msg.Type := CoherenceResponseType:DATA_SHARED;
1057         out_msg.Sender := machineID;
1058         out_msg.Destination.add(in_msg.Requestor);
1059         out_msg.Tokens := 1;
1060         out_msg.DataBlk := cache_entry.DataBlk;
1061         // out_msg.Dirty := cache_entry.Dirty;
1062         out_msg.Dirty := false;
1063         if (in_msg.isLocal) {
1064           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1065         } else {
1066           out_msg.MessageSize := MessageSizeType:Response_Data;
1067         }
1068       }
1069     }
1070     cache_entry.Tokens := cache_entry.Tokens - 1;
1071     assert(cache_entry.Tokens >= 1);
1072   }
1073
1074   action(d_sendDataWithNTokenIfAvail, "\dd", desc="Send data and a token from cache to requestor") {
1075     assert(is_valid(cache_entry));
1076     peek(requestNetwork_in, RequestMsg) {
1077       if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1078         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1079           out_msg.Address := address;
1080           out_msg.Type := CoherenceResponseType:DATA_SHARED;
1081           out_msg.Sender := machineID;
1082           out_msg.Destination.add(in_msg.Requestor);
1083           out_msg.Tokens := N_tokens;
1084           out_msg.DataBlk := cache_entry.DataBlk;
1085           // out_msg.Dirty := cache_entry.Dirty;
1086           out_msg.Dirty := false;
1087           if (in_msg.isLocal) {
1088             out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1089           } else {
1090             out_msg.MessageSize := MessageSizeType:Response_Data;
1091           }
1092         }
1093         cache_entry.Tokens := cache_entry.Tokens - N_tokens;
1094       }
1095       else if (cache_entry.Tokens > 1) {
1096         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1097           out_msg.Address := address;
1098           out_msg.Type := CoherenceResponseType:DATA_SHARED;
1099           out_msg.Sender := machineID;
1100           out_msg.Destination.add(in_msg.Requestor);
1101           out_msg.Tokens := 1;
1102           out_msg.DataBlk := cache_entry.DataBlk;
1103           // out_msg.Dirty := cache_entry.Dirty;
1104           out_msg.Dirty := false;
1105           if (in_msg.isLocal) {
1106             out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1107           } else {
1108             out_msg.MessageSize := MessageSizeType:Response_Data;
1109           }
1110         }
1111         cache_entry.Tokens := cache_entry.Tokens - 1;
1112       }
1113     }
1114 //    assert(cache_entry.Tokens >= 1);
1115   }
1116
1117   action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") {
1118     peek(requestNetwork_in, RequestMsg) {
1119     assert(is_valid(cache_entry));
1120       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1121         out_msg.Address := address;
1122         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1123         out_msg.Sender := machineID;
1124         out_msg.Destination.add(in_msg.Requestor);
1125         assert(cache_entry.Tokens > (max_tokens() / 2));
1126         out_msg.Tokens := cache_entry.Tokens;
1127         out_msg.DataBlk := cache_entry.DataBlk;
1128         out_msg.Dirty := cache_entry.Dirty;
1129         if (in_msg.isLocal) {
1130           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1131         } else {
1132           out_msg.MessageSize := MessageSizeType:Response_Data;
1133         }
1134       }
1135     }
1136     cache_entry.Tokens := 0;
1137   }
1138
1139   action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") {
1140     // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1141     assert(is_valid(cache_entry));
1142     if (cache_entry.Tokens > 0) {
1143       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1144         out_msg.Address := address;
1145         if (cache_entry.Tokens > (max_tokens() / 2)) {
1146           out_msg.Type := CoherenceResponseType:DATA_OWNER;
1147         } else {
1148           out_msg.Type := CoherenceResponseType:ACK;
1149         }
1150         out_msg.Sender := machineID;
1151         out_msg.Destination.add(persistentTable.findSmallest(address));
1152         assert(cache_entry.Tokens >= 1);
1153         out_msg.Tokens := cache_entry.Tokens;
1154         out_msg.DataBlk := cache_entry.DataBlk;
1155         out_msg.MessageSize := MessageSizeType:Response_Control;
1156       }
1157     }
1158     cache_entry.Tokens := 0;
1159   }
1160
1161   action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
1162     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1163     assert(is_valid(cache_entry));
1164     assert(cache_entry.Tokens > 0);
1165     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1166       out_msg.Address := address;
1167       out_msg.Type := CoherenceResponseType:DATA_OWNER;
1168       out_msg.Sender := machineID;
1169       out_msg.Destination.add(persistentTable.findSmallest(address));
1170       assert(cache_entry.Tokens > (max_tokens() / 2));
1171       out_msg.Tokens := cache_entry.Tokens;
1172       out_msg.DataBlk := cache_entry.DataBlk;
1173       out_msg.Dirty := cache_entry.Dirty;
1174       out_msg.MessageSize := MessageSizeType:Response_Data;
1175     }
1176     cache_entry.Tokens := 0;
1177   }
1178
1179   action(f_sendAckWithAllButNorOneTokens, "f", desc="Send ack with all our tokens but one to starver.") {
1180     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1181     assert(is_valid(cache_entry));
1182     assert(cache_entry.Tokens > 0);
1183     if (cache_entry.Tokens > 1) {
1184       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1185         out_msg.Address := address;
1186         if (cache_entry.Tokens > (max_tokens() / 2)) {
1187           out_msg.Type := CoherenceResponseType:DATA_OWNER;
1188         } else {
1189           out_msg.Type := CoherenceResponseType:ACK;
1190         }
1191         out_msg.Sender := machineID;
1192         out_msg.Destination.add(persistentTable.findSmallest(address));
1193         assert(cache_entry.Tokens >= 1);
1194         if (cache_entry.Tokens > N_tokens) {
1195           out_msg.Tokens := cache_entry.Tokens - N_tokens;
1196         } else {
1197           out_msg.Tokens := cache_entry.Tokens - 1;
1198         }
1199         out_msg.DataBlk := cache_entry.DataBlk;
1200         out_msg.MessageSize := MessageSizeType:Response_Control;
1201       }
1202     }
1203     if (cache_entry.Tokens > N_tokens) {
1204       cache_entry.Tokens := N_tokens;
1205     } else {
1206       cache_entry.Tokens := 1;
1207     }
1208   }
1209
1210   action(ff_sendDataWithAllButNorOneTokens, "\f", desc="Send data and out tokens but one to starver") {
1211     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1212     assert(is_valid(cache_entry));
1213     assert(cache_entry.Tokens > ((max_tokens() / 2) + 1));
1214     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1215         out_msg.Address := address;
1216         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1217         out_msg.Sender := machineID;
1218         out_msg.Destination.add(persistentTable.findSmallest(address));
1219         if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1220           out_msg.Tokens := cache_entry.Tokens - N_tokens;
1221         } else {
1222           out_msg.Tokens := cache_entry.Tokens - 1;
1223         }
1224         assert(out_msg.Tokens > (max_tokens() / 2));
1225         out_msg.DataBlk := cache_entry.DataBlk;
1226         out_msg.Dirty := cache_entry.Dirty;
1227         out_msg.MessageSize := MessageSizeType:Response_Data;
1228     }
1229     if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1230       cache_entry.Tokens := N_tokens;
1231     } else {
1232       cache_entry.Tokens := 1;
1233     }
1234   }
1235
1236   action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") {
1237     assert(is_valid(cache_entry));
1238     assert(cache_entry.Tokens == ((max_tokens() / 2) + 1));
1239     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1240         out_msg.Address := address;
1241         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1242         out_msg.Sender := machineID;
1243         out_msg.Destination.add(persistentTable.findSmallest(address));
1244         out_msg.Tokens := cache_entry.Tokens;
1245         assert(out_msg.Tokens > (max_tokens() / 2));
1246         out_msg.DataBlk := cache_entry.DataBlk;
1247         out_msg.Dirty := cache_entry.Dirty;
1248         out_msg.MessageSize := MessageSizeType:Response_Data;
1249     }
1250     cache_entry.Tokens := 0;
1251   }
1252
1253   action(g_bounceResponseToStarver, "g", desc="Redirect response to starving processor") {
1254     // assert(persistentTable.isLocked(address));
1255
1256     peek(responseNetwork_in, ResponseMsg) {
1257       // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1258       // FIXME, should use a 3rd vnet in some cases
1259       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
1260         out_msg.Address := address;
1261         out_msg.Type := in_msg.Type;
1262         out_msg.Sender := machineID;
1263         out_msg.Destination.add(persistentTable.findSmallest(address));
1264         out_msg.Tokens := in_msg.Tokens;
1265         out_msg.DataBlk := in_msg.DataBlk;
1266         out_msg.Dirty := in_msg.Dirty;
1267         out_msg.MessageSize := in_msg.MessageSize;
1268       }
1269     }
1270   }
1271
1272
1273   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
1274     assert(is_valid(cache_entry));
1275     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1276             address, cache_entry.DataBlk);
1277
1278     sequencer.readCallback(address,
1279                            GenericMachineType:L1Cache,
1280                            cache_entry.DataBlk);
1281
1282   }
1283
1284   action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
1285     assert(is_valid(cache_entry));
1286     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1287             address, cache_entry.DataBlk);
1288     peek(responseNetwork_in, ResponseMsg) {
1289
1290       sequencer.readCallback(address,
1291                              getNondirectHitMachType(address, in_msg.Sender),
1292                              cache_entry.DataBlk);
1293
1294     }
1295   }
1296
1297   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
1298     assert(is_valid(cache_entry));
1299     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1300             address, cache_entry.DataBlk);
1301
1302     sequencer.writeCallback(address,
1303                             GenericMachineType:L1Cache,
1304                             cache_entry.DataBlk);
1305
1306     cache_entry.Dirty := true;
1307     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1308   }
1309
1310   action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
1311     assert(is_valid(cache_entry));
1312     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1313             address, cache_entry.DataBlk);
1314     peek(responseNetwork_in, ResponseMsg) {
1315
1316       sequencer.writeCallback(address,
1317                               getNondirectHitMachType(address, in_msg.Sender),
1318                               cache_entry.DataBlk);
1319
1320     }
1321     cache_entry.Dirty := true;
1322     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1323   }
1324
1325   action(i_allocateTBE, "i", desc="Allocate TBE") {
1326     check_allocate(L1_TBEs);
1327     L1_TBEs.allocate(address);
1328     set_tbe(L1_TBEs[address]);
1329     tbe.IssueCount := 0;
1330     peek(mandatoryQueue_in, CacheMsg) {
1331       tbe.PC := in_msg.ProgramCounter;
1332       tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
1333       if (in_msg.Type == CacheRequestType:ATOMIC) {
1334         tbe.IsAtomic := true;
1335       }
1336       tbe.Prefetch := in_msg.Prefetch;
1337       tbe.AccessMode := in_msg.AccessMode;
1338     }
1339     tbe.IssueTime := get_time();
1340   }
1341
1342
1343   action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
1344     if (reissueTimerTable.isSet(address)) {
1345       reissueTimerTable.unset(address);
1346     }
1347   }
1348
1349   action(jj_unsetUseTimer, "\j", desc="Unset use timer.") {
1350     useTimerTable.unset(address);
1351   }
1352
1353   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
1354     mandatoryQueue_in.dequeue();
1355   }
1356
1357   action(l_popPersistentQueue, "l", desc="Pop persistent queue.") {
1358     persistentNetwork_in.dequeue();
1359   }
1360
1361   action(m_popRequestQueue, "m", desc="Pop request queue.") {
1362     requestNetwork_in.dequeue();
1363   }
1364
1365   action(n_popResponseQueue, "n", desc="Pop response queue") {
1366     responseNetwork_in.dequeue();
1367   }
1368
1369   action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
1370     useTimerTable.set(address, 50);
1371   }
1372
1373   action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
1374     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1375        out_msg.Address := address;
1376        out_msg.Type := CoherenceResponseType:INV;
1377        out_msg.Tokens := 0;
1378        out_msg.Sender := machineID;
1379
1380        out_msg.Destination.add(mapAddressToRange(address,
1381                                                  MachineType:L2Cache,
1382                                                  l2_select_low_bit,
1383                                                  l2_select_num_bits));
1384
1385        out_msg.MessageSize := MessageSizeType:Response_Control;
1386     }
1387   }
1388
1389
1390   action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
1391     peek(responseNetwork_in, ResponseMsg) {
1392       assert(is_valid(cache_entry));
1393       assert(in_msg.Tokens != 0);
1394       DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
1395               in_msg.Address, in_msg.Tokens);
1396       cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
1397       DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
1398
1399       if (cache_entry.Dirty == false && in_msg.Dirty) {
1400         cache_entry.Dirty := true;
1401       }
1402     }
1403   }
1404
1405   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1406
1407     assert(is_valid(tbe));
1408     if (tbe.WentPersistent) {
1409       // assert(starving == true);
1410       outstandingRequests := outstandingRequests - 1;
1411       enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
1412         out_msg.Address := address;
1413         out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
1414         out_msg.Requestor := machineID;
1415         out_msg.Destination.broadcast(MachineType:L1Cache);
1416
1417         //
1418         // Currently the configuration system limits the system to only one
1419         // chip.  Therefore, if we assume one shared L2 cache, then only one
1420         // pertinent L2 cache exist.
1421         //
1422         //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
1423
1424         out_msg.Destination.add(mapAddressToRange(address,
1425                                                   MachineType:L2Cache,
1426                                                   l2_select_low_bit,
1427                                                   l2_select_num_bits));
1428
1429         out_msg.Destination.add(map_Address_to_Directory(address));
1430         out_msg.MessageSize := MessageSizeType:Persistent_Control;
1431       }
1432       starving := false;
1433     }
1434
1435     // Update average latency
1436     if (tbe.IssueCount <= 1) {
1437       if (tbe.ExternalResponse == true) {
1438         updateAverageLatencyEstimate(time_to_int(get_time()) - time_to_int(tbe.IssueTime));
1439       }
1440     }
1441
1442     // Profile
1443     //if (tbe.WentPersistent) {
1444     //  profile_token_retry(address, tbe.AccessType, 2);
1445     //}
1446     //else {
1447     //  profile_token_retry(address, tbe.AccessType, 1);
1448     //}
1449
1450     //profile_token_retry(address, tbe.AccessType, tbe.IssueCount);
1451     L1_TBEs.deallocate(address);
1452     unset_tbe();
1453   }
1454
1455   action(t_sendAckWithCollectedTokens, "t", desc="Send ack with the tokens we've collected thus far.") {
1456     assert(is_valid(cache_entry));
1457     if (cache_entry.Tokens > 0) {
1458       peek(requestNetwork_in, RequestMsg) {
1459         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1460           out_msg.Address := address;
1461           if (cache_entry.Tokens > (max_tokens() / 2)) {
1462             out_msg.Type := CoherenceResponseType:DATA_OWNER;
1463           } else {
1464             out_msg.Type := CoherenceResponseType:ACK;
1465           }
1466           out_msg.Sender := machineID;
1467           out_msg.Destination.add(in_msg.Requestor);
1468           assert(cache_entry.Tokens >= 1);
1469           out_msg.Tokens := cache_entry.Tokens;
1470           out_msg.DataBlk := cache_entry.DataBlk;
1471           out_msg.MessageSize := MessageSizeType:Response_Control;
1472         }
1473       }
1474     }
1475     cache_entry.Tokens := 0;
1476   }
1477
1478   action(u_writeDataToCache, "u", desc="Write data to cache") {
1479     peek(responseNetwork_in, ResponseMsg) {
1480       assert(is_valid(cache_entry));
1481       cache_entry.DataBlk := in_msg.DataBlk;
1482       if (cache_entry.Dirty == false && in_msg.Dirty) {
1483         cache_entry.Dirty := in_msg.Dirty;
1484       }
1485
1486     }
1487   }
1488
1489   action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1490     assert(getTokens(cache_entry) == 0);
1491     if (L1DcacheMemory.isTagPresent(address)) {
1492       L1DcacheMemory.deallocate(address);
1493     } else {
1494       L1IcacheMemory.deallocate(address);
1495     }
1496     unset_cache_entry();
1497   }
1498
1499   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1500     if (is_valid(cache_entry)) {
1501     } else {
1502       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
1503     }
1504   }
1505
1506   action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
1507     if (is_valid(cache_entry)) {
1508     } else {
1509       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
1510     }
1511   }
1512
1513   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1514     peek(mandatoryQueue_in, CacheMsg) {
1515       if (L1DcacheMemory.isTagPresent(address)) {
1516         L1DcacheMemory.profileMiss(in_msg);
1517       } else {
1518         L1IcacheMemory.profileMiss(in_msg);
1519       }
1520     }
1521   }
1522
1523   action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
1524     peek(responseNetwork_in, ResponseMsg) {
1525       assert(is_valid(cache_entry));
1526       assert(cache_entry.DataBlk == in_msg.DataBlk);
1527     }
1528   }
1529
1530   action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1531     mandatoryQueue_in.recycle();
1532   }
1533
1534   //*****************************************************
1535   // TRANSITIONS
1536   //*****************************************************
1537
1538   // Transitions for Load/Store/L2_Replacement from transient states
1539   transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
1540     zz_recycleMandatoryQueue;
1541   }
1542
1543   transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
1544     zz_recycleMandatoryQueue;
1545   }
1546
1547   transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
1548     zz_recycleMandatoryQueue;
1549   }
1550
1551
1552   // Lockdowns
1553   transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
1554     l_popPersistentQueue;
1555   }
1556
1557   // Transitions from NP
1558   transition(NP, Load, IS) {
1559     ii_allocateL1DCacheBlock;
1560     i_allocateTBE;
1561     a_issueReadRequest;
1562     uu_profileMiss;
1563     k_popMandatoryQueue;
1564   }
1565
1566   transition(NP, Ifetch, IS) {
1567     pp_allocateL1ICacheBlock;
1568     i_allocateTBE;
1569     a_issueReadRequest;
1570     uu_profileMiss;
1571     k_popMandatoryQueue;
1572   }
1573
1574   transition(NP, {Store, Atomic}, IM) {
1575     ii_allocateL1DCacheBlock;
1576     i_allocateTBE;
1577     b_issueWriteRequest;
1578     uu_profileMiss;
1579     k_popMandatoryQueue;
1580   }
1581
1582   transition(NP, {Ack, Data_Shared, Data_Owner, Data_All_Tokens}) {
1583     bb_bounceResponse;
1584     n_popResponseQueue;
1585   }
1586
1587   transition(NP, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) {
1588     m_popRequestQueue;
1589   }
1590
1591   transition(NP, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1592     l_popPersistentQueue;
1593   }
1594
1595   // Transitions from Idle
1596   transition(I, Load, IS) {
1597     i_allocateTBE;
1598     a_issueReadRequest;
1599     uu_profileMiss;
1600     k_popMandatoryQueue;
1601   }
1602
1603   transition(I, Ifetch, IS) {
1604     i_allocateTBE;
1605     a_issueReadRequest;
1606     uu_profileMiss;
1607     k_popMandatoryQueue;
1608   }
1609
1610   transition(I, {Store, Atomic}, IM) {
1611     i_allocateTBE;
1612     b_issueWriteRequest;
1613     uu_profileMiss;
1614     k_popMandatoryQueue;
1615   }
1616
1617   transition(I, L1_Replacement) {
1618     tr_tokenReplacement;
1619     gg_deallocateL1CacheBlock;
1620   }
1621
1622   transition(I, {Transient_GETX, Transient_Local_GETX}) {
1623     t_sendAckWithCollectedTokens;
1624     m_popRequestQueue;
1625   }
1626
1627   transition(I, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1628     m_popRequestQueue;
1629   }
1630
1631   transition(I, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1632     e_sendAckWithCollectedTokens;
1633     l_popPersistentQueue;
1634   }
1635
1636   transition(I_L, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}) {
1637     l_popPersistentQueue;
1638   }
1639
1640   transition(I, Ack) {
1641     q_updateTokensFromResponse;
1642     n_popResponseQueue;
1643   }
1644
1645   transition(I, Data_Shared, S) {
1646     u_writeDataToCache;
1647     q_updateTokensFromResponse;
1648     n_popResponseQueue;
1649   }
1650
1651   transition(I, Data_Owner, O) {
1652     u_writeDataToCache;
1653     q_updateTokensFromResponse;
1654     n_popResponseQueue;
1655   }
1656
1657   transition(I, Data_All_Tokens, M) {
1658     u_writeDataToCache;
1659     q_updateTokensFromResponse;
1660     n_popResponseQueue;
1661   }
1662
1663   // Transitions from Shared
1664   transition({S, SM, S_L, SM_L}, {Load, Ifetch}) {
1665     h_load_hit;
1666     k_popMandatoryQueue;
1667   }
1668
1669   transition(S, {Store, Atomic}, SM) {
1670     i_allocateTBE;
1671     b_issueWriteRequest;
1672     uu_profileMiss;
1673     k_popMandatoryQueue;
1674   }
1675
1676   transition(S, L1_Replacement, I) {
1677     cc_sharedReplacement; // Only needed in some cases
1678     gg_deallocateL1CacheBlock;
1679   }
1680
1681   transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
1682     t_sendAckWithCollectedTokens;
1683     p_informL2AboutTokenLoss;
1684     m_popRequestQueue;
1685   }
1686
1687   // only owner responds to non-local requests
1688   transition(S, Transient_GETS) {
1689     m_popRequestQueue;
1690   }
1691
1692   transition(S, Transient_Local_GETS) {
1693     d_sendDataWithToken;
1694     m_popRequestQueue;
1695   }
1696
1697   transition(S, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1698     m_popRequestQueue;
1699   }
1700
1701   transition({S, S_L}, Persistent_GETX, I_L) {
1702     e_sendAckWithCollectedTokens;
1703     p_informL2AboutTokenLoss;
1704     l_popPersistentQueue;
1705   }
1706
1707   transition(S, {Persistent_GETS, Persistent_GETS_Last_Token}, S_L) {
1708     f_sendAckWithAllButNorOneTokens;
1709     l_popPersistentQueue;
1710   }
1711
1712   transition(S_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1713     l_popPersistentQueue;
1714   }
1715
1716   transition(S, Ack) {
1717     q_updateTokensFromResponse;
1718     n_popResponseQueue;
1719   }
1720
1721   transition(S, Data_Shared) {
1722     w_assertIncomingDataAndCacheDataMatch;
1723     q_updateTokensFromResponse;
1724     n_popResponseQueue;
1725   }
1726
1727   transition(S, Data_Owner, O) {
1728     w_assertIncomingDataAndCacheDataMatch;
1729     q_updateTokensFromResponse;
1730     n_popResponseQueue;
1731   }
1732
1733   transition(S, Data_All_Tokens, M) {
1734     w_assertIncomingDataAndCacheDataMatch;
1735     q_updateTokensFromResponse;
1736     n_popResponseQueue;
1737   }
1738
1739   // Transitions from Owned
1740   transition({O, OM}, {Load, Ifetch}) {
1741     h_load_hit;
1742     k_popMandatoryQueue;
1743   }
1744
1745   transition(O, {Store, Atomic}, OM) {
1746     i_allocateTBE;
1747     b_issueWriteRequest;
1748     uu_profileMiss;
1749     k_popMandatoryQueue;
1750   }
1751
1752   transition(O, L1_Replacement, I) {
1753     c_ownedReplacement;
1754     gg_deallocateL1CacheBlock;
1755   }
1756
1757   transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
1758     dd_sendDataWithAllTokens;
1759     p_informL2AboutTokenLoss;
1760     m_popRequestQueue;
1761   }
1762
1763   transition(O, Persistent_GETX, I_L) {
1764     ee_sendDataWithAllTokens;
1765     p_informL2AboutTokenLoss;
1766     l_popPersistentQueue;
1767   }
1768
1769   transition(O, Persistent_GETS, S_L) {
1770     ff_sendDataWithAllButNorOneTokens;
1771     l_popPersistentQueue;
1772   }
1773
1774   transition(O, Persistent_GETS_Last_Token, I_L) {
1775     fo_sendDataWithOwnerToken;
1776     l_popPersistentQueue;
1777   }
1778
1779   transition(O, Transient_GETS) {
1780     d_sendDataWithToken;
1781     m_popRequestQueue;
1782   }
1783
1784   transition(O, Transient_Local_GETS) {
1785     d_sendDataWithToken;
1786     m_popRequestQueue;
1787   }
1788
1789   // ran out of tokens, wait for it to go persistent
1790   transition(O, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1791     m_popRequestQueue;
1792   }
1793
1794   transition(O, Ack) {
1795     q_updateTokensFromResponse;
1796     n_popResponseQueue;
1797   }
1798
1799   transition(O, Ack_All_Tokens, M) {
1800     q_updateTokensFromResponse;
1801     n_popResponseQueue;
1802   }
1803
1804   transition(O, Data_Shared) {
1805     w_assertIncomingDataAndCacheDataMatch;
1806     q_updateTokensFromResponse;
1807     n_popResponseQueue;
1808   }
1809
1810   transition(O, Data_All_Tokens, M) {
1811     w_assertIncomingDataAndCacheDataMatch;
1812     q_updateTokensFromResponse;
1813     n_popResponseQueue;
1814   }
1815
1816   // Transitions from Modified
1817   transition({MM, MM_W}, {Load, Ifetch}) {
1818     h_load_hit;
1819     k_popMandatoryQueue;
1820   }
1821
1822   transition({MM_W}, {Store, Atomic}) {
1823     hh_store_hit;
1824     k_popMandatoryQueue;
1825   }
1826
1827   transition(MM, Store) {
1828     hh_store_hit;
1829     k_popMandatoryQueue;
1830   }
1831
1832   transition(MM, Atomic, M) {
1833     hh_store_hit;
1834     k_popMandatoryQueue;
1835   }
1836
1837   transition(MM, L1_Replacement, I) {
1838     c_ownedReplacement;
1839     gg_deallocateL1CacheBlock;
1840   }
1841
1842   transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
1843     dd_sendDataWithAllTokens;
1844     p_informL2AboutTokenLoss;
1845     m_popRequestQueue;
1846   }
1847
1848   transition({MM_W}, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1849     m_popRequestQueue;
1850   }
1851
1852   // Implement the migratory sharing optimization, even for persistent requests
1853   transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
1854     ee_sendDataWithAllTokens;
1855     p_informL2AboutTokenLoss;
1856     l_popPersistentQueue;
1857   }
1858
1859   // ignore persistent requests in lockout period
1860   transition(MM_W, {Persistent_GETX, Persistent_GETS}) {
1861     l_popPersistentQueue;
1862   }
1863
1864   transition(MM_W, Use_TimeoutNoStarvers, MM) {
1865     s_deallocateTBE;
1866     jj_unsetUseTimer;
1867   }
1868
1869   transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
1870     s_deallocateTBE;
1871     jj_unsetUseTimer;
1872   }
1873
1874   // Transitions from Dirty Exclusive
1875   transition({M, M_W}, {Load, Ifetch}) {
1876     h_load_hit;
1877     k_popMandatoryQueue;
1878   }
1879
1880   transition(M, Store, MM) {
1881     hh_store_hit;
1882     k_popMandatoryQueue;
1883   }
1884
1885   transition(M, Atomic) {
1886     hh_store_hit;
1887     k_popMandatoryQueue;
1888   }
1889
1890   transition(M_W, Store, MM_W) {
1891     hh_store_hit;
1892     k_popMandatoryQueue;
1893   }
1894
1895   transition(M_W, Atomic) {
1896     hh_store_hit;
1897     k_popMandatoryQueue;
1898   }
1899
1900   transition(M, L1_Replacement, I) {
1901     c_ownedReplacement;
1902     gg_deallocateL1CacheBlock;
1903   }
1904
1905   transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
1906     dd_sendDataWithAllTokens;
1907     p_informL2AboutTokenLoss;
1908     m_popRequestQueue;
1909   }
1910
1911   transition(M, Transient_Local_GETS, O) {
1912     d_sendDataWithToken;
1913     m_popRequestQueue;
1914   }
1915
1916   transition(M, Transient_GETS, O) {
1917     d_sendDataWithNTokenIfAvail;
1918     m_popRequestQueue;
1919   }
1920
1921   transition(M_W, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1922     m_popRequestQueue;
1923   }
1924
1925   transition(M, Persistent_GETX, I_L) {
1926     ee_sendDataWithAllTokens;
1927     p_informL2AboutTokenLoss;
1928     l_popPersistentQueue;
1929   }
1930
1931   transition(M, Persistent_GETS, S_L) {
1932     ff_sendDataWithAllButNorOneTokens;
1933     l_popPersistentQueue;
1934   }
1935
1936   // ignore persistent requests in lockout period
1937   transition(M_W, {Persistent_GETX, Persistent_GETS}) {
1938     l_popPersistentQueue;
1939   }
1940
1941   transition(M_W, Use_TimeoutStarverS, S_L) {
1942     s_deallocateTBE;
1943     ff_sendDataWithAllButNorOneTokens;
1944     jj_unsetUseTimer;
1945   }
1946
1947   // someone unlocked during timeout
1948   transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
1949     s_deallocateTBE;
1950     jj_unsetUseTimer;
1951   }
1952
1953   transition(M_W, Use_TimeoutStarverX, I_L) {
1954     s_deallocateTBE;
1955     ee_sendDataWithAllTokens;
1956     p_informL2AboutTokenLoss;
1957     jj_unsetUseTimer;
1958   }
1959
1960
1961
1962   // migratory
1963   transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
1964     s_deallocateTBE;
1965     ee_sendDataWithAllTokens;
1966     p_informL2AboutTokenLoss;
1967     jj_unsetUseTimer;
1968
1969   }
1970
1971
1972   // Transient_GETX and Transient_GETS in transient states
1973   transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1974     m_popRequestQueue;  // Even if we have the data, we can pretend we don't have it yet.
1975   }
1976
1977   transition(IS, {Transient_GETX, Transient_Local_GETX}) {
1978     t_sendAckWithCollectedTokens;
1979     m_popRequestQueue;
1980   }
1981
1982   transition(IS, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1983     m_popRequestQueue;
1984   }
1985
1986   transition(IS, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IS_L) {
1987     e_sendAckWithCollectedTokens;
1988     l_popPersistentQueue;
1989   }
1990
1991   transition(IS_L, {Persistent_GETX, Persistent_GETS}) {
1992     l_popPersistentQueue;
1993   }
1994
1995   transition(IM, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IM_L) {
1996     e_sendAckWithCollectedTokens;
1997     l_popPersistentQueue;
1998   }
1999
2000   transition(IM_L, {Persistent_GETX, Persistent_GETS}) {
2001     l_popPersistentQueue;
2002   }
2003
2004   transition({SM, SM_L}, Persistent_GETX, IM_L) {
2005     e_sendAckWithCollectedTokens;
2006     l_popPersistentQueue;
2007   }
2008
2009   transition(SM, {Persistent_GETS, Persistent_GETS_Last_Token}, SM_L) {
2010     f_sendAckWithAllButNorOneTokens;
2011     l_popPersistentQueue;
2012   }
2013
2014   transition(SM_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
2015     l_popPersistentQueue;
2016   }
2017
2018   transition(OM, Persistent_GETX, IM_L) {
2019     ee_sendDataWithAllTokens;
2020     l_popPersistentQueue;
2021   }
2022
2023   transition(OM, Persistent_GETS, SM_L) {
2024     ff_sendDataWithAllButNorOneTokens;
2025     l_popPersistentQueue;
2026   }
2027
2028   transition(OM, Persistent_GETS_Last_Token, IM_L) {
2029     fo_sendDataWithOwnerToken;
2030     l_popPersistentQueue;
2031   }
2032
2033   // Transitions from IM/SM
2034
2035   transition({IM, SM}, Ack) {
2036     q_updateTokensFromResponse;
2037     n_popResponseQueue;
2038   }
2039
2040   transition(IM, Data_Shared, SM) {
2041     u_writeDataToCache;
2042     q_updateTokensFromResponse;
2043     n_popResponseQueue;
2044   }
2045
2046   transition(IM, Data_Owner, OM) {
2047     u_writeDataToCache;
2048     q_updateTokensFromResponse;
2049     n_popResponseQueue;
2050   }
2051
2052   transition(IM, Data_All_Tokens, MM_W) {
2053     u_writeDataToCache;
2054     q_updateTokensFromResponse;
2055     xx_external_store_hit;
2056     o_scheduleUseTimeout;
2057     j_unsetReissueTimer;
2058     n_popResponseQueue;
2059   }
2060
2061   transition(SM, Data_Shared) {
2062     w_assertIncomingDataAndCacheDataMatch;
2063     q_updateTokensFromResponse;
2064     n_popResponseQueue;
2065   }
2066
2067   transition(SM, Data_Owner, OM) {
2068     w_assertIncomingDataAndCacheDataMatch;
2069     q_updateTokensFromResponse;
2070     n_popResponseQueue;
2071   }
2072
2073   transition(SM, Data_All_Tokens, MM_W) {
2074     w_assertIncomingDataAndCacheDataMatch;
2075     q_updateTokensFromResponse;
2076     xx_external_store_hit;
2077     o_scheduleUseTimeout;
2078     j_unsetReissueTimer;
2079     n_popResponseQueue;
2080   }
2081
2082   transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens.  We give them up here to avoid livelock
2083     t_sendAckWithCollectedTokens;
2084     m_popRequestQueue;
2085   }
2086
2087   transition({IM, SM}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2088     m_popRequestQueue;
2089   }
2090
2091   transition({IM, SM}, Request_Timeout) {
2092     j_unsetReissueTimer;
2093     b_issueWriteRequest;
2094   }
2095
2096   // Transitions from OM
2097
2098   transition(OM, Ack) {
2099     q_updateTokensFromResponse;
2100     n_popResponseQueue;
2101   }
2102
2103   transition(OM, Ack_All_Tokens, MM_W) {
2104     q_updateTokensFromResponse;
2105     xx_external_store_hit;
2106     o_scheduleUseTimeout;
2107     j_unsetReissueTimer;
2108     n_popResponseQueue;
2109   }
2110
2111   transition(OM, Data_Shared) {
2112     w_assertIncomingDataAndCacheDataMatch;
2113     q_updateTokensFromResponse;
2114     n_popResponseQueue;
2115   }
2116
2117   transition(OM, Data_All_Tokens, MM_W) {
2118     w_assertIncomingDataAndCacheDataMatch;
2119     q_updateTokensFromResponse;
2120     xx_external_store_hit;
2121     o_scheduleUseTimeout;
2122     j_unsetReissueTimer;
2123     n_popResponseQueue;
2124   }
2125
2126   transition(OM, Request_Timeout) {
2127     j_unsetReissueTimer;
2128     b_issueWriteRequest;
2129   }
2130
2131   // Transitions from IS
2132
2133   transition(IS, Ack) {
2134     q_updateTokensFromResponse;
2135     n_popResponseQueue;
2136   }
2137
2138   transition(IS, Data_Shared, S) {
2139     u_writeDataToCache;
2140     q_updateTokensFromResponse;
2141     x_external_load_hit;
2142     s_deallocateTBE;
2143     j_unsetReissueTimer;
2144     n_popResponseQueue;
2145   }
2146
2147   transition(IS, Data_Owner, O) {
2148     u_writeDataToCache;
2149     q_updateTokensFromResponse;
2150     x_external_load_hit;
2151     s_deallocateTBE;
2152     j_unsetReissueTimer;
2153     n_popResponseQueue;
2154   }
2155
2156   transition(IS, Data_All_Tokens, M_W) {
2157     u_writeDataToCache;
2158     q_updateTokensFromResponse;
2159     x_external_load_hit;
2160     o_scheduleUseTimeout;
2161     j_unsetReissueTimer;
2162     n_popResponseQueue;
2163   }
2164
2165   transition(IS, Request_Timeout) {
2166     j_unsetReissueTimer;
2167     a_issueReadRequest;
2168   }
2169
2170   // Transitions from I_L
2171
2172   transition(I_L, Load, IS_L) {
2173     ii_allocateL1DCacheBlock;
2174     i_allocateTBE;
2175     a_issueReadRequest;
2176     uu_profileMiss;
2177     k_popMandatoryQueue;
2178   }
2179
2180   transition(I_L, Ifetch, IS_L) {
2181     pp_allocateL1ICacheBlock;
2182     i_allocateTBE;
2183     a_issueReadRequest;
2184     uu_profileMiss;
2185     k_popMandatoryQueue;
2186   }
2187
2188   transition(I_L, {Store, Atomic}, IM_L) {
2189     ii_allocateL1DCacheBlock;
2190     i_allocateTBE;
2191     b_issueWriteRequest;
2192     uu_profileMiss;
2193     k_popMandatoryQueue;
2194   }
2195
2196
2197   // Transitions from S_L
2198
2199   transition(S_L, {Store, Atomic}, SM_L) {
2200     i_allocateTBE;
2201     b_issueWriteRequest;
2202     uu_profileMiss;
2203     k_popMandatoryQueue;
2204   }
2205
2206   // Other transitions from *_L states
2207
2208   transition({I_L, IM_L, IS_L, S_L, SM_L}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS, Transient_GETX, Transient_Local_GETX}) {
2209     m_popRequestQueue;
2210   }
2211
2212   transition({I_L, IM_L, IS_L, S_L, SM_L}, Ack) {
2213     g_bounceResponseToStarver;
2214     n_popResponseQueue;
2215   }
2216
2217   transition({I_L, IM_L, S_L, SM_L}, {Data_Shared, Data_Owner}) {
2218     g_bounceResponseToStarver;
2219     n_popResponseQueue;
2220   }
2221
2222   transition({I_L, S_L}, Data_All_Tokens) {
2223     g_bounceResponseToStarver;
2224     n_popResponseQueue;
2225   }
2226
2227   transition(IS_L, Request_Timeout) {
2228     j_unsetReissueTimer;
2229     a_issueReadRequest;
2230   }
2231
2232   transition({IM_L, SM_L}, Request_Timeout) {
2233     j_unsetReissueTimer;
2234     b_issueWriteRequest;
2235   }
2236
2237   // Opportunisticly Complete the memory operation in the following
2238   // cases.  Note: these transitions could just use
2239   // g_bounceResponseToStarver, but if we have the data and tokens, we
2240   // might as well complete the memory request while we have the
2241   // chance (and then immediately forward on the data)
2242
2243   transition(IM_L, Data_All_Tokens, MM_W) {
2244     u_writeDataToCache;
2245     q_updateTokensFromResponse;
2246     xx_external_store_hit;
2247     j_unsetReissueTimer;
2248     o_scheduleUseTimeout;
2249     n_popResponseQueue;
2250   }
2251
2252   transition(SM_L, Data_All_Tokens, S_L) {
2253     u_writeDataToCache;
2254     q_updateTokensFromResponse;
2255     xx_external_store_hit;
2256     ff_sendDataWithAllButNorOneTokens;
2257     s_deallocateTBE;
2258     j_unsetReissueTimer;
2259     n_popResponseQueue;
2260   }
2261
2262   transition(IS_L, Data_Shared, I_L) {
2263     u_writeDataToCache;
2264     q_updateTokensFromResponse;
2265     x_external_load_hit;
2266     s_deallocateTBE;
2267     e_sendAckWithCollectedTokens;
2268     p_informL2AboutTokenLoss;
2269     j_unsetReissueTimer;
2270     n_popResponseQueue;
2271   }
2272
2273   transition(IS_L, Data_Owner, I_L) {
2274     u_writeDataToCache;
2275     q_updateTokensFromResponse;
2276     x_external_load_hit;
2277     ee_sendDataWithAllTokens;
2278     s_deallocateTBE;
2279     p_informL2AboutTokenLoss;
2280     j_unsetReissueTimer;
2281     n_popResponseQueue;
2282   }
2283
2284   transition(IS_L, Data_All_Tokens, M_W) {
2285     u_writeDataToCache;
2286     q_updateTokensFromResponse;
2287     x_external_load_hit;
2288     j_unsetReissueTimer;
2289     o_scheduleUseTimeout;
2290     n_popResponseQueue;
2291   }
2292
2293
2294   // Own_Lock_or_Unlock
2295
2296   transition(I_L, Own_Lock_or_Unlock, I) {
2297     l_popPersistentQueue;
2298   }
2299
2300   transition(S_L, Own_Lock_or_Unlock, S) {
2301     l_popPersistentQueue;
2302   }
2303
2304   transition(IM_L, Own_Lock_or_Unlock, IM) {
2305     l_popPersistentQueue;
2306   }
2307
2308   transition(IS_L, Own_Lock_or_Unlock, IS) {
2309     l_popPersistentQueue;
2310   }
2311
2312   transition(SM_L, Own_Lock_or_Unlock, SM) {
2313     l_popPersistentQueue;
2314   }
2315 }
2316