src/mem/protocol/MOESI_CMP_token-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id: MOESI_CMP_token-L1cache.sm 1.22 05/01/19 15:55:39-06:00 beckmann@s0-28.cs.wisc.edu $
  32  *
  33  */
  34
  35 machine(L1Cache, "Token protocol")
  36  : Sequencer * sequencer,
  37    CacheMemory * L1IcacheMemory,
  38    CacheMemory * L1DcacheMemory,
  39    int l2_select_num_bits,
  40    int N_tokens,
  41    int l1_request_latency = 2,
  42    int l1_response_latency = 2,
  43    int retry_threshold = 1,
  44    int fixed_timeout_latency = 100,
  45    bool dynamic_timeout_enabled = true,
  46    bool no_mig_atomic = true,
  47    bool send_evictions
  48 {
  49
  50   // From this node's L1 cache TO the network
  51
  52   // a local L1 -> this L2 bank
  53   MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false", vnet_type="response";
  54   MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true", vnet_type="persistent";
  55   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  56   MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="request";
  57
  58
  59   // To this node's L1 cache FROM the network
  60   // a L2 bank -> this L1
  61   MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false", vnet_type="response";
  62   MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true", vnet_type="persistent";
  63   // a L2 bank -> this L1
  64   MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="request";
  65
  66   // STATES
  67   state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
  68     // Base states
  69     NP, AccessPermission:Invalid, "NP", desc="Not Present";
  70     I, AccessPermission:Invalid, "I", desc="Idle";
  71     S, AccessPermission:Read_Only, "S", desc="Shared";
  72     O, AccessPermission:Read_Only, "O", desc="Owned";
  73     M, AccessPermission:Read_Only, "M", desc="Modified (dirty)";
  74     MM, AccessPermission:Read_Write, "MM", desc="Modified (dirty and locally modified)";
  75     M_W, AccessPermission:Read_Only, "M^W", desc="Modified (dirty), waiting";
  76     MM_W, AccessPermission:Read_Write, "MM^W", desc="Modified (dirty and locally modified), waiting";
  77
  78     // Transient States
  79     IM, AccessPermission:Busy, "IM", desc="Issued GetX";
  80     SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have an old copy of the line";
  81     OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
  82     IS, AccessPermission:Busy, "IS", desc="Issued GetS";
  83
  84     // Locked states
  85     I_L, AccessPermission:Busy, "I^L", desc="Invalid, Locked";
  86     S_L, AccessPermission:Busy, "S^L", desc="Shared, Locked";
  87     IM_L, AccessPermission:Busy, "IM^L", desc="Invalid, Locked, trying to go to Modified";
  88     SM_L, AccessPermission:Busy, "SM^L", desc="Shared, Locked, trying to go to Modified";
  89     IS_L, AccessPermission:Busy, "IS^L", desc="Invalid, Locked, trying to go to Shared";
  90   }
  91
  92   // EVENTS
  93   enumeration(Event, desc="Cache events") {
  94     Load,            desc="Load request from the processor";
  95     Ifetch,          desc="I-fetch request from the processor";
  96     Store,           desc="Store request from the processor";
  97     Atomic,          desc="Atomic request from the processor";
  98     L1_Replacement,  desc="L1 Replacement";
  99
 100     // Responses
 101     Data_Shared,             desc="Received a data message, we are now a sharer";
 102     Data_Owner,              desc="Received a data message, we are now the owner";
 103     Data_All_Tokens,   desc="Received a data message, we are now the owner, we now have all the tokens";
 104     Ack,                     desc="Received an ack message";
 105     Ack_All_Tokens,          desc="Received an ack message, we now have all the tokens";
 106
 107     // Requests
 108     Transient_GETX,  desc="A GetX from another processor";
 109     Transient_Local_GETX,  desc="A GetX from another processor";
 110     Transient_GETS,  desc="A GetS from another processor";
 111     Transient_Local_GETS,  desc="A GetS from another processor";
 112     Transient_GETS_Last_Token,  desc="A GetS from another processor";
 113     Transient_Local_GETS_Last_Token,  desc="A GetS from another processor";
 114
 115     // Lock/Unlock for distributed
 116     Persistent_GETX,     desc="Another processor has priority to read/write";
 117     Persistent_GETS,     desc="Another processor has priority to read";
 118     Persistent_GETS_Last_Token, desc="Another processor has priority to read, no more tokens";
 119     Own_Lock_or_Unlock,  desc="This processor now has priority";
 120
 121     // Triggers
 122     Request_Timeout,         desc="Timeout";
 123     Use_TimeoutStarverX,             desc="Timeout";
 124     Use_TimeoutStarverS,             desc="Timeout";
 125     Use_TimeoutNoStarvers,             desc="Timeout";
 126     Use_TimeoutNoStarvers_NoMig,     desc="Timeout Don't Migrate";
 127   }
 128
 129   // TYPES
 130
 131   // CacheEntry
 132   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 133     State CacheState,        desc="cache state";
 134     bool Dirty,              desc="Is the data dirty (different than memory)?";
 135     int Tokens,              desc="The number of tokens we're holding for the line";
 136     DataBlock DataBlk,       desc="data for the block";
 137   }
 138
 139
 140   // TBE fields
 141   structure(TBE, desc="...") {
 142     Address address,                      desc="Physical address for this TBE";
 143     State TBEState,                       desc="Transient state";
 144     int IssueCount,      default="0",     desc="The number of times we've issued a request for this line.";
 145     Address PC,                           desc="Program counter of request";
 146
 147     bool WentPersistent, default="false",  desc="Request went persistent";
 148     bool ExternalResponse, default="false", desc="Response came from an external controller";
 149     bool IsAtomic, default="false",       desc="Request was an atomic request";
 150
 151     AccessType AccessType,                desc="Type of request (used for profiling)";
 152     Time IssueTime,                       desc="Time the request was issued";
 153     RubyAccessMode AccessMode,    desc="user/supervisor access type";
 154     PrefetchBit Prefetch,         desc="Is this a prefetch request";
 155   }
 156
 157   structure(TBETable, external="yes") {
 158     TBE lookup(Address);
 159     void allocate(Address);
 160     void deallocate(Address);
 161     bool isPresent(Address);
 162   }
 163
 164   structure(PersistentTable, external="yes") {
 165     void persistentRequestLock(Address, MachineID, AccessType);
 166     void persistentRequestUnlock(Address, MachineID);
 167     bool okToIssueStarving(Address, MachineID);
 168     MachineID findSmallest(Address);
 169     AccessType typeOfSmallest(Address);
 170     void markEntries(Address);
 171     bool isLocked(Address);
 172     int countStarvingForAddress(Address);
 173     int countReadStarvingForAddress(Address);
 174   }
 175
 176   void set_cache_entry(AbstractCacheEntry b);
 177   void unset_cache_entry();
 178   void set_tbe(TBE b);
 179   void unset_tbe();
 180   void wakeUpAllBuffers();
 181   void wakeUpBuffers(Address a);
 182
 183   TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 184
 185   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 186
 187   bool starving, default="false";
 188   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 189
 190   PersistentTable persistentTable;
 191   TimerTable useTimerTable;
 192   TimerTable reissueTimerTable;
 193
 194   int outstandingRequests, default="0";
 195   int outstandingPersistentRequests, default="0";
 196
 197   int averageLatencyHysteresis, default="(8)"; // Constant that provides hysteresis for calculated the estimated average
 198   int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))";
 199
 200   int averageLatencyEstimate() {
 201     DPRINTF(RubySlicc, "%d\n",
 202             (averageLatencyCounter >> averageLatencyHysteresis));
 203     //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
 204     return averageLatencyCounter >> averageLatencyHysteresis;
 205   }
 206
 207   void updateAverageLatencyEstimate(int latency) {
 208     DPRINTF(RubySlicc, "%d\n", latency);
 209     assert(latency >= 0);
 210
 211     // By subtracting the current average and then adding the most
 212     // recent sample, we calculate an estimate of the recent average.
 213     // If we simply used a running sum and divided by the total number
 214     // of entries, the estimate of the average would adapt very slowly
 215     // after the execution has run for a long time.
 216     // averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
 217
 218     averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
 219   }
 220
 221   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 222     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 223     if(is_valid(L1Dcache_entry)) {
 224       return L1Dcache_entry;
 225     }
 226
 227     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 228     return L1Icache_entry;
 229   }
 230
 231   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 232     return getCacheEntry(addr).DataBlk;
 233   }
 234
 235   Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
 236     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 237     return L1Dcache_entry;
 238   }
 239
 240   Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
 241     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 242     return L1Icache_entry;
 243   }
 244
 245   int getTokens(Entry cache_entry) {
 246     if (is_valid(cache_entry)) {
 247       return cache_entry.Tokens;
 248     }
 249     return 0;
 250   }
 251
 252   State getState(TBE tbe, Entry cache_entry, Address addr) {
 253
 254     if (is_valid(tbe)) {
 255       return tbe.TBEState;
 256     } else if (is_valid(cache_entry)) {
 257       return cache_entry.CacheState;
 258     } else {
 259       if ((persistentTable.isLocked(addr) == true) && (persistentTable.findSmallest(addr) != machineID)) {
 260       // Not in cache, in persistent table, but this processor isn't highest priority
 261       return State:I_L;
 262       } else {
 263         return State:NP;
 264       }
 265     }
 266   }
 267
 268   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 269     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 270
 271     if (is_valid(tbe)) {
 272       assert(state != State:I);
 273       assert(state != State:S);
 274       assert(state != State:O);
 275       assert(state != State:MM);
 276       assert(state != State:M);
 277       tbe.TBEState := state;
 278     }
 279
 280     if (is_valid(cache_entry)) {
 281       // Make sure the token count is in range
 282       assert(cache_entry.Tokens >= 0);
 283       assert(cache_entry.Tokens <= max_tokens());
 284       assert(cache_entry.Tokens != (max_tokens() / 2));
 285
 286       if ((state == State:I_L) ||
 287           (state == State:IM_L) ||
 288           (state == State:IS_L)) {
 289         // Make sure we have no tokens in the "Invalid, locked" states
 290           assert(cache_entry.Tokens == 0);
 291
 292         // Make sure the line is locked
 293         // assert(persistentTable.isLocked(addr));
 294
 295         // But we shouldn't have highest priority for it
 296         // assert(persistentTable.findSmallest(addr) != id);
 297
 298       } else if ((state == State:S_L) ||
 299                  (state == State:SM_L)) {
 300         assert(cache_entry.Tokens >= 1);
 301         assert(cache_entry.Tokens < (max_tokens() / 2));
 302
 303         // Make sure the line is locked...
 304         // assert(persistentTable.isLocked(addr));
 305
 306         // ...But we shouldn't have highest priority for it...
 307         // assert(persistentTable.findSmallest(addr) != id);
 308
 309         // ...And it must be a GETS request
 310         // assert(persistentTable.typeOfSmallest(addr) == AccessType:Read);
 311
 312       } else {
 313
 314         // If there is an entry in the persistent table of this block,
 315         // this processor needs to have an entry in the table for this
 316         // block, and that entry better be the smallest (highest
 317         // priority).  Otherwise, the state should have been one of
 318         // locked states
 319
 320         //if (persistentTable.isLocked(addr)) {
 321         //  assert(persistentTable.findSmallest(addr) == id);
 322         //}
 323       }
 324
 325       // in M and E you have all the tokens
 326       if (state == State:MM || state == State:M || state == State:MM_W || state == State:M_W) {
 327         assert(cache_entry.Tokens == max_tokens());
 328       }
 329
 330       // in NP you have no tokens
 331       if (state == State:NP) {
 332         assert(cache_entry.Tokens == 0);
 333       }
 334
 335       // You have at least one token in S-like states
 336       if (state == State:S || state == State:SM) {
 337         assert(cache_entry.Tokens > 0);
 338       }
 339
 340       // You have at least half the token in O-like states
 341       if (state == State:O && state == State:OM) {
 342         assert(cache_entry.Tokens > (max_tokens() / 2));
 343       }
 344
 345       cache_entry.CacheState := state;
 346     }
 347   }
 348
 349   AccessPermission getAccessPermission(Address addr) {
 350     TBE tbe := L1_TBEs[addr];
 351     if(is_valid(tbe)) {
 352       return L1Cache_State_to_permission(tbe.TBEState);
 353     }
 354
 355     Entry cache_entry := getCacheEntry(addr);
 356     if(is_valid(cache_entry)) {
 357       return L1Cache_State_to_permission(cache_entry.CacheState);
 358     }
 359
 360     return AccessPermission:NotPresent;
 361   }
 362
 363   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 364     if (is_valid(cache_entry)) {
 365       cache_entry.changePermission(L1Cache_State_to_permission(state));
 366     }
 367   }
 368
 369   Event mandatory_request_type_to_event(RubyRequestType type) {
 370     if (type == RubyRequestType:LD) {
 371       return Event:Load;
 372     } else if (type == RubyRequestType:IFETCH) {
 373       return Event:Ifetch;
 374     } else if (type == RubyRequestType:ST) {
 375       return Event:Store;
 376     } else if (type == RubyRequestType:ATOMIC) {
 377       if (no_mig_atomic) {
 378         return Event:Atomic;
 379       } else {
 380         return Event:Store;
 381       }
 382     } else {
 383       error("Invalid RubyRequestType");
 384     }
 385   }
 386
 387   AccessType cache_request_type_to_access_type(RubyRequestType type) {
 388     if ((type == RubyRequestType:LD) || (type == RubyRequestType:IFETCH)) {
 389       return AccessType:Read;
 390     } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
 391       return AccessType:Write;
 392     } else {
 393       error("Invalid RubyRequestType");
 394     }
 395   }
 396
 397   GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
 398     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
 399       //
 400       // NOTE direct local hits should not call this
 401       //
 402       return GenericMachineType:L1Cache_wCC;
 403     } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
 404
 405       if (sender == (mapAddressToRange(addr,
 406                                        MachineType:L2Cache,
 407                                        l2_select_low_bit,
 408                                        l2_select_num_bits))) {
 409
 410         return GenericMachineType:L2Cache;
 411       } else {
 412         return GenericMachineType:L2Cache_wCC;
 413       }
 414     } else {
 415       return ConvertMachToGenericMach(machineIDToMachineType(sender));
 416     }
 417   }
 418
 419   bool okToIssueStarving(Address addr, MachineID machinID) {
 420     return persistentTable.okToIssueStarving(addr, machineID);
 421   }
 422
 423   void markPersistentEntries(Address addr) {
 424     persistentTable.markEntries(addr);
 425   }
 426
 427   void setExternalResponse(TBE tbe) {
 428     assert(is_valid(tbe));
 429     tbe.ExternalResponse := true;
 430   }
 431
 432   bool IsAtomic(TBE tbe) {
 433     assert(is_valid(tbe));
 434     return tbe.IsAtomic;
 435   }
 436
 437   // ** OUT_PORTS **
 438   out_port(persistentNetwork_out, PersistentMsg, persistentFromL1Cache);
 439   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 440   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 441   out_port(requestRecycle_out, RequestMsg, requestToL1Cache);
 442
 443   // ** IN_PORTS **
 444
 445   // Use Timer
 446   in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
 447     if (useTimerTable_in.isReady()) {
 448       TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
 449
 450       if (persistentTable.isLocked(useTimerTable.readyAddress()) &&
 451           (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
 452         if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
 453           trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress(),
 454                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 455         } else {
 456           trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress(),
 457                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 458         }
 459       } else {
 460         if (no_mig_atomic && IsAtomic(tbe)) {
 461           trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress(),
 462                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 463         } else {
 464           trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress(),
 465                   getCacheEntry(useTimerTable.readyAddress()), tbe);
 466         }
 467       }
 468     }
 469   }
 470
 471   // Reissue Timer
 472   in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
 473     if (reissueTimerTable_in.isReady()) {
 474       trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
 475               getCacheEntry(reissueTimerTable.readyAddress()),
 476               L1_TBEs[reissueTimerTable.readyAddress()]);
 477     }
 478   }
 479
 480   // Persistent Network
 481   in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
 482     if (persistentNetwork_in.isReady()) {
 483       peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
 484         assert(in_msg.Destination.isElement(machineID));
 485
 486         // Apply the lockdown or unlockdown message to the table
 487         if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
 488           persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
 489         } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
 490           persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
 491         } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
 492           persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
 493         } else {
 494           error("Unexpected message");
 495         }
 496
 497         // React to the message based on the current state of the table
 498         Entry cache_entry := getCacheEntry(in_msg.Address);
 499         TBE tbe := L1_TBEs[in_msg.Address];
 500
 501         if (persistentTable.isLocked(in_msg.Address)) {
 502           if (persistentTable.findSmallest(in_msg.Address) == machineID) {
 503             // Our Own Lock - this processor is highest priority
 504             trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 505                     cache_entry, tbe);
 506           } else {
 507             if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
 508               if (getTokens(cache_entry) == 1 ||
 509                   getTokens(cache_entry) == (max_tokens() / 2) + 1) {
 510                 trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
 511                         cache_entry, tbe);
 512               } else {
 513                 trigger(Event:Persistent_GETS, in_msg.Address,
 514                         cache_entry, tbe);
 515               }
 516             } else {
 517               trigger(Event:Persistent_GETX, in_msg.Address,
 518                       cache_entry, tbe);
 519             }
 520           }
 521         } else {
 522           // Unlock case - no entries in the table
 523           trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 524                   cache_entry, tbe);
 525         }
 526       }
 527     }
 528   }
 529
 530   // Response Network
 531   in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
 532     if (responseNetwork_in.isReady()) {
 533       peek(responseNetwork_in, ResponseMsg, block_on="Address") {
 534         assert(in_msg.Destination.isElement(machineID));
 535
 536         Entry cache_entry := getCacheEntry(in_msg.Address);
 537         TBE tbe := L1_TBEs[in_msg.Address];
 538
 539         // Mark TBE flag if response received off-chip.  Use this to update average latency estimate
 540         if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
 541
 542           if (in_msg.Sender == mapAddressToRange(in_msg.Address,
 543                                                  MachineType:L2Cache,
 544                                                  l2_select_low_bit,
 545                                                  l2_select_num_bits)) {
 546
 547             // came from an off-chip L2 cache
 548             if (is_valid(tbe)) {
 549                // L1_TBEs[in_msg.Address].ExternalResponse := true;
 550                // profile_offchipL2_response(in_msg.Address);
 551             }
 552           }
 553           else {
 554                // profile_onchipL2_response(in_msg.Address );
 555           }
 556         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
 557           if (is_valid(tbe)) {
 558             setExternalResponse(tbe);
 559             // profile_memory_response( in_msg.Address);
 560           }
 561         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 562           //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
 563             //if (is_valid(tbe)) {
 564                // tbe.ExternalResponse := true;
 565                // profile_offchipL1_response(in_msg.Address );
 566             //}
 567           //}
 568           //else {
 569                // profile_onchipL1_response(in_msg.Address );
 570           //}
 571         } else {
 572           error("unexpected SenderMachine");
 573         }
 574
 575
 576         if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
 577           if (in_msg.Type == CoherenceResponseType:ACK) {
 578             assert(in_msg.Tokens < (max_tokens() / 2));
 579             trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
 580           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
 581             trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
 582           } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 583             assert(in_msg.Tokens < (max_tokens() / 2));
 584             trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
 585           } else {
 586             error("Unexpected message");
 587           }
 588         } else {
 589           if (in_msg.Type == CoherenceResponseType:ACK) {
 590             assert(in_msg.Tokens < (max_tokens() / 2));
 591             trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
 592           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 593             trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
 594           } else {
 595             error("Unexpected message");
 596           }
 597         }
 598       }
 599     }
 600   }
 601
 602   // Request Network
 603   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 604     if (requestNetwork_in.isReady()) {
 605       peek(requestNetwork_in, RequestMsg, block_on="Address") {
 606         assert(in_msg.Destination.isElement(machineID));
 607
 608         Entry cache_entry := getCacheEntry(in_msg.Address);
 609         TBE tbe := L1_TBEs[in_msg.Address];
 610
 611         if (in_msg.Type == CoherenceRequestType:GETX) {
 612           if (in_msg.isLocal) {
 613             trigger(Event:Transient_Local_GETX, in_msg.Address,
 614                     cache_entry, tbe);
 615           }
 616           else {
 617             trigger(Event:Transient_GETX, in_msg.Address,
 618                     cache_entry, tbe);
 619           }
 620         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 621           if (getTokens(cache_entry) == 1 ||
 622               getTokens(cache_entry) == (max_tokens() / 2) + 1) {
 623             if (in_msg.isLocal) {
 624               trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
 625                       cache_entry, tbe);
 626             }
 627             else {
 628               trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
 629                       cache_entry, tbe);
 630             }
 631           }
 632           else {
 633             if (in_msg.isLocal) {
 634               trigger(Event:Transient_Local_GETS, in_msg.Address,
 635                       cache_entry, tbe);
 636             }
 637             else {
 638               trigger(Event:Transient_GETS, in_msg.Address,
 639                       cache_entry, tbe);
 640             }
 641           }
 642         } else {
 643           error("Unexpected message");
 644         }
 645       }
 646     }
 647   }
 648
 649   // Mandatory Queue
 650   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
 651     if (mandatoryQueue_in.isReady()) {
 652       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 653         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 654
 655         TBE tbe := L1_TBEs[in_msg.LineAddress];
 656
 657         if (in_msg.Type == RubyRequestType:IFETCH) {
 658           // ** INSTRUCTION ACCESS ***
 659
 660           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 661           if (is_valid(L1Icache_entry)) {
 662             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 663             trigger(mandatory_request_type_to_event(in_msg.Type),
 664                     in_msg.LineAddress, L1Icache_entry, tbe);
 665           } else {
 666
 667             // Check to see if it is in the OTHER L1
 668             Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 669             if (is_valid(L1Dcache_entry)) {
 670               // The block is in the wrong L1, try to write it to the L2
 671                 trigger(Event:L1_Replacement, in_msg.LineAddress,
 672                         L1Dcache_entry, tbe);
 673             }
 674
 675             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 676               // L1 does't have the line, but we have space for it in the L1
 677               trigger(mandatory_request_type_to_event(in_msg.Type),
 678                       in_msg.LineAddress, L1Icache_entry, tbe);
 679             } else {
 680               // No room in the L1, so we need to make room
 681               trigger(Event:L1_Replacement,
 682                       L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 683                       getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 684                       L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 685             }
 686           }
 687         } else {
 688           // *** DATA ACCESS ***
 689
 690           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 691           if (is_valid(L1Dcache_entry)) {
 692             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 693             trigger(mandatory_request_type_to_event(in_msg.Type),
 694                     in_msg.LineAddress, L1Dcache_entry, tbe);
 695           } else {
 696
 697             // Check to see if it is in the OTHER L1
 698             Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 699             if (is_valid(L1Icache_entry)) {
 700               // The block is in the wrong L1, try to write it to the L2
 701               trigger(Event:L1_Replacement, in_msg.LineAddress,
 702                       L1Icache_entry, tbe);
 703             }
 704
 705             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 706               // L1 does't have the line, but we have space for it in the L1
 707               trigger(mandatory_request_type_to_event(in_msg.Type),
 708                       in_msg.LineAddress, L1Dcache_entry, tbe);
 709             } else {
 710               // No room in the L1, so we need to make room
 711               trigger(Event:L1_Replacement,
 712                       L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 713                       getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 714                       L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 715             }
 716           }
 717         }
 718       }
 719     }
 720   }
 721
 722   // ACTIONS
 723
 724   action(a_issueReadRequest, "a", desc="Issue GETS") {
 725       assert(is_valid(tbe));
 726       if (tbe.IssueCount == 0) {
 727         // Update outstanding requests
 728         //profile_outstanding_request(outstandingRequests);
 729         outstandingRequests := outstandingRequests + 1;
 730       }
 731
 732       if (tbe.IssueCount >= retry_threshold) {
 733         // Issue a persistent request if possible
 734         if (okToIssueStarving(address, machineID) && (starving == false)) {
 735           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
 736             out_msg.Address := address;
 737             out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
 738             out_msg.Requestor := machineID;
 739             out_msg.Destination.broadcast(MachineType:L1Cache);
 740
 741             //
 742             // Currently the configuration system limits the system to only one
 743             // chip.  Therefore, if we assume one shared L2 cache, then only one
 744             // pertinent L2 cache exist.
 745             //
 746             //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 747
 748             out_msg.Destination.add(mapAddressToRange(address,
 749                                                       MachineType:L2Cache,
 750                                                       l2_select_low_bit,
 751                                                       l2_select_num_bits));
 752
 753             out_msg.Destination.add(map_Address_to_Directory(address));
 754             out_msg.MessageSize := MessageSizeType:Persistent_Control;
 755             out_msg.Prefetch := tbe.Prefetch;
 756             out_msg.AccessMode := tbe.AccessMode;
 757           }
 758           markPersistentEntries(address);
 759           starving := true;
 760
 761           if (tbe.IssueCount == 0) {
 762             //profile_persistent_prediction(address, tbe.AccessType);
 763           }
 764
 765           // Update outstanding requests
 766           //profile_outstanding_persistent_request(outstandingPersistentRequests);
 767           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 768
 769           // Increment IssueCount
 770           tbe.IssueCount := tbe.IssueCount + 1;
 771
 772           tbe.WentPersistent := true;
 773
 774           // Do not schedule a wakeup, a persistent requests will always complete
 775         }
 776         else {
 777
 778           // We'd like to issue a persistent request, but are not allowed
 779           // to issue a P.R. right now.  This, we do not increment the
 780           // IssueCount.
 781
 782           // Set a wakeup timer
 783           reissueTimerTable.set(address, 10);
 784
 785         }
 786       } else {
 787         // Make a normal request
 788         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 789           out_msg.Address := address;
 790           out_msg.Type := CoherenceRequestType:GETS;
 791           out_msg.Requestor := machineID;
 792           out_msg.Destination.add(mapAddressToRange(address,
 793                                                     MachineType:L2Cache,
 794                                                     l2_select_low_bit,
 795                                                     l2_select_num_bits));
 796
 797           out_msg.RetryNum := tbe.IssueCount;
 798           if (tbe.IssueCount == 0) {
 799             out_msg.MessageSize := MessageSizeType:Request_Control;
 800           } else {
 801             out_msg.MessageSize := MessageSizeType:Reissue_Control;
 802           }
 803           out_msg.Prefetch := tbe.Prefetch;
 804           out_msg.AccessMode := tbe.AccessMode;
 805         }
 806
 807         // send to other local L1s, with local bit set
 808         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 809           out_msg.Address := address;
 810           out_msg.Type := CoherenceRequestType:GETS;
 811           out_msg.Requestor := machineID;
 812           //
 813           // Since only one chip, assuming all L1 caches are local
 814           //
 815           //out_msg.Destination := getOtherLocalL1IDs(machineID);
 816           out_msg.Destination.broadcast(MachineType:L1Cache);
 817           out_msg.Destination.remove(machineID);
 818
 819           out_msg.RetryNum := tbe.IssueCount;
 820           out_msg.isLocal := true;
 821           if (tbe.IssueCount == 0) {
 822             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 823           } else {
 824             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 825           }
 826           out_msg.Prefetch := tbe.Prefetch;
 827           out_msg.AccessMode := tbe.AccessMode;
 828         }
 829
 830         // Increment IssueCount
 831         tbe.IssueCount := tbe.IssueCount + 1;
 832
 833         // Set a wakeup timer
 834
 835         if (dynamic_timeout_enabled) {
 836           reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
 837         } else {
 838           reissueTimerTable.set(address, fixed_timeout_latency);
 839         }
 840
 841       }
 842   }
 843
 844   action(b_issueWriteRequest, "b", desc="Issue GETX") {
 845
 846       assert(is_valid(tbe));
 847       if (tbe.IssueCount == 0) {
 848         // Update outstanding requests
 849         //profile_outstanding_request(outstandingRequests);
 850         outstandingRequests := outstandingRequests + 1;
 851       }
 852
 853       if (tbe.IssueCount >= retry_threshold) {
 854         // Issue a persistent request if possible
 855         if ( okToIssueStarving(address, machineID) && (starving == false)) {
 856           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
 857             out_msg.Address := address;
 858             out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
 859             out_msg.Requestor := machineID;
 860             out_msg.Destination.broadcast(MachineType:L1Cache);
 861
 862             //
 863             // Currently the configuration system limits the system to only one
 864             // chip.  Therefore, if we assume one shared L2 cache, then only one
 865             // pertinent L2 cache exist.
 866             //
 867             //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 868
 869             out_msg.Destination.add(mapAddressToRange(address,
 870                                                       MachineType:L2Cache,
 871                                                       l2_select_low_bit,
 872                                                       l2_select_num_bits));
 873
 874             out_msg.Destination.add(map_Address_to_Directory(address));
 875             out_msg.MessageSize := MessageSizeType:Persistent_Control;
 876             out_msg.Prefetch := tbe.Prefetch;
 877             out_msg.AccessMode := tbe.AccessMode;
 878           }
 879           markPersistentEntries(address);
 880           starving := true;
 881
 882           // Update outstanding requests
 883           //profile_outstanding_persistent_request(outstandingPersistentRequests);
 884           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 885
 886           if (tbe.IssueCount == 0) {
 887             //profile_persistent_prediction(address, tbe.AccessType);
 888           }
 889
 890           // Increment IssueCount
 891           tbe.IssueCount := tbe.IssueCount + 1;
 892
 893           tbe.WentPersistent := true;
 894
 895           // Do not schedule a wakeup, a persistent requests will always complete
 896         }
 897         else {
 898
 899           // We'd like to issue a persistent request, but are not allowed
 900           // to issue a P.R. right now.  This, we do not increment the
 901           // IssueCount.
 902
 903           // Set a wakeup timer
 904           reissueTimerTable.set(address, 10);
 905         }
 906
 907
 908       } else  {
 909         // Make a normal request
 910         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 911           out_msg.Address := address;
 912           out_msg.Type := CoherenceRequestType:GETX;
 913           out_msg.Requestor := machineID;
 914
 915           out_msg.Destination.add(mapAddressToRange(address,
 916                                                     MachineType:L2Cache,
 917                                                     l2_select_low_bit,
 918                                                     l2_select_num_bits));
 919
 920           out_msg.RetryNum := tbe.IssueCount;
 921
 922           if (tbe.IssueCount == 0) {
 923             out_msg.MessageSize := MessageSizeType:Request_Control;
 924           } else {
 925             out_msg.MessageSize := MessageSizeType:Reissue_Control;
 926           }
 927           out_msg.Prefetch := tbe.Prefetch;
 928           out_msg.AccessMode := tbe.AccessMode;
 929         }
 930
 931         // send to other local L1s too
 932         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
 933           out_msg.Address := address;
 934           out_msg.Type := CoherenceRequestType:GETX;
 935           out_msg.Requestor := machineID;
 936           out_msg.isLocal := true;
 937
 938           //
 939           // Since only one chip, assuming all L1 caches are local
 940           //
 941           //out_msg.Destination := getOtherLocalL1IDs(machineID);
 942           out_msg.Destination.broadcast(MachineType:L1Cache);
 943           out_msg.Destination.remove(machineID);
 944
 945           out_msg.RetryNum := tbe.IssueCount;
 946           if (tbe.IssueCount == 0) {
 947             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 948           } else {
 949             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 950           }
 951           out_msg.Prefetch := tbe.Prefetch;
 952           out_msg.AccessMode := tbe.AccessMode;
 953         }
 954
 955         // Increment IssueCount
 956         tbe.IssueCount := tbe.IssueCount + 1;
 957
 958         DPRINTF(RubySlicc, "incremented issue count to %d\n",
 959                 tbe.IssueCount);
 960
 961         // Set a wakeup timer
 962         if (dynamic_timeout_enabled) {
 963           reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
 964         } else {
 965           reissueTimerTable.set(address, fixed_timeout_latency);
 966         }
 967       }
 968   }
 969
 970   action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") {
 971     peek(responseNetwork_in, ResponseMsg) {
 972       // FIXME, should use a 3rd vnet
 973       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 974         out_msg.Address := address;
 975         out_msg.Type := in_msg.Type;
 976         out_msg.Sender := machineID;
 977         out_msg.Destination.add(map_Address_to_Directory(address));
 978         out_msg.Tokens := in_msg.Tokens;
 979         out_msg.MessageSize := in_msg.MessageSize;
 980         out_msg.DataBlk := in_msg.DataBlk;
 981         out_msg.Dirty := in_msg.Dirty;
 982       }
 983     }
 984   }
 985
 986   action(c_ownedReplacement, "c", desc="Issue writeback") {
 987     assert(is_valid(cache_entry));
 988     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
 989       out_msg.Address := address;
 990       out_msg.Sender := machineID;
 991
 992       out_msg.Destination.add(mapAddressToRange(address,
 993                                                 MachineType:L2Cache,
 994                                                 l2_select_low_bit,
 995                                                 l2_select_num_bits));
 996
 997       out_msg.Tokens := cache_entry.Tokens;
 998       out_msg.DataBlk := cache_entry.DataBlk;
 999       out_msg.Dirty := cache_entry.Dirty;
1000       out_msg.Type := CoherenceResponseType:WB_OWNED;
1001
1002       // always send the data?
1003       out_msg.MessageSize := MessageSizeType:Writeback_Data;
1004     }
1005     cache_entry.Tokens := 0;
1006   }
1007
1008   action(cc_sharedReplacement, "\c", desc="Issue shared writeback") {
1009
1010     // don't send writeback if replacing block with no tokens
1011     assert(is_valid(cache_entry));
1012     assert (cache_entry.Tokens > 0);
1013     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1014         out_msg.Address := address;
1015         out_msg.Sender := machineID;
1016
1017         out_msg.Destination.add(mapAddressToRange(address,
1018                                                   MachineType:L2Cache,
1019                                                   l2_select_low_bit,
1020                                                   l2_select_num_bits));
1021
1022         out_msg.Tokens := cache_entry.Tokens;
1023         out_msg.DataBlk := cache_entry.DataBlk;
1024         // assert(cache_entry.Dirty == false);
1025         out_msg.Dirty := false;
1026
1027         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1028         out_msg.Type := CoherenceResponseType:WB_SHARED_DATA;
1029     }
1030     cache_entry.Tokens := 0;
1031   }
1032
1033   action(tr_tokenReplacement, "tr", desc="Issue token writeback") {
1034     assert(is_valid(cache_entry));
1035     if (cache_entry.Tokens > 0) {
1036       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1037         out_msg.Address := address;
1038         out_msg.Sender := machineID;
1039
1040         out_msg.Destination.add(mapAddressToRange(address,
1041                                                   MachineType:L2Cache,
1042                                                   l2_select_low_bit,
1043                                                   l2_select_num_bits));
1044
1045         out_msg.Tokens := cache_entry.Tokens;
1046         out_msg.DataBlk := cache_entry.DataBlk;
1047         // assert(cache_entry.Dirty == false);
1048         out_msg.Dirty := false;
1049
1050         // always send the data?
1051         out_msg.MessageSize := MessageSizeType:Writeback_Control;
1052         out_msg.Type := CoherenceResponseType:WB_TOKENS;
1053       }
1054     }
1055     cache_entry.Tokens := 0;
1056   }
1057
1058
1059   action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") {
1060     assert(is_valid(cache_entry));
1061     peek(requestNetwork_in, RequestMsg) {
1062       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1063         out_msg.Address := address;
1064         out_msg.Type := CoherenceResponseType:DATA_SHARED;
1065         out_msg.Sender := machineID;
1066         out_msg.Destination.add(in_msg.Requestor);
1067         out_msg.Tokens := 1;
1068         out_msg.DataBlk := cache_entry.DataBlk;
1069         // out_msg.Dirty := cache_entry.Dirty;
1070         out_msg.Dirty := false;
1071         if (in_msg.isLocal) {
1072           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1073         } else {
1074           out_msg.MessageSize := MessageSizeType:Response_Data;
1075         }
1076       }
1077     }
1078     cache_entry.Tokens := cache_entry.Tokens - 1;
1079     assert(cache_entry.Tokens >= 1);
1080   }
1081
1082   action(d_sendDataWithNTokenIfAvail, "\dd", desc="Send data and a token from cache to requestor") {
1083     assert(is_valid(cache_entry));
1084     peek(requestNetwork_in, RequestMsg) {
1085       if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1086         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1087           out_msg.Address := address;
1088           out_msg.Type := CoherenceResponseType:DATA_SHARED;
1089           out_msg.Sender := machineID;
1090           out_msg.Destination.add(in_msg.Requestor);
1091           out_msg.Tokens := N_tokens;
1092           out_msg.DataBlk := cache_entry.DataBlk;
1093           // out_msg.Dirty := cache_entry.Dirty;
1094           out_msg.Dirty := false;
1095           if (in_msg.isLocal) {
1096             out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1097           } else {
1098             out_msg.MessageSize := MessageSizeType:Response_Data;
1099           }
1100         }
1101         cache_entry.Tokens := cache_entry.Tokens - N_tokens;
1102       }
1103       else if (cache_entry.Tokens > 1) {
1104         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1105           out_msg.Address := address;
1106           out_msg.Type := CoherenceResponseType:DATA_SHARED;
1107           out_msg.Sender := machineID;
1108           out_msg.Destination.add(in_msg.Requestor);
1109           out_msg.Tokens := 1;
1110           out_msg.DataBlk := cache_entry.DataBlk;
1111           // out_msg.Dirty := cache_entry.Dirty;
1112           out_msg.Dirty := false;
1113           if (in_msg.isLocal) {
1114             out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1115           } else {
1116             out_msg.MessageSize := MessageSizeType:Response_Data;
1117           }
1118         }
1119         cache_entry.Tokens := cache_entry.Tokens - 1;
1120       }
1121     }
1122 //    assert(cache_entry.Tokens >= 1);
1123   }
1124
1125   action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") {
1126     peek(requestNetwork_in, RequestMsg) {
1127     assert(is_valid(cache_entry));
1128       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1129         out_msg.Address := address;
1130         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1131         out_msg.Sender := machineID;
1132         out_msg.Destination.add(in_msg.Requestor);
1133         assert(cache_entry.Tokens > (max_tokens() / 2));
1134         out_msg.Tokens := cache_entry.Tokens;
1135         out_msg.DataBlk := cache_entry.DataBlk;
1136         out_msg.Dirty := cache_entry.Dirty;
1137         if (in_msg.isLocal) {
1138           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1139         } else {
1140           out_msg.MessageSize := MessageSizeType:Response_Data;
1141         }
1142       }
1143     }
1144     cache_entry.Tokens := 0;
1145   }
1146
1147   action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") {
1148     // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1149     assert(is_valid(cache_entry));
1150     if (cache_entry.Tokens > 0) {
1151       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1152         out_msg.Address := address;
1153         if (cache_entry.Tokens > (max_tokens() / 2)) {
1154           out_msg.Type := CoherenceResponseType:DATA_OWNER;
1155         } else {
1156           out_msg.Type := CoherenceResponseType:ACK;
1157         }
1158         out_msg.Sender := machineID;
1159         out_msg.Destination.add(persistentTable.findSmallest(address));
1160         assert(cache_entry.Tokens >= 1);
1161         out_msg.Tokens := cache_entry.Tokens;
1162         out_msg.DataBlk := cache_entry.DataBlk;
1163         out_msg.MessageSize := MessageSizeType:Response_Control;
1164       }
1165     }
1166     cache_entry.Tokens := 0;
1167   }
1168
1169   action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
1170     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1171     assert(is_valid(cache_entry));
1172     assert(cache_entry.Tokens > 0);
1173     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1174       out_msg.Address := address;
1175       out_msg.Type := CoherenceResponseType:DATA_OWNER;
1176       out_msg.Sender := machineID;
1177       out_msg.Destination.add(persistentTable.findSmallest(address));
1178       assert(cache_entry.Tokens > (max_tokens() / 2));
1179       out_msg.Tokens := cache_entry.Tokens;
1180       out_msg.DataBlk := cache_entry.DataBlk;
1181       out_msg.Dirty := cache_entry.Dirty;
1182       out_msg.MessageSize := MessageSizeType:Response_Data;
1183     }
1184     cache_entry.Tokens := 0;
1185   }
1186
1187   action(f_sendAckWithAllButNorOneTokens, "f", desc="Send ack with all our tokens but one to starver.") {
1188     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1189     assert(is_valid(cache_entry));
1190     assert(cache_entry.Tokens > 0);
1191     if (cache_entry.Tokens > 1) {
1192       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1193         out_msg.Address := address;
1194         if (cache_entry.Tokens > (max_tokens() / 2)) {
1195           out_msg.Type := CoherenceResponseType:DATA_OWNER;
1196         } else {
1197           out_msg.Type := CoherenceResponseType:ACK;
1198         }
1199         out_msg.Sender := machineID;
1200         out_msg.Destination.add(persistentTable.findSmallest(address));
1201         assert(cache_entry.Tokens >= 1);
1202         if (cache_entry.Tokens > N_tokens) {
1203           out_msg.Tokens := cache_entry.Tokens - N_tokens;
1204         } else {
1205           out_msg.Tokens := cache_entry.Tokens - 1;
1206         }
1207         out_msg.DataBlk := cache_entry.DataBlk;
1208         out_msg.MessageSize := MessageSizeType:Response_Control;
1209       }
1210     }
1211     if (cache_entry.Tokens > N_tokens) {
1212       cache_entry.Tokens := N_tokens;
1213     } else {
1214       cache_entry.Tokens := 1;
1215     }
1216   }
1217
1218   action(ff_sendDataWithAllButNorOneTokens, "\f", desc="Send data and out tokens but one to starver") {
1219     //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1220     assert(is_valid(cache_entry));
1221     assert(cache_entry.Tokens > ((max_tokens() / 2) + 1));
1222     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1223         out_msg.Address := address;
1224         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1225         out_msg.Sender := machineID;
1226         out_msg.Destination.add(persistentTable.findSmallest(address));
1227         if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1228           out_msg.Tokens := cache_entry.Tokens - N_tokens;
1229         } else {
1230           out_msg.Tokens := cache_entry.Tokens - 1;
1231         }
1232         assert(out_msg.Tokens > (max_tokens() / 2));
1233         out_msg.DataBlk := cache_entry.DataBlk;
1234         out_msg.Dirty := cache_entry.Dirty;
1235         out_msg.MessageSize := MessageSizeType:Response_Data;
1236     }
1237     if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
1238       cache_entry.Tokens := N_tokens;
1239     } else {
1240       cache_entry.Tokens := 1;
1241     }
1242   }
1243
1244   action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") {
1245     assert(is_valid(cache_entry));
1246     assert(cache_entry.Tokens == ((max_tokens() / 2) + 1));
1247     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1248         out_msg.Address := address;
1249         out_msg.Type := CoherenceResponseType:DATA_OWNER;
1250         out_msg.Sender := machineID;
1251         out_msg.Destination.add(persistentTable.findSmallest(address));
1252         out_msg.Tokens := cache_entry.Tokens;
1253         assert(out_msg.Tokens > (max_tokens() / 2));
1254         out_msg.DataBlk := cache_entry.DataBlk;
1255         out_msg.Dirty := cache_entry.Dirty;
1256         out_msg.MessageSize := MessageSizeType:Response_Data;
1257     }
1258     cache_entry.Tokens := 0;
1259   }
1260
1261   action(g_bounceResponseToStarver, "g", desc="Redirect response to starving processor") {
1262     // assert(persistentTable.isLocked(address));
1263
1264     peek(responseNetwork_in, ResponseMsg) {
1265       // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1266       // FIXME, should use a 3rd vnet in some cases
1267       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
1268         out_msg.Address := address;
1269         out_msg.Type := in_msg.Type;
1270         out_msg.Sender := machineID;
1271         out_msg.Destination.add(persistentTable.findSmallest(address));
1272         out_msg.Tokens := in_msg.Tokens;
1273         out_msg.DataBlk := in_msg.DataBlk;
1274         out_msg.Dirty := in_msg.Dirty;
1275         out_msg.MessageSize := in_msg.MessageSize;
1276       }
1277     }
1278   }
1279
1280
1281   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
1282     assert(is_valid(cache_entry));
1283     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1284             address, cache_entry.DataBlk);
1285
1286     sequencer.readCallback(address,
1287                            GenericMachineType:L1Cache,
1288                            cache_entry.DataBlk);
1289
1290   }
1291
1292   action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
1293     assert(is_valid(cache_entry));
1294     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1295             address, cache_entry.DataBlk);
1296     peek(responseNetwork_in, ResponseMsg) {
1297
1298       sequencer.readCallback(address,
1299                              getNondirectHitMachType(address, in_msg.Sender),
1300                              cache_entry.DataBlk);
1301
1302     }
1303   }
1304
1305   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
1306     assert(is_valid(cache_entry));
1307     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1308             address, cache_entry.DataBlk);
1309
1310     sequencer.writeCallback(address,
1311                             GenericMachineType:L1Cache,
1312                             cache_entry.DataBlk);
1313
1314     cache_entry.Dirty := true;
1315     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1316   }
1317
1318   action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
1319     assert(is_valid(cache_entry));
1320     DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1321             address, cache_entry.DataBlk);
1322     peek(responseNetwork_in, ResponseMsg) {
1323
1324       sequencer.writeCallback(address,
1325                               getNondirectHitMachType(address, in_msg.Sender),
1326                               cache_entry.DataBlk);
1327
1328     }
1329     cache_entry.Dirty := true;
1330     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1331   }
1332
1333   action(i_allocateTBE, "i", desc="Allocate TBE") {
1334     check_allocate(L1_TBEs);
1335     L1_TBEs.allocate(address);
1336     set_tbe(L1_TBEs[address]);
1337     tbe.IssueCount := 0;
1338     peek(mandatoryQueue_in, RubyRequest) {
1339       tbe.PC := in_msg.ProgramCounter;
1340       tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
1341       if (in_msg.Type == RubyRequestType:ATOMIC) {
1342         tbe.IsAtomic := true;
1343       }
1344       tbe.Prefetch := in_msg.Prefetch;
1345       tbe.AccessMode := in_msg.AccessMode;
1346     }
1347     tbe.IssueTime := get_time();
1348   }
1349
1350   action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
1351     peek(mandatoryQueue_in, RubyRequest) {
1352       APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1353     }
1354   }
1355
1356   action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
1357     if (reissueTimerTable.isSet(address)) {
1358       reissueTimerTable.unset(address);
1359     }
1360   }
1361
1362   action(jj_unsetUseTimer, "\j", desc="Unset use timer.") {
1363     useTimerTable.unset(address);
1364   }
1365
1366   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
1367     mandatoryQueue_in.dequeue();
1368   }
1369
1370   action(l_popPersistentQueue, "l", desc="Pop persistent queue.") {
1371     persistentNetwork_in.dequeue();
1372   }
1373
1374   action(m_popRequestQueue, "m", desc="Pop request queue.") {
1375     requestNetwork_in.dequeue();
1376   }
1377
1378   action(n_popResponseQueue, "n", desc="Pop response queue") {
1379     responseNetwork_in.dequeue();
1380   }
1381
1382   action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
1383     useTimerTable.set(address, 50);
1384   }
1385
1386   action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
1387     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1388        out_msg.Address := address;
1389        out_msg.Type := CoherenceResponseType:INV;
1390        out_msg.Tokens := 0;
1391        out_msg.Sender := machineID;
1392
1393        out_msg.Destination.add(mapAddressToRange(address,
1394                                                  MachineType:L2Cache,
1395                                                  l2_select_low_bit,
1396                                                  l2_select_num_bits));
1397
1398        out_msg.MessageSize := MessageSizeType:Response_Control;
1399     }
1400   }
1401
1402   action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
1403     peek(responseNetwork_in, ResponseMsg) {
1404       assert(is_valid(cache_entry));
1405       assert(in_msg.Tokens != 0);
1406       DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
1407               in_msg.Address, in_msg.Tokens);
1408       cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
1409       DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
1410
1411       if (cache_entry.Dirty == false && in_msg.Dirty) {
1412         cache_entry.Dirty := true;
1413       }
1414     }
1415   }
1416
1417   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1418
1419     assert(is_valid(tbe));
1420     if (tbe.WentPersistent) {
1421       // assert(starving == true);
1422       outstandingRequests := outstandingRequests - 1;
1423       enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
1424         out_msg.Address := address;
1425         out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
1426         out_msg.Requestor := machineID;
1427         out_msg.Destination.broadcast(MachineType:L1Cache);
1428
1429         //
1430         // Currently the configuration system limits the system to only one
1431         // chip.  Therefore, if we assume one shared L2 cache, then only one
1432         // pertinent L2 cache exist.
1433         //
1434         //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
1435
1436         out_msg.Destination.add(mapAddressToRange(address,
1437                                                   MachineType:L2Cache,
1438                                                   l2_select_low_bit,
1439                                                   l2_select_num_bits));
1440
1441         out_msg.Destination.add(map_Address_to_Directory(address));
1442         out_msg.MessageSize := MessageSizeType:Persistent_Control;
1443       }
1444       starving := false;
1445     }
1446
1447     // Update average latency
1448     if (tbe.IssueCount <= 1) {
1449       if (tbe.ExternalResponse == true) {
1450         updateAverageLatencyEstimate(time_to_int(get_time()) - time_to_int(tbe.IssueTime));
1451       }
1452     }
1453
1454     // Profile
1455     //if (tbe.WentPersistent) {
1456     //  profile_token_retry(address, tbe.AccessType, 2);
1457     //}
1458     //else {
1459     //  profile_token_retry(address, tbe.AccessType, 1);
1460     //}
1461
1462     //profile_token_retry(address, tbe.AccessType, tbe.IssueCount);
1463     L1_TBEs.deallocate(address);
1464     unset_tbe();
1465   }
1466
1467   action(t_sendAckWithCollectedTokens, "t", desc="Send ack with the tokens we've collected thus far.") {
1468     assert(is_valid(cache_entry));
1469     if (cache_entry.Tokens > 0) {
1470       peek(requestNetwork_in, RequestMsg) {
1471         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1472           out_msg.Address := address;
1473           if (cache_entry.Tokens > (max_tokens() / 2)) {
1474             out_msg.Type := CoherenceResponseType:DATA_OWNER;
1475           } else {
1476             out_msg.Type := CoherenceResponseType:ACK;
1477           }
1478           out_msg.Sender := machineID;
1479           out_msg.Destination.add(in_msg.Requestor);
1480           assert(cache_entry.Tokens >= 1);
1481           out_msg.Tokens := cache_entry.Tokens;
1482           out_msg.DataBlk := cache_entry.DataBlk;
1483           out_msg.MessageSize := MessageSizeType:Response_Control;
1484         }
1485       }
1486     }
1487     cache_entry.Tokens := 0;
1488   }
1489
1490   action(u_writeDataToCache, "u", desc="Write data to cache") {
1491     peek(responseNetwork_in, ResponseMsg) {
1492       assert(is_valid(cache_entry));
1493       cache_entry.DataBlk := in_msg.DataBlk;
1494       if (cache_entry.Dirty == false && in_msg.Dirty) {
1495         cache_entry.Dirty := in_msg.Dirty;
1496       }
1497
1498     }
1499   }
1500
1501   action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1502     assert(getTokens(cache_entry) == 0);
1503     if (L1DcacheMemory.isTagPresent(address)) {
1504       L1DcacheMemory.deallocate(address);
1505     } else {
1506       L1IcacheMemory.deallocate(address);
1507     }
1508     unset_cache_entry();
1509   }
1510
1511   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1512     if (is_valid(cache_entry)) {
1513     } else {
1514       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
1515     }
1516   }
1517
1518   action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
1519     if (is_valid(cache_entry)) {
1520     } else {
1521       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
1522     }
1523   }
1524
1525   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
1526     if (send_evictions) {
1527       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1528       sequencer.evictionCallback(address);
1529     }
1530   }
1531
1532   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1533     peek(mandatoryQueue_in, RubyRequest) {
1534       if (L1DcacheMemory.isTagPresent(address)) {
1535         L1DcacheMemory.profileMiss(in_msg);
1536       } else {
1537         L1IcacheMemory.profileMiss(in_msg);
1538       }
1539     }
1540   }
1541
1542   action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
1543     peek(responseNetwork_in, ResponseMsg) {
1544       assert(is_valid(cache_entry));
1545       assert(cache_entry.DataBlk == in_msg.DataBlk);
1546     }
1547   }
1548
1549   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1550     peek(mandatoryQueue_in, RubyRequest) {
1551       APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
1552     }
1553     stall_and_wait(mandatoryQueue_in, address);
1554   }
1555
1556   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1557     wakeUpBuffers(address);
1558   }
1559
1560   action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1561     wakeUpAllBuffers();
1562   }
1563
1564   //*****************************************************
1565   // TRANSITIONS
1566   //*****************************************************
1567
1568   // Transitions for Load/Store/L2_Replacement from transient states
1569   transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
1570     ta_traceStalledAddress;
1571     zz_stallAndWaitMandatoryQueue;
1572   }
1573
1574   transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
1575     zz_stallAndWaitMandatoryQueue;
1576   }
1577
1578   transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
1579     zz_stallAndWaitMandatoryQueue;
1580   }
1581
1582   // Lockdowns
1583   transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
1584     l_popPersistentQueue;
1585   }
1586
1587   // Transitions from NP
1588   transition(NP, Load, IS) {
1589     ii_allocateL1DCacheBlock;
1590     i_allocateTBE;
1591     a_issueReadRequest;
1592     uu_profileMiss;
1593     k_popMandatoryQueue;
1594   }
1595
1596   transition(NP, Ifetch, IS) {
1597     pp_allocateL1ICacheBlock;
1598     i_allocateTBE;
1599     a_issueReadRequest;
1600     uu_profileMiss;
1601     k_popMandatoryQueue;
1602   }
1603
1604   transition(NP, {Store, Atomic}, IM) {
1605     ii_allocateL1DCacheBlock;
1606     i_allocateTBE;
1607     b_issueWriteRequest;
1608     uu_profileMiss;
1609     k_popMandatoryQueue;
1610   }
1611
1612   transition(NP, {Ack, Data_Shared, Data_Owner, Data_All_Tokens}) {
1613     bb_bounceResponse;
1614     n_popResponseQueue;
1615   }
1616
1617   transition(NP, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) {
1618     m_popRequestQueue;
1619   }
1620
1621   transition(NP, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1622     l_popPersistentQueue;
1623   }
1624
1625   // Transitions from Idle
1626   transition(I, Load, IS) {
1627     i_allocateTBE;
1628     a_issueReadRequest;
1629     uu_profileMiss;
1630     k_popMandatoryQueue;
1631   }
1632
1633   transition(I, Ifetch, IS) {
1634     i_allocateTBE;
1635     a_issueReadRequest;
1636     uu_profileMiss;
1637     k_popMandatoryQueue;
1638   }
1639
1640   transition(I, {Store, Atomic}, IM) {
1641     i_allocateTBE;
1642     b_issueWriteRequest;
1643     uu_profileMiss;
1644     k_popMandatoryQueue;
1645   }
1646
1647   transition(I, L1_Replacement) {
1648     ta_traceStalledAddress;
1649     tr_tokenReplacement;
1650     gg_deallocateL1CacheBlock;
1651     ka_wakeUpAllDependents;
1652   }
1653
1654   transition(I, {Transient_GETX, Transient_Local_GETX}) {
1655     t_sendAckWithCollectedTokens;
1656     m_popRequestQueue;
1657   }
1658
1659   transition(I, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1660     m_popRequestQueue;
1661   }
1662
1663   transition(I, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1664     e_sendAckWithCollectedTokens;
1665     l_popPersistentQueue;
1666   }
1667
1668   transition(I_L, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}) {
1669     l_popPersistentQueue;
1670   }
1671
1672   transition(I, Ack) {
1673     q_updateTokensFromResponse;
1674     n_popResponseQueue;
1675   }
1676
1677   transition(I, Data_Shared, S) {
1678     u_writeDataToCache;
1679     q_updateTokensFromResponse;
1680     n_popResponseQueue;
1681   }
1682
1683   transition(I, Data_Owner, O) {
1684     u_writeDataToCache;
1685     q_updateTokensFromResponse;
1686     n_popResponseQueue;
1687   }
1688
1689   transition(I, Data_All_Tokens, M) {
1690     u_writeDataToCache;
1691     q_updateTokensFromResponse;
1692     n_popResponseQueue;
1693   }
1694
1695   // Transitions from Shared
1696   transition({S, SM, S_L, SM_L}, {Load, Ifetch}) {
1697     h_load_hit;
1698     k_popMandatoryQueue;
1699   }
1700
1701   transition(S, {Store, Atomic}, SM) {
1702     i_allocateTBE;
1703     b_issueWriteRequest;
1704     uu_profileMiss;
1705     k_popMandatoryQueue;
1706   }
1707
1708   transition(S, L1_Replacement, I) {
1709     ta_traceStalledAddress;
1710     cc_sharedReplacement; // Only needed in some cases
1711     forward_eviction_to_cpu;
1712     gg_deallocateL1CacheBlock;
1713     ka_wakeUpAllDependents;
1714   }
1715
1716   transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
1717     t_sendAckWithCollectedTokens;
1718     p_informL2AboutTokenLoss;
1719     forward_eviction_to_cpu
1720     m_popRequestQueue;
1721   }
1722
1723   // only owner responds to non-local requests
1724   transition(S, Transient_GETS) {
1725     m_popRequestQueue;
1726   }
1727
1728   transition(S, Transient_Local_GETS) {
1729     d_sendDataWithToken;
1730     m_popRequestQueue;
1731   }
1732
1733   transition(S, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1734     m_popRequestQueue;
1735   }
1736
1737   transition({S, S_L}, Persistent_GETX, I_L) {
1738     e_sendAckWithCollectedTokens;
1739     p_informL2AboutTokenLoss;
1740     forward_eviction_to_cpu
1741     l_popPersistentQueue;
1742   }
1743
1744   transition(S, {Persistent_GETS, Persistent_GETS_Last_Token}, S_L) {
1745     f_sendAckWithAllButNorOneTokens;
1746     l_popPersistentQueue;
1747   }
1748
1749   transition(S_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1750     l_popPersistentQueue;
1751   }
1752
1753   transition(S, Ack) {
1754     q_updateTokensFromResponse;
1755     n_popResponseQueue;
1756   }
1757
1758   transition(S, Data_Shared) {
1759     w_assertIncomingDataAndCacheDataMatch;
1760     q_updateTokensFromResponse;
1761     n_popResponseQueue;
1762   }
1763
1764   transition(S, Data_Owner, O) {
1765     w_assertIncomingDataAndCacheDataMatch;
1766     q_updateTokensFromResponse;
1767     n_popResponseQueue;
1768   }
1769
1770   transition(S, Data_All_Tokens, M) {
1771     w_assertIncomingDataAndCacheDataMatch;
1772     q_updateTokensFromResponse;
1773     n_popResponseQueue;
1774   }
1775
1776   // Transitions from Owned
1777   transition({O, OM}, {Load, Ifetch}) {
1778     h_load_hit;
1779     k_popMandatoryQueue;
1780   }
1781
1782   transition(O, {Store, Atomic}, OM) {
1783     i_allocateTBE;
1784     b_issueWriteRequest;
1785     uu_profileMiss;
1786     k_popMandatoryQueue;
1787   }
1788
1789   transition(O, L1_Replacement, I) {
1790     ta_traceStalledAddress;
1791     c_ownedReplacement;
1792     forward_eviction_to_cpu
1793     gg_deallocateL1CacheBlock;
1794     ka_wakeUpAllDependents;
1795   }
1796
1797   transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
1798     dd_sendDataWithAllTokens;
1799     p_informL2AboutTokenLoss;
1800     forward_eviction_to_cpu
1801     m_popRequestQueue;
1802   }
1803
1804   transition(O, Persistent_GETX, I_L) {
1805     ee_sendDataWithAllTokens;
1806     p_informL2AboutTokenLoss;
1807     forward_eviction_to_cpu
1808     l_popPersistentQueue;
1809   }
1810
1811   transition(O, Persistent_GETS, S_L) {
1812     ff_sendDataWithAllButNorOneTokens;
1813     l_popPersistentQueue;
1814   }
1815
1816   transition(O, Persistent_GETS_Last_Token, I_L) {
1817     fo_sendDataWithOwnerToken;
1818     forward_eviction_to_cpu
1819     l_popPersistentQueue;
1820   }
1821
1822   transition(O, Transient_GETS) {
1823     d_sendDataWithToken;
1824     m_popRequestQueue;
1825   }
1826
1827   transition(O, Transient_Local_GETS) {
1828     d_sendDataWithToken;
1829     m_popRequestQueue;
1830   }
1831
1832   // ran out of tokens, wait for it to go persistent
1833   transition(O, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1834     m_popRequestQueue;
1835   }
1836
1837   transition(O, Ack) {
1838     q_updateTokensFromResponse;
1839     n_popResponseQueue;
1840   }
1841
1842   transition(O, Ack_All_Tokens, M) {
1843     q_updateTokensFromResponse;
1844     n_popResponseQueue;
1845   }
1846
1847   transition(O, Data_Shared) {
1848     w_assertIncomingDataAndCacheDataMatch;
1849     q_updateTokensFromResponse;
1850     n_popResponseQueue;
1851   }
1852
1853   transition(O, Data_All_Tokens, M) {
1854     w_assertIncomingDataAndCacheDataMatch;
1855     q_updateTokensFromResponse;
1856     n_popResponseQueue;
1857   }
1858
1859   // Transitions from Modified
1860   transition({MM, MM_W}, {Load, Ifetch}) {
1861     h_load_hit;
1862     k_popMandatoryQueue;
1863   }
1864
1865   transition({MM_W}, {Store, Atomic}) {
1866     hh_store_hit;
1867     k_popMandatoryQueue;
1868   }
1869
1870   transition(MM, Store) {
1871     hh_store_hit;
1872     k_popMandatoryQueue;
1873   }
1874
1875   transition(MM, Atomic, M) {
1876     hh_store_hit;
1877     k_popMandatoryQueue;
1878   }
1879
1880   transition(MM, L1_Replacement, I) {
1881     ta_traceStalledAddress;
1882     c_ownedReplacement;
1883     forward_eviction_to_cpu
1884     gg_deallocateL1CacheBlock;
1885     ka_wakeUpAllDependents;
1886   }
1887
1888   transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
1889     dd_sendDataWithAllTokens;
1890     p_informL2AboutTokenLoss;
1891     forward_eviction_to_cpu
1892     m_popRequestQueue;
1893   }
1894
1895   transition({MM_W}, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1896     m_popRequestQueue;
1897   }
1898
1899   // Implement the migratory sharing optimization, even for persistent requests
1900   transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
1901     ee_sendDataWithAllTokens;
1902     p_informL2AboutTokenLoss;
1903     forward_eviction_to_cpu
1904     l_popPersistentQueue;
1905   }
1906
1907   // ignore persistent requests in lockout period
1908   transition(MM_W, {Persistent_GETX, Persistent_GETS}) {
1909     l_popPersistentQueue;
1910   }
1911
1912   transition(MM_W, Use_TimeoutNoStarvers, MM) {
1913     s_deallocateTBE;
1914     jj_unsetUseTimer;
1915     kd_wakeUpDependents;
1916   }
1917
1918   transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
1919     s_deallocateTBE;
1920     jj_unsetUseTimer;
1921     kd_wakeUpDependents;
1922   }
1923
1924   // Transitions from Dirty Exclusive
1925   transition({M, M_W}, {Load, Ifetch}) {
1926     h_load_hit;
1927     k_popMandatoryQueue;
1928   }
1929
1930   transition(M, Store, MM) {
1931     hh_store_hit;
1932     k_popMandatoryQueue;
1933   }
1934
1935   transition(M, Atomic) {
1936     hh_store_hit;
1937     k_popMandatoryQueue;
1938   }
1939
1940   transition(M_W, Store, MM_W) {
1941     hh_store_hit;
1942     k_popMandatoryQueue;
1943   }
1944
1945   transition(M_W, Atomic) {
1946     hh_store_hit;
1947     k_popMandatoryQueue;
1948   }
1949
1950   transition(M, L1_Replacement, I) {
1951     ta_traceStalledAddress;
1952     c_ownedReplacement;
1953     forward_eviction_to_cpu
1954     gg_deallocateL1CacheBlock;
1955     ka_wakeUpAllDependents;
1956   }
1957
1958   transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
1959     dd_sendDataWithAllTokens;
1960     p_informL2AboutTokenLoss;
1961     forward_eviction_to_cpu
1962     m_popRequestQueue;
1963   }
1964
1965   transition(M, Transient_Local_GETS, O) {
1966     d_sendDataWithToken;
1967     m_popRequestQueue;
1968   }
1969
1970   transition(M, Transient_GETS, O) {
1971     d_sendDataWithNTokenIfAvail;
1972     m_popRequestQueue;
1973   }
1974
1975   transition(M_W, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1976     m_popRequestQueue;
1977   }
1978
1979   transition(M, Persistent_GETX, I_L) {
1980     ee_sendDataWithAllTokens;
1981     p_informL2AboutTokenLoss;
1982     forward_eviction_to_cpu
1983     l_popPersistentQueue;
1984   }
1985
1986   transition(M, Persistent_GETS, S_L) {
1987     ff_sendDataWithAllButNorOneTokens;
1988     l_popPersistentQueue;
1989   }
1990
1991   // ignore persistent requests in lockout period
1992   transition(M_W, {Persistent_GETX, Persistent_GETS}) {
1993     l_popPersistentQueue;
1994   }
1995
1996   transition(M_W, Use_TimeoutStarverS, S_L) {
1997     s_deallocateTBE;
1998     ff_sendDataWithAllButNorOneTokens;
1999     jj_unsetUseTimer;
2000   }
2001
2002   // someone unlocked during timeout
2003   transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
2004     s_deallocateTBE;
2005     jj_unsetUseTimer;
2006     kd_wakeUpDependents;
2007   }
2008
2009   transition(M_W, Use_TimeoutStarverX, I_L) {
2010     s_deallocateTBE;
2011     ee_sendDataWithAllTokens;
2012     forward_eviction_to_cpu;
2013     p_informL2AboutTokenLoss;
2014     jj_unsetUseTimer;
2015   }
2016
2017   // migratory
2018   transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
2019     s_deallocateTBE;
2020     ee_sendDataWithAllTokens;
2021     forward_eviction_to_cpu;
2022     p_informL2AboutTokenLoss;
2023     jj_unsetUseTimer;
2024
2025   }
2026
2027   // Transient_GETX and Transient_GETS in transient states
2028   transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2029     m_popRequestQueue;  // Even if we have the data, we can pretend we don't have it yet.
2030   }
2031
2032   transition(IS, {Transient_GETX, Transient_Local_GETX}) {
2033     t_sendAckWithCollectedTokens;
2034     m_popRequestQueue;
2035   }
2036
2037   transition(IS, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2038     m_popRequestQueue;
2039   }
2040
2041   transition(IS, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IS_L) {
2042     e_sendAckWithCollectedTokens;
2043     l_popPersistentQueue;
2044   }
2045
2046   transition(IS_L, {Persistent_GETX, Persistent_GETS}) {
2047     l_popPersistentQueue;
2048   }
2049
2050   transition(IM, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IM_L) {
2051     e_sendAckWithCollectedTokens;
2052     l_popPersistentQueue;
2053   }
2054
2055   transition(IM_L, {Persistent_GETX, Persistent_GETS}) {
2056     l_popPersistentQueue;
2057   }
2058
2059   transition({SM, SM_L}, Persistent_GETX, IM_L) {
2060     e_sendAckWithCollectedTokens;
2061     forward_eviction_to_cpu
2062     l_popPersistentQueue;
2063   }
2064
2065   transition(SM, {Persistent_GETS, Persistent_GETS_Last_Token}, SM_L) {
2066     f_sendAckWithAllButNorOneTokens;
2067     l_popPersistentQueue;
2068   }
2069
2070   transition(SM_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
2071     l_popPersistentQueue;
2072   }
2073
2074   transition(OM, Persistent_GETX, IM_L) {
2075     ee_sendDataWithAllTokens;
2076     forward_eviction_to_cpu
2077     l_popPersistentQueue;
2078   }
2079
2080   transition(OM, Persistent_GETS, SM_L) {
2081     ff_sendDataWithAllButNorOneTokens;
2082     l_popPersistentQueue;
2083   }
2084
2085   transition(OM, Persistent_GETS_Last_Token, IM_L) {
2086     fo_sendDataWithOwnerToken;
2087     l_popPersistentQueue;
2088   }
2089
2090   // Transitions from IM/SM
2091
2092   transition({IM, SM}, Ack) {
2093     q_updateTokensFromResponse;
2094     n_popResponseQueue;
2095   }
2096
2097   transition(IM, Data_Shared, SM) {
2098     u_writeDataToCache;
2099     q_updateTokensFromResponse;
2100     n_popResponseQueue;
2101   }
2102
2103   transition(IM, Data_Owner, OM) {
2104     u_writeDataToCache;
2105     q_updateTokensFromResponse;
2106     n_popResponseQueue;
2107   }
2108
2109   transition(IM, Data_All_Tokens, MM_W) {
2110     u_writeDataToCache;
2111     q_updateTokensFromResponse;
2112     xx_external_store_hit;
2113     o_scheduleUseTimeout;
2114     j_unsetReissueTimer;
2115     n_popResponseQueue;
2116     kd_wakeUpDependents;
2117   }
2118
2119   transition(SM, Data_Shared) {
2120     w_assertIncomingDataAndCacheDataMatch;
2121     q_updateTokensFromResponse;
2122     n_popResponseQueue;
2123   }
2124
2125   transition(SM, Data_Owner, OM) {
2126     w_assertIncomingDataAndCacheDataMatch;
2127     q_updateTokensFromResponse;
2128     n_popResponseQueue;
2129   }
2130
2131   transition(SM, Data_All_Tokens, MM_W) {
2132     w_assertIncomingDataAndCacheDataMatch;
2133     q_updateTokensFromResponse;
2134     xx_external_store_hit;
2135     o_scheduleUseTimeout;
2136     j_unsetReissueTimer;
2137     n_popResponseQueue;
2138     kd_wakeUpDependents;
2139   }
2140
2141   transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens.  We give them up here to avoid livelock
2142     t_sendAckWithCollectedTokens;
2143     forward_eviction_to_cpu;
2144     m_popRequestQueue;
2145   }
2146
2147   transition({IM, SM}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2148     m_popRequestQueue;
2149   }
2150
2151   transition({IM, SM}, Request_Timeout) {
2152     j_unsetReissueTimer;
2153     b_issueWriteRequest;
2154   }
2155
2156   // Transitions from OM
2157
2158   transition(OM, Ack) {
2159     q_updateTokensFromResponse;
2160     n_popResponseQueue;
2161   }
2162
2163   transition(OM, Ack_All_Tokens, MM_W) {
2164     q_updateTokensFromResponse;
2165     xx_external_store_hit;
2166     o_scheduleUseTimeout;
2167     j_unsetReissueTimer;
2168     n_popResponseQueue;
2169     kd_wakeUpDependents;
2170   }
2171
2172   transition(OM, Data_Shared) {
2173     w_assertIncomingDataAndCacheDataMatch;
2174     q_updateTokensFromResponse;
2175     n_popResponseQueue;
2176   }
2177
2178   transition(OM, Data_All_Tokens, MM_W) {
2179     w_assertIncomingDataAndCacheDataMatch;
2180     q_updateTokensFromResponse;
2181     xx_external_store_hit;
2182     o_scheduleUseTimeout;
2183     j_unsetReissueTimer;
2184     n_popResponseQueue;
2185     kd_wakeUpDependents;
2186   }
2187
2188   transition(OM, Request_Timeout) {
2189     j_unsetReissueTimer;
2190     b_issueWriteRequest;
2191   }
2192
2193   // Transitions from IS
2194
2195   transition(IS, Ack) {
2196     q_updateTokensFromResponse;
2197     n_popResponseQueue;
2198   }
2199
2200   transition(IS, Data_Shared, S) {
2201     u_writeDataToCache;
2202     q_updateTokensFromResponse;
2203     x_external_load_hit;
2204     s_deallocateTBE;
2205     j_unsetReissueTimer;
2206     n_popResponseQueue;
2207     kd_wakeUpDependents;
2208   }
2209
2210   transition(IS, Data_Owner, O) {
2211     u_writeDataToCache;
2212     q_updateTokensFromResponse;
2213     x_external_load_hit;
2214     s_deallocateTBE;
2215     j_unsetReissueTimer;
2216     n_popResponseQueue;
2217     kd_wakeUpDependents;
2218   }
2219
2220   transition(IS, Data_All_Tokens, M_W) {
2221     u_writeDataToCache;
2222     q_updateTokensFromResponse;
2223     x_external_load_hit;
2224     o_scheduleUseTimeout;
2225     j_unsetReissueTimer;
2226     n_popResponseQueue;
2227     kd_wakeUpDependents;
2228   }
2229
2230   transition(IS, Request_Timeout) {
2231     j_unsetReissueTimer;
2232     a_issueReadRequest;
2233   }
2234
2235   // Transitions from I_L
2236
2237   transition(I_L, Load, IS_L) {
2238     ii_allocateL1DCacheBlock;
2239     i_allocateTBE;
2240     a_issueReadRequest;
2241     uu_profileMiss;
2242     k_popMandatoryQueue;
2243   }
2244
2245   transition(I_L, Ifetch, IS_L) {
2246     pp_allocateL1ICacheBlock;
2247     i_allocateTBE;
2248     a_issueReadRequest;
2249     uu_profileMiss;
2250     k_popMandatoryQueue;
2251   }
2252
2253   transition(I_L, {Store, Atomic}, IM_L) {
2254     ii_allocateL1DCacheBlock;
2255     i_allocateTBE;
2256     b_issueWriteRequest;
2257     uu_profileMiss;
2258     k_popMandatoryQueue;
2259   }
2260
2261
2262   // Transitions from S_L
2263
2264   transition(S_L, {Store, Atomic}, SM_L) {
2265     i_allocateTBE;
2266     b_issueWriteRequest;
2267     uu_profileMiss;
2268     k_popMandatoryQueue;
2269   }
2270
2271   // Other transitions from *_L states
2272
2273   transition({I_L, IM_L, IS_L, S_L, SM_L}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS, Transient_GETX, Transient_Local_GETX}) {
2274     m_popRequestQueue;
2275   }
2276
2277   transition({I_L, IM_L, IS_L, S_L, SM_L}, Ack) {
2278     g_bounceResponseToStarver;
2279     n_popResponseQueue;
2280   }
2281
2282   transition({I_L, IM_L, S_L, SM_L}, {Data_Shared, Data_Owner}) {
2283     g_bounceResponseToStarver;
2284     n_popResponseQueue;
2285   }
2286
2287   transition({I_L, S_L}, Data_All_Tokens) {
2288     g_bounceResponseToStarver;
2289     n_popResponseQueue;
2290   }
2291
2292   transition(IS_L, Request_Timeout) {
2293     j_unsetReissueTimer;
2294     a_issueReadRequest;
2295   }
2296
2297   transition({IM_L, SM_L}, Request_Timeout) {
2298     j_unsetReissueTimer;
2299     b_issueWriteRequest;
2300   }
2301
2302   // Opportunisticly Complete the memory operation in the following
2303   // cases.  Note: these transitions could just use
2304   // g_bounceResponseToStarver, but if we have the data and tokens, we
2305   // might as well complete the memory request while we have the
2306   // chance (and then immediately forward on the data)
2307
2308   transition(IM_L, Data_All_Tokens, MM_W) {
2309     u_writeDataToCache;
2310     q_updateTokensFromResponse;
2311     xx_external_store_hit;
2312     j_unsetReissueTimer;
2313     o_scheduleUseTimeout;
2314     n_popResponseQueue;
2315     kd_wakeUpDependents;
2316   }
2317
2318   transition(SM_L, Data_All_Tokens, S_L) {
2319     u_writeDataToCache;
2320     q_updateTokensFromResponse;
2321     xx_external_store_hit;
2322     ff_sendDataWithAllButNorOneTokens;
2323     s_deallocateTBE;
2324     j_unsetReissueTimer;
2325     n_popResponseQueue;
2326   }
2327
2328   transition(IS_L, Data_Shared, I_L) {
2329     u_writeDataToCache;
2330     q_updateTokensFromResponse;
2331     x_external_load_hit;
2332     s_deallocateTBE;
2333     e_sendAckWithCollectedTokens;
2334     p_informL2AboutTokenLoss;
2335     j_unsetReissueTimer;
2336     n_popResponseQueue;
2337   }
2338
2339   transition(IS_L, Data_Owner, I_L) {
2340     u_writeDataToCache;
2341     q_updateTokensFromResponse;
2342     x_external_load_hit;
2343     ee_sendDataWithAllTokens;
2344     s_deallocateTBE;
2345     p_informL2AboutTokenLoss;
2346     j_unsetReissueTimer;
2347     n_popResponseQueue;
2348   }
2349
2350   transition(IS_L, Data_All_Tokens, M_W) {
2351     u_writeDataToCache;
2352     q_updateTokensFromResponse;
2353     x_external_load_hit;
2354     j_unsetReissueTimer;
2355     o_scheduleUseTimeout;
2356     n_popResponseQueue;
2357     kd_wakeUpDependents;
2358   }
2359
2360   // Own_Lock_or_Unlock
2361
2362   transition(I_L, Own_Lock_or_Unlock, I) {
2363     l_popPersistentQueue;
2364     kd_wakeUpDependents;
2365   }
2366
2367   transition(S_L, Own_Lock_or_Unlock, S) {
2368     l_popPersistentQueue;
2369     kd_wakeUpDependents;
2370   }
2371
2372   transition(IM_L, Own_Lock_or_Unlock, IM) {
2373     l_popPersistentQueue;
2374     kd_wakeUpDependents;
2375   }
2376
2377   transition(IS_L, Own_Lock_or_Unlock, IS) {
2378     l_popPersistentQueue;
2379     kd_wakeUpDependents;
2380   }
2381
2382   transition(SM_L, Own_Lock_or_Unlock, SM) {
2383     l_popPersistentQueue;
2384     kd_wakeUpDependents;
2385   }
2386 }