3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
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17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * $Id: MOESI_CMP_token-L1cache.sm 1.22 05/01/19 15:55:39-06:00 beckmann@s0-28.cs.wisc.edu $
35 machine(L1Cache, "Token protocol")
36 : Sequencer * sequencer,
37 CacheMemory * L1IcacheMemory,
38 CacheMemory * L1DcacheMemory,
39 int l2_select_num_bits,
41 int l1_request_latency = 2,
42 int l1_response_latency = 2,
43 int retry_threshold = 1,
44 int fixed_timeout_latency = 100,
45 bool dynamic_timeout_enabled = true,
46 bool no_mig_atomic = true
49 // From this node's L1 cache TO the network
51 // a local L1 -> this L2 bank
52 MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false";
53 MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true";
54 // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
55 MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false";
58 // To this node's L1 cache FROM the network
59 // a L2 bank -> this L1
60 MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false";
61 MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true";
62 // a L2 bank -> this L1
63 MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
66 enumeration(State, desc="Cache states", default="L1Cache_State_I") {
68 NP, "NP", desc="Not Present";
70 S, "S", desc="Shared";
72 M, "M", desc="Modified (dirty)";
73 MM, "MM", desc="Modified (dirty and locally modified)";
74 M_W, "M^W", desc="Modified (dirty), waiting";
75 MM_W, "MM^W", desc="Modified (dirty and locally modified), waiting";
78 IM, "IM", desc="Issued GetX";
79 SM, "SM", desc="Issued GetX, we still have an old copy of the line";
80 OM, "OM", desc="Issued GetX, received data";
81 IS, "IS", desc="Issued GetS";
84 I_L, "I^L", desc="Invalid, Locked";
85 S_L, "S^L", desc="Shared, Locked";
86 IM_L, "IM^L", desc="Invalid, Locked, trying to go to Modified";
87 SM_L, "SM^L", desc="Shared, Locked, trying to go to Modified";
88 IS_L, "IS^L", desc="Invalid, Locked, trying to go to Shared";
92 enumeration(Event, desc="Cache events") {
93 Load, desc="Load request from the processor";
94 Ifetch, desc="I-fetch request from the processor";
95 Store, desc="Store request from the processor";
96 Atomic, desc="Atomic request from the processor";
97 L1_Replacement, desc="L1 Replacement";
100 Data_Shared, desc="Received a data message, we are now a sharer";
101 Data_Owner, desc="Received a data message, we are now the owner";
102 Data_All_Tokens, desc="Received a data message, we are now the owner, we now have all the tokens";
103 Ack, desc="Received an ack message";
104 Ack_All_Tokens, desc="Received an ack message, we now have all the tokens";
107 Transient_GETX, desc="A GetX from another processor";
108 Transient_Local_GETX, desc="A GetX from another processor";
109 Transient_GETS, desc="A GetS from another processor";
110 Transient_Local_GETS, desc="A GetS from another processor";
111 Transient_GETS_Last_Token, desc="A GetS from another processor";
112 Transient_Local_GETS_Last_Token, desc="A GetS from another processor";
114 // Lock/Unlock for distributed
115 Persistent_GETX, desc="Another processor has priority to read/write";
116 Persistent_GETS, desc="Another processor has priority to read";
117 Persistent_GETS_Last_Token, desc="Another processor has priority to read, no more tokens";
118 Own_Lock_or_Unlock, desc="This processor now has priority";
121 Request_Timeout, desc="Timeout";
122 Use_TimeoutStarverX, desc="Timeout";
123 Use_TimeoutStarverS, desc="Timeout";
124 Use_TimeoutNoStarvers, desc="Timeout";
125 Use_TimeoutNoStarvers_NoMig, desc="Timeout Don't Migrate";
131 structure(Entry, desc="...", interface="AbstractCacheEntry") {
132 State CacheState, desc="cache state";
133 bool Dirty, desc="Is the data dirty (different than memory)?";
134 int Tokens, desc="The number of tokens we're holding for the line";
135 DataBlock DataBlk, desc="data for the block";
140 structure(TBE, desc="...") {
141 Address Address, desc="Physical address for this TBE";
142 State TBEState, desc="Transient state";
143 int IssueCount, default="0", desc="The number of times we've issued a request for this line.";
144 Address PC, desc="Program counter of request";
146 bool WentPersistent, default="false", desc="Request went persistent";
147 bool ExternalResponse, default="false", desc="Response came from an external controller";
148 bool IsAtomic, default="false", desc="Request was an atomic request";
150 AccessType AccessType, desc="Type of request (used for profiling)";
151 Time IssueTime, desc="Time the request was issued";
152 AccessModeType AccessMode, desc="user/supervisor access type";
153 PrefetchBit Prefetch, desc="Is this a prefetch request";
156 external_type(TBETable) {
158 void allocate(Address);
159 void deallocate(Address);
160 bool isPresent(Address);
163 external_type(PersistentTable) {
164 void persistentRequestLock(Address, MachineID, AccessType);
165 void persistentRequestUnlock(Address, MachineID);
166 bool okToIssueStarving(Address, MachineID);
167 MachineID findSmallest(Address);
168 AccessType typeOfSmallest(Address);
169 void markEntries(Address);
170 bool isLocked(Address);
171 int countStarvingForAddress(Address);
172 int countReadStarvingForAddress(Address);
175 TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
177 MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
179 bool starving, default="false";
180 int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
182 PersistentTable persistentTable;
183 TimerTable useTimerTable;
184 TimerTable reissueTimerTable;
186 int outstandingRequests, default="0";
187 int outstandingPersistentRequests, default="0";
189 int averageLatencyHysteresis, default="(8)"; // Constant that provides hysteresis for calculated the estimated average
190 int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))";
192 int averageLatencyEstimate() {
193 DPRINTF(RubySlicc, "%d\n",
194 (averageLatencyCounter >> averageLatencyHysteresis));
195 //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
196 return averageLatencyCounter >> averageLatencyHysteresis;
199 void updateAverageLatencyEstimate(int latency) {
200 DPRINTF(RubySlicc, "%d\n", latency);
201 assert(latency >= 0);
203 // By subtracting the current average and then adding the most
204 // recent sample, we calculate an estimate of the recent average.
205 // If we simply used a running sum and divided by the total number
206 // of entries, the estimate of the average would adapt very slowly
207 // after the execution has run for a long time.
208 // averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
210 averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
214 Entry getCacheEntry(Address addr), return_by_ref="yes" {
215 if (L1DcacheMemory.isTagPresent(addr)) {
216 assert(L1IcacheMemory.isTagPresent(addr) == false);
217 return static_cast(Entry, L1DcacheMemory[addr]);
219 return static_cast(Entry, L1IcacheMemory[addr]);
223 int getTokens(Address addr) {
224 if (L1DcacheMemory.isTagPresent(addr)) {
225 assert(L1IcacheMemory.isTagPresent(addr) == false);
226 return static_cast(Entry, L1DcacheMemory[addr]).Tokens;
227 } else if (L1IcacheMemory.isTagPresent(addr)) {
228 return static_cast(Entry, L1IcacheMemory[addr]).Tokens;
234 void changePermission(Address addr, AccessPermission permission) {
235 if (L1DcacheMemory.isTagPresent(addr)) {
236 return L1DcacheMemory.changePermission(addr, permission);
238 return L1IcacheMemory.changePermission(addr, permission);
242 bool isCacheTagPresent(Address addr) {
243 return (L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
246 State getState(Address addr) {
247 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
249 if (L1_TBEs.isPresent(addr)) {
250 return L1_TBEs[addr].TBEState;
251 } else if (isCacheTagPresent(addr)) {
252 return getCacheEntry(addr).CacheState;
254 if ((persistentTable.isLocked(addr) == true) && (persistentTable.findSmallest(addr) != machineID)) {
255 // Not in cache, in persistent table, but this processor isn't highest priority
263 void setState(Address addr, State state) {
264 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
266 if (L1_TBEs.isPresent(addr)) {
267 assert(state != State:I);
268 assert(state != State:S);
269 assert(state != State:O);
270 assert(state != State:MM);
271 assert(state != State:M);
272 L1_TBEs[addr].TBEState := state;
275 if (isCacheTagPresent(addr)) {
276 // Make sure the token count is in range
277 assert(getCacheEntry(addr).Tokens >= 0);
278 assert(getCacheEntry(addr).Tokens <= max_tokens());
279 assert(getCacheEntry(addr).Tokens != (max_tokens() / 2));
281 if ((state == State:I_L) ||
282 (state == State:IM_L) ||
283 (state == State:IS_L)) {
284 // Make sure we have no tokens in the "Invalid, locked" states
285 if (isCacheTagPresent(addr)) {
286 assert(getCacheEntry(addr).Tokens == 0);
289 // Make sure the line is locked
290 // assert(persistentTable.isLocked(addr));
292 // But we shouldn't have highest priority for it
293 // assert(persistentTable.findSmallest(addr) != id);
295 } else if ((state == State:S_L) ||
296 (state == State:SM_L)) {
297 assert(getCacheEntry(addr).Tokens >= 1);
298 assert(getCacheEntry(addr).Tokens < (max_tokens() / 2));
300 // Make sure the line is locked...
301 // assert(persistentTable.isLocked(addr));
303 // ...But we shouldn't have highest priority for it...
304 // assert(persistentTable.findSmallest(addr) != id);
306 // ...And it must be a GETS request
307 // assert(persistentTable.typeOfSmallest(addr) == AccessType:Read);
311 // If there is an entry in the persistent table of this block,
312 // this processor needs to have an entry in the table for this
313 // block, and that entry better be the smallest (highest
314 // priority). Otherwise, the state should have been one of
317 //if (persistentTable.isLocked(addr)) {
318 // assert(persistentTable.findSmallest(addr) == id);
322 // in M and E you have all the tokens
323 if (state == State:MM || state == State:M || state == State:MM_W || state == State:M_W) {
324 assert(getCacheEntry(addr).Tokens == max_tokens());
327 // in NP you have no tokens
328 if (state == State:NP) {
329 assert(getCacheEntry(addr).Tokens == 0);
332 // You have at least one token in S-like states
333 if (state == State:S || state == State:SM) {
334 assert(getCacheEntry(addr).Tokens > 0);
337 // You have at least half the token in O-like states
338 if (state == State:O && state == State:OM) {
339 assert(getCacheEntry(addr).Tokens > (max_tokens() / 2));
342 getCacheEntry(addr).CacheState := state;
345 if (state == State:MM ||
346 state == State:MM_W) {
347 changePermission(addr, AccessPermission:Read_Write);
348 } else if ((state == State:S) ||
349 (state == State:O) ||
350 (state == State:M) ||
351 (state == State:M_W) ||
352 (state == State:SM) ||
353 (state == State:S_L) ||
354 (state == State:SM_L) ||
355 (state == State:OM)) {
356 changePermission(addr, AccessPermission:Read_Only);
358 changePermission(addr, AccessPermission:Invalid);
363 Event mandatory_request_type_to_event(CacheRequestType type) {
364 if (type == CacheRequestType:LD) {
366 } else if (type == CacheRequestType:IFETCH) {
368 } else if (type == CacheRequestType:ST) {
370 } else if (type == CacheRequestType:ATOMIC) {
377 error("Invalid CacheRequestType");
381 AccessType cache_request_type_to_access_type(CacheRequestType type) {
382 if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) {
383 return AccessType:Read;
384 } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
385 return AccessType:Write;
387 error("Invalid CacheRequestType");
391 GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
392 if (machineIDToMachineType(sender) == MachineType:L1Cache) {
394 // NOTE direct local hits should not call this
396 return GenericMachineType:L1Cache_wCC;
397 } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
399 if (sender == (mapAddressToRange(addr,
402 l2_select_num_bits))) {
404 return GenericMachineType:L2Cache;
406 return GenericMachineType:L2Cache_wCC;
409 return ConvertMachToGenericMach(machineIDToMachineType(sender));
413 bool okToIssueStarving(Address addr, MachineID machinID) {
414 return persistentTable.okToIssueStarving(addr, machineID);
417 void markPersistentEntries(Address addr) {
418 persistentTable.markEntries(addr);
422 out_port(persistentNetwork_out, PersistentMsg, persistentFromL1Cache);
423 out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
424 out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
425 out_port(requestRecycle_out, RequestMsg, requestToL1Cache);
430 in_port(useTimerTable_in, Address, useTimerTable) {
431 if (useTimerTable_in.isReady()) {
432 if (persistentTable.isLocked(useTimerTable.readyAddress()) && (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
433 if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
434 trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress());
436 trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress());
439 assert(L1_TBEs.isPresent(useTimerTable.readyAddress()));
440 if (no_mig_atomic && L1_TBEs[useTimerTable.readyAddress()].IsAtomic) {
441 trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress());
443 trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress());
450 in_port(reissueTimerTable_in, Address, reissueTimerTable) {
451 if (reissueTimerTable_in.isReady()) {
452 trigger(Event:Request_Timeout, reissueTimerTable.readyAddress());
458 // Persistent Network
459 in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache) {
460 if (persistentNetwork_in.isReady()) {
461 peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
462 assert(in_msg.Destination.isElement(machineID));
464 // Apply the lockdown or unlockdown message to the table
465 if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
466 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
467 } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
468 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
469 } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
470 persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
472 error("Unexpected message");
475 // React to the message based on the current state of the table
476 if (persistentTable.isLocked(in_msg.Address)) {
477 if (persistentTable.findSmallest(in_msg.Address) == machineID) {
478 // Our Own Lock - this processor is highest priority
479 trigger(Event:Own_Lock_or_Unlock, in_msg.Address);
481 if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
482 if (getTokens(in_msg.Address) == 1 ||
483 getTokens(in_msg.Address) == (max_tokens() / 2) + 1) {
484 trigger(Event:Persistent_GETS_Last_Token, in_msg.Address);
486 trigger(Event:Persistent_GETS, in_msg.Address);
489 trigger(Event:Persistent_GETX, in_msg.Address);
493 // Unlock case - no entries in the table
494 trigger(Event:Own_Lock_or_Unlock, in_msg.Address);
502 in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
503 if (requestNetwork_in.isReady()) {
504 peek(requestNetwork_in, RequestMsg, block_on="Address") {
505 assert(in_msg.Destination.isElement(machineID));
506 if (in_msg.Type == CoherenceRequestType:GETX) {
507 if (in_msg.isLocal) {
508 trigger(Event:Transient_Local_GETX, in_msg.Address);
511 trigger(Event:Transient_GETX, in_msg.Address);
513 } else if (in_msg.Type == CoherenceRequestType:GETS) {
514 if (getTokens(in_msg.Address) == 1 ||
515 getTokens(in_msg.Address) == (max_tokens() / 2) + 1) {
516 if (in_msg.isLocal) {
517 trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address);
520 trigger(Event:Transient_GETS_Last_Token, in_msg.Address);
524 if (in_msg.isLocal) {
525 trigger(Event:Transient_Local_GETS, in_msg.Address);
528 trigger(Event:Transient_GETS, in_msg.Address);
532 error("Unexpected message");
539 in_port(responseNetwork_in, ResponseMsg, responseToL1Cache) {
540 if (responseNetwork_in.isReady()) {
541 peek(responseNetwork_in, ResponseMsg, block_on="Address") {
542 assert(in_msg.Destination.isElement(machineID));
544 // Mark TBE flag if response received off-chip. Use this to update average latency estimate
545 if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
547 if (in_msg.Sender == mapAddressToRange(in_msg.Address,
550 l2_select_num_bits)) {
552 // came from an off-chip L2 cache
553 if (L1_TBEs.isPresent(in_msg.Address)) {
554 // L1_TBEs[in_msg.Address].ExternalResponse := true;
555 // profile_offchipL2_response(in_msg.Address);
559 // profile_onchipL2_response(in_msg.Address );
561 } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
562 if (L1_TBEs.isPresent(in_msg.Address)) {
563 L1_TBEs[in_msg.Address].ExternalResponse := true;
564 // profile_memory_response( in_msg.Address);
566 } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
567 //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
568 //if (L1_TBEs.isPresent(in_msg.Address)) {
569 // L1_TBEs[in_msg.Address].ExternalResponse := true;
570 // profile_offchipL1_response(in_msg.Address );
574 // profile_onchipL1_response(in_msg.Address );
577 error("unexpected SenderMachine");
581 if (getTokens(in_msg.Address) + in_msg.Tokens != max_tokens()) {
582 if (in_msg.Type == CoherenceResponseType:ACK) {
583 assert(in_msg.Tokens < (max_tokens() / 2));
584 trigger(Event:Ack, in_msg.Address);
585 } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
586 trigger(Event:Data_Owner, in_msg.Address);
587 } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
588 assert(in_msg.Tokens < (max_tokens() / 2));
589 trigger(Event:Data_Shared, in_msg.Address);
591 error("Unexpected message");
594 if (in_msg.Type == CoherenceResponseType:ACK) {
595 assert(in_msg.Tokens < (max_tokens() / 2));
596 trigger(Event:Ack_All_Tokens, in_msg.Address);
597 } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
598 trigger(Event:Data_All_Tokens, in_msg.Address);
600 error("Unexpected message");
608 in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
609 if (mandatoryQueue_in.isReady()) {
610 peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
611 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
613 if (in_msg.Type == CacheRequestType:IFETCH) {
614 // ** INSTRUCTION ACCESS ***
616 // Check to see if it is in the OTHER L1
617 if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) {
618 // The block is in the wrong L1, try to write it to the L2
619 trigger(Event:L1_Replacement, in_msg.LineAddress);
622 if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) {
623 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
624 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
626 if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
627 // L1 does't have the line, but we have space for it in the L1
628 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
630 // No room in the L1, so we need to make room
631 trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress));
635 // *** DATA ACCESS ***
637 // Check to see if it is in the OTHER L1
638 if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) {
639 // The block is in the wrong L1, try to write it to the L2
640 trigger(Event:L1_Replacement, in_msg.LineAddress);
643 if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) {
644 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
645 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
647 if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
648 // L1 does't have the line, but we have space for it in the L1
649 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
651 // No room in the L1, so we need to make room
652 trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress));
662 action(a_issueReadRequest, "a", desc="Issue GETS") {
663 if (L1_TBEs[address].IssueCount == 0) {
664 // Update outstanding requests
665 //profile_outstanding_request(outstandingRequests);
666 outstandingRequests := outstandingRequests + 1;
669 if (L1_TBEs[address].IssueCount >= retry_threshold) {
670 // Issue a persistent request if possible
671 if (okToIssueStarving(address, machineID) && (starving == false)) {
672 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
673 out_msg.Address := address;
674 out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
675 out_msg.Requestor := machineID;
676 out_msg.Destination.broadcast(MachineType:L1Cache);
679 // Currently the configuration system limits the system to only one
680 // chip. Therefore, if we assume one shared L2 cache, then only one
681 // pertinent L2 cache exist.
683 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
685 out_msg.Destination.add(mapAddressToRange(address,
688 l2_select_num_bits));
690 out_msg.Destination.add(map_Address_to_Directory(address));
691 out_msg.MessageSize := MessageSizeType:Persistent_Control;
692 out_msg.Prefetch := L1_TBEs[address].Prefetch;
693 out_msg.AccessMode := L1_TBEs[address].AccessMode;
695 markPersistentEntries(address);
698 if (L1_TBEs[address].IssueCount == 0) {
699 //profile_persistent_prediction(address, L1_TBEs[address].AccessType);
702 // Update outstanding requests
703 //profile_outstanding_persistent_request(outstandingPersistentRequests);
704 outstandingPersistentRequests := outstandingPersistentRequests + 1;
706 // Increment IssueCount
707 L1_TBEs[address].IssueCount := L1_TBEs[address].IssueCount + 1;
709 L1_TBEs[address].WentPersistent := true;
711 // Do not schedule a wakeup, a persistent requests will always complete
715 // We'd like to issue a persistent request, but are not allowed
716 // to issue a P.R. right now. This, we do not increment the
719 // Set a wakeup timer
720 reissueTimerTable.set(address, 10);
724 // Make a normal request
725 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
726 out_msg.Address := address;
727 out_msg.Type := CoherenceRequestType:GETS;
728 out_msg.Requestor := machineID;
729 out_msg.Destination.add(mapAddressToRange(address,
732 l2_select_num_bits));
734 out_msg.RetryNum := L1_TBEs[address].IssueCount;
735 if (L1_TBEs[address].IssueCount == 0) {
736 out_msg.MessageSize := MessageSizeType:Request_Control;
738 out_msg.MessageSize := MessageSizeType:Reissue_Control;
740 out_msg.Prefetch := L1_TBEs[address].Prefetch;
741 out_msg.AccessMode := L1_TBEs[address].AccessMode;
744 // send to other local L1s, with local bit set
745 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
746 out_msg.Address := address;
747 out_msg.Type := CoherenceRequestType:GETS;
748 out_msg.Requestor := machineID;
750 // Since only one chip, assuming all L1 caches are local
752 //out_msg.Destination := getOtherLocalL1IDs(machineID);
753 out_msg.Destination.broadcast(MachineType:L1Cache);
754 out_msg.Destination.remove(machineID);
756 out_msg.RetryNum := L1_TBEs[address].IssueCount;
757 out_msg.isLocal := true;
758 if (L1_TBEs[address].IssueCount == 0) {
759 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
761 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
763 out_msg.Prefetch := L1_TBEs[address].Prefetch;
764 out_msg.AccessMode := L1_TBEs[address].AccessMode;
767 // Increment IssueCount
768 L1_TBEs[address].IssueCount := L1_TBEs[address].IssueCount + 1;
770 // Set a wakeup timer
772 if (dynamic_timeout_enabled) {
773 reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
775 reissueTimerTable.set(address, fixed_timeout_latency);
781 action(b_issueWriteRequest, "b", desc="Issue GETX") {
783 if (L1_TBEs[address].IssueCount == 0) {
784 // Update outstanding requests
785 //profile_outstanding_request(outstandingRequests);
786 outstandingRequests := outstandingRequests + 1;
789 if (L1_TBEs[address].IssueCount >= retry_threshold) {
790 // Issue a persistent request if possible
791 if ( okToIssueStarving(address, machineID) && (starving == false)) {
792 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
793 out_msg.Address := address;
794 out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
795 out_msg.Requestor := machineID;
796 out_msg.Destination.broadcast(MachineType:L1Cache);
799 // Currently the configuration system limits the system to only one
800 // chip. Therefore, if we assume one shared L2 cache, then only one
801 // pertinent L2 cache exist.
803 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
805 out_msg.Destination.add(mapAddressToRange(address,
808 l2_select_num_bits));
810 out_msg.Destination.add(map_Address_to_Directory(address));
811 out_msg.MessageSize := MessageSizeType:Persistent_Control;
812 out_msg.Prefetch := L1_TBEs[address].Prefetch;
813 out_msg.AccessMode := L1_TBEs[address].AccessMode;
815 markPersistentEntries(address);
818 // Update outstanding requests
819 //profile_outstanding_persistent_request(outstandingPersistentRequests);
820 outstandingPersistentRequests := outstandingPersistentRequests + 1;
822 if (L1_TBEs[address].IssueCount == 0) {
823 //profile_persistent_prediction(address, L1_TBEs[address].AccessType);
826 // Increment IssueCount
827 L1_TBEs[address].IssueCount := L1_TBEs[address].IssueCount + 1;
829 L1_TBEs[address].WentPersistent := true;
831 // Do not schedule a wakeup, a persistent requests will always complete
835 // We'd like to issue a persistent request, but are not allowed
836 // to issue a P.R. right now. This, we do not increment the
839 // Set a wakeup timer
840 reissueTimerTable.set(address, 10);
845 // Make a normal request
846 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
847 out_msg.Address := address;
848 out_msg.Type := CoherenceRequestType:GETX;
849 out_msg.Requestor := machineID;
851 out_msg.Destination.add(mapAddressToRange(address,
854 l2_select_num_bits));
856 out_msg.RetryNum := L1_TBEs[address].IssueCount;
858 if (L1_TBEs[address].IssueCount == 0) {
859 out_msg.MessageSize := MessageSizeType:Request_Control;
861 out_msg.MessageSize := MessageSizeType:Reissue_Control;
863 out_msg.Prefetch := L1_TBEs[address].Prefetch;
864 out_msg.AccessMode := L1_TBEs[address].AccessMode;
867 // send to other local L1s too
868 enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
869 out_msg.Address := address;
870 out_msg.Type := CoherenceRequestType:GETX;
871 out_msg.Requestor := machineID;
872 out_msg.isLocal := true;
875 // Since only one chip, assuming all L1 caches are local
877 //out_msg.Destination := getOtherLocalL1IDs(machineID);
878 out_msg.Destination.broadcast(MachineType:L1Cache);
879 out_msg.Destination.remove(machineID);
881 out_msg.RetryNum := L1_TBEs[address].IssueCount;
882 if (L1_TBEs[address].IssueCount == 0) {
883 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
885 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
887 out_msg.Prefetch := L1_TBEs[address].Prefetch;
888 out_msg.AccessMode := L1_TBEs[address].AccessMode;
891 // Increment IssueCount
892 L1_TBEs[address].IssueCount := L1_TBEs[address].IssueCount + 1;
894 DPRINTF(RubySlicc, "incremented issue count to %d\n",
895 L1_TBEs[address].IssueCount);
897 // Set a wakeup timer
898 if (dynamic_timeout_enabled) {
899 reissueTimerTable.set(address, 1.25 * averageLatencyEstimate());
901 reissueTimerTable.set(address, fixed_timeout_latency);
906 action(bb_bounceResponse, "\b", desc="Bounce tokens and data to memory") {
907 peek(responseNetwork_in, ResponseMsg) {
908 // FIXME, should use a 3rd vnet
909 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
910 out_msg.Address := address;
911 out_msg.Type := in_msg.Type;
912 out_msg.Sender := machineID;
913 out_msg.Destination.add(map_Address_to_Directory(address));
914 out_msg.Tokens := in_msg.Tokens;
915 out_msg.MessageSize := in_msg.MessageSize;
916 out_msg.DataBlk := in_msg.DataBlk;
917 out_msg.Dirty := in_msg.Dirty;
922 action(c_ownedReplacement, "c", desc="Issue writeback") {
923 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
924 out_msg.Address := address;
925 out_msg.Sender := machineID;
927 out_msg.Destination.add(mapAddressToRange(address,
930 l2_select_num_bits));
932 out_msg.Tokens := getCacheEntry(address).Tokens;
933 out_msg.DataBlk := getCacheEntry(address).DataBlk;
934 out_msg.Dirty := getCacheEntry(address).Dirty;
935 out_msg.Type := CoherenceResponseType:WB_OWNED;
937 // always send the data?
938 out_msg.MessageSize := MessageSizeType:Writeback_Data;
940 getCacheEntry(address).Tokens := 0;
943 action(cc_sharedReplacement, "\c", desc="Issue shared writeback") {
945 // don't send writeback if replacing block with no tokens
946 assert (getCacheEntry(address).Tokens > 0);
947 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
948 out_msg.Address := address;
949 out_msg.Sender := machineID;
951 out_msg.Destination.add(mapAddressToRange(address,
954 l2_select_num_bits));
956 out_msg.Tokens := getCacheEntry(address).Tokens;
957 out_msg.DataBlk := getCacheEntry(address).DataBlk;
958 // assert(getCacheEntry(address).Dirty == false);
959 out_msg.Dirty := false;
961 out_msg.MessageSize := MessageSizeType:Writeback_Data;
962 out_msg.Type := CoherenceResponseType:WB_SHARED_DATA;
964 getCacheEntry(address).Tokens := 0;
967 action(tr_tokenReplacement, "tr", desc="Issue token writeback") {
968 if (getCacheEntry(address).Tokens > 0) {
969 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
970 out_msg.Address := address;
971 out_msg.Sender := machineID;
973 out_msg.Destination.add(mapAddressToRange(address,
976 l2_select_num_bits));
978 out_msg.Tokens := getCacheEntry(address).Tokens;
979 out_msg.DataBlk := getCacheEntry(address).DataBlk;
980 // assert(getCacheEntry(address).Dirty == false);
981 out_msg.Dirty := false;
983 // always send the data?
984 out_msg.MessageSize := MessageSizeType:Writeback_Control;
985 out_msg.Type := CoherenceResponseType:WB_TOKENS;
988 getCacheEntry(address).Tokens := 0;
992 action(d_sendDataWithToken, "d", desc="Send data and a token from cache to requestor") {
993 peek(requestNetwork_in, RequestMsg) {
994 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
995 out_msg.Address := address;
996 out_msg.Type := CoherenceResponseType:DATA_SHARED;
997 out_msg.Sender := machineID;
998 out_msg.Destination.add(in_msg.Requestor);
1000 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1001 // out_msg.Dirty := getCacheEntry(address).Dirty;
1002 out_msg.Dirty := false;
1003 if (in_msg.isLocal) {
1004 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1006 out_msg.MessageSize := MessageSizeType:Response_Data;
1010 getCacheEntry(address).Tokens := getCacheEntry(address).Tokens - 1;
1011 assert(getCacheEntry(address).Tokens >= 1);
1014 action(d_sendDataWithNTokenIfAvail, "\dd", desc="Send data and a token from cache to requestor") {
1015 peek(requestNetwork_in, RequestMsg) {
1016 if (getCacheEntry(address).Tokens > (N_tokens + (max_tokens() / 2))) {
1017 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1018 out_msg.Address := address;
1019 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1020 out_msg.Sender := machineID;
1021 out_msg.Destination.add(in_msg.Requestor);
1022 out_msg.Tokens := N_tokens;
1023 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1024 // out_msg.Dirty := getCacheEntry(address).Dirty;
1025 out_msg.Dirty := false;
1026 if (in_msg.isLocal) {
1027 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1029 out_msg.MessageSize := MessageSizeType:Response_Data;
1032 getCacheEntry(address).Tokens := getCacheEntry(address).Tokens - N_tokens;
1034 else if (getCacheEntry(address).Tokens > 1) {
1035 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1036 out_msg.Address := address;
1037 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1038 out_msg.Sender := machineID;
1039 out_msg.Destination.add(in_msg.Requestor);
1040 out_msg.Tokens := 1;
1041 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1042 // out_msg.Dirty := getCacheEntry(address).Dirty;
1043 out_msg.Dirty := false;
1044 if (in_msg.isLocal) {
1045 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1047 out_msg.MessageSize := MessageSizeType:Response_Data;
1050 getCacheEntry(address).Tokens := getCacheEntry(address).Tokens - 1;
1053 // assert(getCacheEntry(address).Tokens >= 1);
1056 action(dd_sendDataWithAllTokens, "\d", desc="Send data and all tokens from cache to requestor") {
1057 peek(requestNetwork_in, RequestMsg) {
1058 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1059 out_msg.Address := address;
1060 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1061 out_msg.Sender := machineID;
1062 out_msg.Destination.add(in_msg.Requestor);
1063 assert(getCacheEntry(address).Tokens > (max_tokens() / 2));
1064 out_msg.Tokens := getCacheEntry(address).Tokens;
1065 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1066 out_msg.Dirty := getCacheEntry(address).Dirty;
1067 if (in_msg.isLocal) {
1068 out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
1070 out_msg.MessageSize := MessageSizeType:Response_Data;
1074 getCacheEntry(address).Tokens := 0;
1077 action(e_sendAckWithCollectedTokens, "e", desc="Send ack with the tokens we've collected thus far.") {
1078 // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1079 if (getCacheEntry(address).Tokens > 0) {
1080 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1081 out_msg.Address := address;
1082 if (getCacheEntry(address).Tokens > (max_tokens() / 2)) {
1083 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1085 out_msg.Type := CoherenceResponseType:ACK;
1087 out_msg.Sender := machineID;
1088 out_msg.Destination.add(persistentTable.findSmallest(address));
1089 assert(getCacheEntry(address).Tokens >= 1);
1090 out_msg.Tokens := getCacheEntry(address).Tokens;
1091 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1092 out_msg.MessageSize := MessageSizeType:Response_Control;
1095 getCacheEntry(address).Tokens := 0;
1098 action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
1099 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1100 assert(getCacheEntry(address).Tokens > 0);
1101 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1102 out_msg.Address := address;
1103 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1104 out_msg.Sender := machineID;
1105 out_msg.Destination.add(persistentTable.findSmallest(address));
1106 assert(getCacheEntry(address).Tokens > (max_tokens() / 2));
1107 out_msg.Tokens := getCacheEntry(address).Tokens;
1108 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1109 out_msg.Dirty := getCacheEntry(address).Dirty;
1110 out_msg.MessageSize := MessageSizeType:Response_Data;
1112 getCacheEntry(address).Tokens := 0;
1115 action(f_sendAckWithAllButNorOneTokens, "f", desc="Send ack with all our tokens but one to starver.") {
1116 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1117 assert(getCacheEntry(address).Tokens > 0);
1118 if (getCacheEntry(address).Tokens > 1) {
1119 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1120 out_msg.Address := address;
1121 if (getCacheEntry(address).Tokens > (max_tokens() / 2)) {
1122 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1124 out_msg.Type := CoherenceResponseType:ACK;
1126 out_msg.Sender := machineID;
1127 out_msg.Destination.add(persistentTable.findSmallest(address));
1128 assert(getCacheEntry(address).Tokens >= 1);
1129 if (getCacheEntry(address).Tokens > N_tokens) {
1130 out_msg.Tokens := getCacheEntry(address).Tokens - N_tokens;
1132 out_msg.Tokens := getCacheEntry(address).Tokens - 1;
1134 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1135 out_msg.MessageSize := MessageSizeType:Response_Control;
1138 if (getCacheEntry(address).Tokens > N_tokens) {
1139 getCacheEntry(address).Tokens := N_tokens;
1141 getCacheEntry(address).Tokens := 1;
1145 action(ff_sendDataWithAllButNorOneTokens, "\f", desc="Send data and out tokens but one to starver") {
1146 //assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1147 assert(getCacheEntry(address).Tokens > ((max_tokens() / 2) + 1));
1148 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1149 out_msg.Address := address;
1150 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1151 out_msg.Sender := machineID;
1152 out_msg.Destination.add(persistentTable.findSmallest(address));
1153 if (getCacheEntry(address).Tokens > (N_tokens + (max_tokens() / 2))) {
1154 out_msg.Tokens := getCacheEntry(address).Tokens - N_tokens;
1156 out_msg.Tokens := getCacheEntry(address).Tokens - 1;
1158 assert(out_msg.Tokens > (max_tokens() / 2));
1159 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1160 out_msg.Dirty := getCacheEntry(address).Dirty;
1161 out_msg.MessageSize := MessageSizeType:Response_Data;
1163 if (getCacheEntry(address).Tokens > (N_tokens + (max_tokens() / 2))) {
1164 getCacheEntry(address).Tokens := N_tokens;
1166 getCacheEntry(address).Tokens := 1;
1170 action(fo_sendDataWithOwnerToken, "fo", desc="Send data and owner tokens") {
1171 assert(getCacheEntry(address).Tokens == ((max_tokens() / 2) + 1));
1172 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1173 out_msg.Address := address;
1174 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1175 out_msg.Sender := machineID;
1176 out_msg.Destination.add(persistentTable.findSmallest(address));
1177 out_msg.Tokens := getCacheEntry(address).Tokens;
1178 assert(out_msg.Tokens > (max_tokens() / 2));
1179 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1180 out_msg.Dirty := getCacheEntry(address).Dirty;
1181 out_msg.MessageSize := MessageSizeType:Response_Data;
1183 getCacheEntry(address).Tokens := 0;
1186 action(g_bounceResponseToStarver, "g", desc="Redirect response to starving processor") {
1187 // assert(persistentTable.isLocked(address));
1189 peek(responseNetwork_in, ResponseMsg) {
1190 // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
1191 // FIXME, should use a 3rd vnet in some cases
1192 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
1193 out_msg.Address := address;
1194 out_msg.Type := in_msg.Type;
1195 out_msg.Sender := machineID;
1196 out_msg.Destination.add(persistentTable.findSmallest(address));
1197 out_msg.Tokens := in_msg.Tokens;
1198 out_msg.DataBlk := in_msg.DataBlk;
1199 out_msg.Dirty := in_msg.Dirty;
1200 out_msg.MessageSize := in_msg.MessageSize;
1206 action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
1207 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1208 address, getCacheEntry(address).DataBlk);
1210 sequencer.readCallback(address,
1211 GenericMachineType:L1Cache,
1212 getCacheEntry(address).DataBlk);
1216 action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
1217 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1218 address, getCacheEntry(address).DataBlk);
1219 peek(responseNetwork_in, ResponseMsg) {
1221 sequencer.readCallback(address,
1222 getNondirectHitMachType(address, in_msg.Sender),
1223 getCacheEntry(address).DataBlk);
1228 action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
1229 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1230 address, getCacheEntry(address).DataBlk);
1232 sequencer.writeCallback(address,
1233 GenericMachineType:L1Cache,
1234 getCacheEntry(address).DataBlk);
1236 getCacheEntry(address).Dirty := true;
1237 DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
1240 action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
1241 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1242 address, getCacheEntry(address).DataBlk);
1243 peek(responseNetwork_in, ResponseMsg) {
1245 sequencer.writeCallback(address,
1246 getNondirectHitMachType(address, in_msg.Sender),
1247 getCacheEntry(address).DataBlk);
1250 getCacheEntry(address).Dirty := true;
1251 DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
1254 action(i_allocateTBE, "i", desc="Allocate TBE") {
1255 check_allocate(L1_TBEs);
1256 L1_TBEs.allocate(address);
1257 L1_TBEs[address].IssueCount := 0;
1258 peek(mandatoryQueue_in, CacheMsg) {
1259 L1_TBEs[address].PC := in_msg.ProgramCounter;
1260 L1_TBEs[address].AccessType := cache_request_type_to_access_type(in_msg.Type);
1261 if (in_msg.Type == CacheRequestType:ATOMIC) {
1262 L1_TBEs[address].IsAtomic := true;
1264 L1_TBEs[address].Prefetch := in_msg.Prefetch;
1265 L1_TBEs[address].AccessMode := in_msg.AccessMode;
1267 L1_TBEs[address].IssueTime := get_time();
1271 action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
1272 if (reissueTimerTable.isSet(address)) {
1273 reissueTimerTable.unset(address);
1277 action(jj_unsetUseTimer, "\j", desc="Unset use timer.") {
1278 useTimerTable.unset(address);
1281 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
1282 mandatoryQueue_in.dequeue();
1285 action(l_popPersistentQueue, "l", desc="Pop persistent queue.") {
1286 persistentNetwork_in.dequeue();
1289 action(m_popRequestQueue, "m", desc="Pop request queue.") {
1290 requestNetwork_in.dequeue();
1293 action(n_popResponseQueue, "n", desc="Pop response queue") {
1294 responseNetwork_in.dequeue();
1297 action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") {
1298 useTimerTable.set(address, 50);
1301 action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
1302 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1303 out_msg.Address := address;
1304 out_msg.Type := CoherenceResponseType:INV;
1305 out_msg.Tokens := 0;
1306 out_msg.Sender := machineID;
1308 out_msg.Destination.add(mapAddressToRange(address,
1309 MachineType:L2Cache,
1311 l2_select_num_bits));
1313 out_msg.MessageSize := MessageSizeType:Response_Control;
1318 action(q_updateTokensFromResponse, "q", desc="Update the token count based on the incoming response message") {
1319 peek(responseNetwork_in, ResponseMsg) {
1320 assert(in_msg.Tokens != 0);
1321 DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
1322 in_msg.Address, in_msg.Tokens);
1323 getCacheEntry(address).Tokens := getCacheEntry(address).Tokens + in_msg.Tokens;
1324 DPRINTF(RubySlicc, "%d\n", getCacheEntry(address).Tokens);
1326 if (getCacheEntry(address).Dirty == false && in_msg.Dirty) {
1327 getCacheEntry(address).Dirty := true;
1332 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1334 if (L1_TBEs[address].WentPersistent) {
1335 // assert(starving == true);
1336 outstandingRequests := outstandingRequests - 1;
1337 enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
1338 out_msg.Address := address;
1339 out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
1340 out_msg.Requestor := machineID;
1341 out_msg.Destination.broadcast(MachineType:L1Cache);
1344 // Currently the configuration system limits the system to only one
1345 // chip. Therefore, if we assume one shared L2 cache, then only one
1346 // pertinent L2 cache exist.
1348 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
1350 out_msg.Destination.add(mapAddressToRange(address,
1351 MachineType:L2Cache,
1353 l2_select_num_bits));
1355 out_msg.Destination.add(map_Address_to_Directory(address));
1356 out_msg.MessageSize := MessageSizeType:Persistent_Control;
1361 // Update average latency
1362 if (L1_TBEs[address].IssueCount <= 1) {
1363 if (L1_TBEs[address].ExternalResponse == true) {
1364 updateAverageLatencyEstimate(time_to_int(get_time()) - time_to_int(L1_TBEs[address].IssueTime));
1369 //if (L1_TBEs[address].WentPersistent) {
1370 // profile_token_retry(address, L1_TBEs[address].AccessType, 2);
1373 // profile_token_retry(address, L1_TBEs[address].AccessType, 1);
1376 //profile_token_retry(address, L1_TBEs[address].AccessType, L1_TBEs[address].IssueCount);
1377 L1_TBEs.deallocate(address);
1380 action(t_sendAckWithCollectedTokens, "t", desc="Send ack with the tokens we've collected thus far.") {
1381 if (getCacheEntry(address).Tokens > 0) {
1382 peek(requestNetwork_in, RequestMsg) {
1383 enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
1384 out_msg.Address := address;
1385 if (getCacheEntry(address).Tokens > (max_tokens() / 2)) {
1386 out_msg.Type := CoherenceResponseType:DATA_OWNER;
1388 out_msg.Type := CoherenceResponseType:ACK;
1390 out_msg.Sender := machineID;
1391 out_msg.Destination.add(in_msg.Requestor);
1392 assert(getCacheEntry(address).Tokens >= 1);
1393 out_msg.Tokens := getCacheEntry(address).Tokens;
1394 out_msg.DataBlk := getCacheEntry(address).DataBlk;
1395 out_msg.MessageSize := MessageSizeType:Response_Control;
1399 getCacheEntry(address).Tokens := 0;
1402 action(u_writeDataToCache, "u", desc="Write data to cache") {
1403 peek(responseNetwork_in, ResponseMsg) {
1404 getCacheEntry(address).DataBlk := in_msg.DataBlk;
1405 if (getCacheEntry(address).Dirty == false && in_msg.Dirty) {
1406 getCacheEntry(address).Dirty := in_msg.Dirty;
1412 action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1413 assert(getTokens(address) == 0);
1414 if (L1DcacheMemory.isTagPresent(address)) {
1415 L1DcacheMemory.deallocate(address);
1417 L1IcacheMemory.deallocate(address);
1421 action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1422 if (L1DcacheMemory.isTagPresent(address) == false) {
1423 L1DcacheMemory.allocate(address, new Entry);
1427 action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
1428 if (L1IcacheMemory.isTagPresent(address) == false) {
1429 L1IcacheMemory.allocate(address, new Entry);
1433 action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1434 peek(mandatoryQueue_in, CacheMsg) {
1435 if (L1DcacheMemory.isTagPresent(address)) {
1436 L1DcacheMemory.profileMiss(in_msg);
1438 L1IcacheMemory.profileMiss(in_msg);
1443 action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
1444 peek(responseNetwork_in, ResponseMsg) {
1445 assert(getCacheEntry(address).DataBlk == in_msg.DataBlk);
1449 action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1450 mandatoryQueue_in.recycle();
1453 //*****************************************************
1455 //*****************************************************
1457 // Transitions for Load/Store/L2_Replacement from transient states
1458 transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
1459 zz_recycleMandatoryQueue;
1462 transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
1463 zz_recycleMandatoryQueue;
1466 transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
1467 zz_recycleMandatoryQueue;
1472 transition({NP, I, S, O, M, MM, M_W, MM_W, IM, SM, OM, IS}, Own_Lock_or_Unlock) {
1473 l_popPersistentQueue;
1476 // Transitions from NP
1477 transition(NP, Load, IS) {
1478 ii_allocateL1DCacheBlock;
1482 k_popMandatoryQueue;
1485 transition(NP, Ifetch, IS) {
1486 pp_allocateL1ICacheBlock;
1490 k_popMandatoryQueue;
1493 transition(NP, {Store, Atomic}, IM) {
1494 ii_allocateL1DCacheBlock;
1496 b_issueWriteRequest;
1498 k_popMandatoryQueue;
1501 transition(NP, {Ack, Data_Shared, Data_Owner, Data_All_Tokens}) {
1506 transition(NP, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) {
1510 transition(NP, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1511 l_popPersistentQueue;
1514 // Transitions from Idle
1515 transition(I, Load, IS) {
1519 k_popMandatoryQueue;
1522 transition(I, Ifetch, IS) {
1526 k_popMandatoryQueue;
1529 transition(I, {Store, Atomic}, IM) {
1531 b_issueWriteRequest;
1533 k_popMandatoryQueue;
1536 transition(I, L1_Replacement) {
1537 tr_tokenReplacement;
1538 gg_deallocateL1CacheBlock;
1541 transition(I, {Transient_GETX, Transient_Local_GETX}) {
1542 t_sendAckWithCollectedTokens;
1546 transition(I, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1550 transition(I, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, I_L) {
1551 e_sendAckWithCollectedTokens;
1552 l_popPersistentQueue;
1555 transition(I_L, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}) {
1556 l_popPersistentQueue;
1559 transition(I, Ack) {
1560 q_updateTokensFromResponse;
1564 transition(I, Data_Shared, S) {
1566 q_updateTokensFromResponse;
1570 transition(I, Data_Owner, O) {
1572 q_updateTokensFromResponse;
1576 transition(I, Data_All_Tokens, M) {
1578 q_updateTokensFromResponse;
1582 // Transitions from Shared
1583 transition({S, SM, S_L, SM_L}, {Load, Ifetch}) {
1585 k_popMandatoryQueue;
1588 transition(S, {Store, Atomic}, SM) {
1590 b_issueWriteRequest;
1592 k_popMandatoryQueue;
1595 transition(S, L1_Replacement, I) {
1596 cc_sharedReplacement; // Only needed in some cases
1597 gg_deallocateL1CacheBlock;
1600 transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
1601 t_sendAckWithCollectedTokens;
1602 p_informL2AboutTokenLoss;
1606 // only owner responds to non-local requests
1607 transition(S, Transient_GETS) {
1611 transition(S, Transient_Local_GETS) {
1612 d_sendDataWithToken;
1616 transition(S, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1620 transition({S, S_L}, Persistent_GETX, I_L) {
1621 e_sendAckWithCollectedTokens;
1622 p_informL2AboutTokenLoss;
1623 l_popPersistentQueue;
1626 transition(S, {Persistent_GETS, Persistent_GETS_Last_Token}, S_L) {
1627 f_sendAckWithAllButNorOneTokens;
1628 l_popPersistentQueue;
1631 transition(S_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1632 l_popPersistentQueue;
1635 transition(S, Ack) {
1636 q_updateTokensFromResponse;
1640 transition(S, Data_Shared) {
1641 w_assertIncomingDataAndCacheDataMatch;
1642 q_updateTokensFromResponse;
1646 transition(S, Data_Owner, O) {
1647 w_assertIncomingDataAndCacheDataMatch;
1648 q_updateTokensFromResponse;
1652 transition(S, Data_All_Tokens, M) {
1653 w_assertIncomingDataAndCacheDataMatch;
1654 q_updateTokensFromResponse;
1658 // Transitions from Owned
1659 transition({O, OM}, {Load, Ifetch}) {
1661 k_popMandatoryQueue;
1664 transition(O, {Store, Atomic}, OM) {
1666 b_issueWriteRequest;
1668 k_popMandatoryQueue;
1671 transition(O, L1_Replacement, I) {
1673 gg_deallocateL1CacheBlock;
1676 transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
1677 dd_sendDataWithAllTokens;
1678 p_informL2AboutTokenLoss;
1682 transition(O, Persistent_GETX, I_L) {
1683 ee_sendDataWithAllTokens;
1684 p_informL2AboutTokenLoss;
1685 l_popPersistentQueue;
1688 transition(O, Persistent_GETS, S_L) {
1689 ff_sendDataWithAllButNorOneTokens;
1690 l_popPersistentQueue;
1693 transition(O, Persistent_GETS_Last_Token, I_L) {
1694 fo_sendDataWithOwnerToken;
1695 l_popPersistentQueue;
1698 transition(O, Transient_GETS) {
1699 d_sendDataWithToken;
1703 transition(O, Transient_Local_GETS) {
1704 d_sendDataWithToken;
1708 // ran out of tokens, wait for it to go persistent
1709 transition(O, {Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token}) {
1713 transition(O, Ack) {
1714 q_updateTokensFromResponse;
1718 transition(O, Ack_All_Tokens, M) {
1719 q_updateTokensFromResponse;
1723 transition(O, Data_Shared) {
1724 w_assertIncomingDataAndCacheDataMatch;
1725 q_updateTokensFromResponse;
1729 transition(O, Data_All_Tokens, M) {
1730 w_assertIncomingDataAndCacheDataMatch;
1731 q_updateTokensFromResponse;
1735 // Transitions from Modified
1736 transition({MM, MM_W}, {Load, Ifetch}) {
1738 k_popMandatoryQueue;
1741 transition({MM_W}, {Store, Atomic}) {
1743 k_popMandatoryQueue;
1746 transition(MM, Store) {
1748 k_popMandatoryQueue;
1751 transition(MM, Atomic, M) {
1753 k_popMandatoryQueue;
1756 transition(MM, L1_Replacement, I) {
1758 gg_deallocateL1CacheBlock;
1761 transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
1762 dd_sendDataWithAllTokens;
1763 p_informL2AboutTokenLoss;
1767 transition({MM_W}, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1771 // Implement the migratory sharing optimization, even for persistent requests
1772 transition(MM, {Persistent_GETX, Persistent_GETS}, I_L) {
1773 ee_sendDataWithAllTokens;
1774 p_informL2AboutTokenLoss;
1775 l_popPersistentQueue;
1778 // ignore persistent requests in lockout period
1779 transition(MM_W, {Persistent_GETX, Persistent_GETS}) {
1780 l_popPersistentQueue;
1783 transition(MM_W, Use_TimeoutNoStarvers, MM) {
1788 transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
1793 // Transitions from Dirty Exclusive
1794 transition({M, M_W}, {Load, Ifetch}) {
1796 k_popMandatoryQueue;
1799 transition(M, Store, MM) {
1801 k_popMandatoryQueue;
1804 transition(M, Atomic) {
1806 k_popMandatoryQueue;
1809 transition(M_W, Store, MM_W) {
1811 k_popMandatoryQueue;
1814 transition(M_W, Atomic) {
1816 k_popMandatoryQueue;
1819 transition(M, L1_Replacement, I) {
1821 gg_deallocateL1CacheBlock;
1824 transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
1825 dd_sendDataWithAllTokens;
1826 p_informL2AboutTokenLoss;
1830 transition(M, Transient_Local_GETS, O) {
1831 d_sendDataWithToken;
1835 transition(M, Transient_GETS, O) {
1836 d_sendDataWithNTokenIfAvail;
1840 transition(M_W, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}) { // Ignore the request
1844 transition(M, Persistent_GETX, I_L) {
1845 ee_sendDataWithAllTokens;
1846 p_informL2AboutTokenLoss;
1847 l_popPersistentQueue;
1850 transition(M, Persistent_GETS, S_L) {
1851 ff_sendDataWithAllButNorOneTokens;
1852 l_popPersistentQueue;
1855 // ignore persistent requests in lockout period
1856 transition(M_W, {Persistent_GETX, Persistent_GETS}) {
1857 l_popPersistentQueue;
1860 transition(M_W, Use_TimeoutStarverS, S_L) {
1862 ff_sendDataWithAllButNorOneTokens;
1866 // someone unlocked during timeout
1867 transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
1872 transition(M_W, Use_TimeoutStarverX, I_L) {
1874 ee_sendDataWithAllTokens;
1875 p_informL2AboutTokenLoss;
1882 transition(MM_W, {Use_TimeoutStarverX, Use_TimeoutStarverS}, I_L) {
1884 ee_sendDataWithAllTokens;
1885 p_informL2AboutTokenLoss;
1891 // Transient_GETX and Transient_GETS in transient states
1892 transition(OM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1893 m_popRequestQueue; // Even if we have the data, we can pretend we don't have it yet.
1896 transition(IS, {Transient_GETX, Transient_Local_GETX}) {
1897 t_sendAckWithCollectedTokens;
1901 transition(IS, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
1905 transition(IS, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IS_L) {
1906 e_sendAckWithCollectedTokens;
1907 l_popPersistentQueue;
1910 transition(IS_L, {Persistent_GETX, Persistent_GETS}) {
1911 l_popPersistentQueue;
1914 transition(IM, {Persistent_GETX, Persistent_GETS, Persistent_GETS_Last_Token}, IM_L) {
1915 e_sendAckWithCollectedTokens;
1916 l_popPersistentQueue;
1919 transition(IM_L, {Persistent_GETX, Persistent_GETS}) {
1920 l_popPersistentQueue;
1923 transition({SM, SM_L}, Persistent_GETX, IM_L) {
1924 e_sendAckWithCollectedTokens;
1925 l_popPersistentQueue;
1928 transition(SM, {Persistent_GETS, Persistent_GETS_Last_Token}, SM_L) {
1929 f_sendAckWithAllButNorOneTokens;
1930 l_popPersistentQueue;
1933 transition(SM_L, {Persistent_GETS, Persistent_GETS_Last_Token}) {
1934 l_popPersistentQueue;
1937 transition(OM, Persistent_GETX, IM_L) {
1938 ee_sendDataWithAllTokens;
1939 l_popPersistentQueue;
1942 transition(OM, Persistent_GETS, SM_L) {
1943 ff_sendDataWithAllButNorOneTokens;
1944 l_popPersistentQueue;
1947 transition(OM, Persistent_GETS_Last_Token, IM_L) {
1948 fo_sendDataWithOwnerToken;
1949 l_popPersistentQueue;
1952 // Transitions from IM/SM
1954 transition({IM, SM}, Ack) {
1955 q_updateTokensFromResponse;
1959 transition(IM, Data_Shared, SM) {
1961 q_updateTokensFromResponse;
1965 transition(IM, Data_Owner, OM) {
1967 q_updateTokensFromResponse;
1971 transition(IM, Data_All_Tokens, MM_W) {
1973 q_updateTokensFromResponse;
1974 xx_external_store_hit;
1975 o_scheduleUseTimeout;
1976 j_unsetReissueTimer;
1980 transition(SM, Data_Shared) {
1981 w_assertIncomingDataAndCacheDataMatch;
1982 q_updateTokensFromResponse;
1986 transition(SM, Data_Owner, OM) {
1987 w_assertIncomingDataAndCacheDataMatch;
1988 q_updateTokensFromResponse;
1992 transition(SM, Data_All_Tokens, MM_W) {
1993 w_assertIncomingDataAndCacheDataMatch;
1994 q_updateTokensFromResponse;
1995 xx_external_store_hit;
1996 o_scheduleUseTimeout;
1997 j_unsetReissueTimer;
2001 transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens. We give them up here to avoid livelock
2002 t_sendAckWithCollectedTokens;
2006 transition({IM, SM}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS}) {
2010 transition({IM, SM}, Request_Timeout) {
2011 j_unsetReissueTimer;
2012 b_issueWriteRequest;
2015 // Transitions from OM
2017 transition(OM, Ack) {
2018 q_updateTokensFromResponse;
2022 transition(OM, Ack_All_Tokens, MM_W) {
2023 q_updateTokensFromResponse;
2024 xx_external_store_hit;
2025 o_scheduleUseTimeout;
2026 j_unsetReissueTimer;
2030 transition(OM, Data_Shared) {
2031 w_assertIncomingDataAndCacheDataMatch;
2032 q_updateTokensFromResponse;
2036 transition(OM, Data_All_Tokens, MM_W) {
2037 w_assertIncomingDataAndCacheDataMatch;
2038 q_updateTokensFromResponse;
2039 xx_external_store_hit;
2040 o_scheduleUseTimeout;
2041 j_unsetReissueTimer;
2045 transition(OM, Request_Timeout) {
2046 j_unsetReissueTimer;
2047 b_issueWriteRequest;
2050 // Transitions from IS
2052 transition(IS, Ack) {
2053 q_updateTokensFromResponse;
2057 transition(IS, Data_Shared, S) {
2059 q_updateTokensFromResponse;
2060 x_external_load_hit;
2062 j_unsetReissueTimer;
2066 transition(IS, Data_Owner, O) {
2068 q_updateTokensFromResponse;
2069 x_external_load_hit;
2071 j_unsetReissueTimer;
2075 transition(IS, Data_All_Tokens, M_W) {
2077 q_updateTokensFromResponse;
2078 x_external_load_hit;
2079 o_scheduleUseTimeout;
2080 j_unsetReissueTimer;
2084 transition(IS, Request_Timeout) {
2085 j_unsetReissueTimer;
2089 // Transitions from I_L
2091 transition(I_L, Load, IS_L) {
2092 ii_allocateL1DCacheBlock;
2096 k_popMandatoryQueue;
2099 transition(I_L, Ifetch, IS_L) {
2100 pp_allocateL1ICacheBlock;
2104 k_popMandatoryQueue;
2107 transition(I_L, {Store, Atomic}, IM_L) {
2108 ii_allocateL1DCacheBlock;
2110 b_issueWriteRequest;
2112 k_popMandatoryQueue;
2116 // Transitions from S_L
2118 transition(S_L, {Store, Atomic}, SM_L) {
2120 b_issueWriteRequest;
2122 k_popMandatoryQueue;
2125 // Other transitions from *_L states
2127 transition({I_L, IM_L, IS_L, S_L, SM_L}, {Transient_GETS, Transient_GETS_Last_Token, Transient_Local_GETS_Last_Token, Transient_Local_GETS, Transient_GETX, Transient_Local_GETX}) {
2131 transition({I_L, IM_L, IS_L, S_L, SM_L}, Ack) {
2132 g_bounceResponseToStarver;
2136 transition({I_L, IM_L, S_L, SM_L}, {Data_Shared, Data_Owner}) {
2137 g_bounceResponseToStarver;
2141 transition({I_L, S_L}, Data_All_Tokens) {
2142 g_bounceResponseToStarver;
2146 transition(IS_L, Request_Timeout) {
2147 j_unsetReissueTimer;
2151 transition({IM_L, SM_L}, Request_Timeout) {
2152 j_unsetReissueTimer;
2153 b_issueWriteRequest;
2156 // Opportunisticly Complete the memory operation in the following
2157 // cases. Note: these transitions could just use
2158 // g_bounceResponseToStarver, but if we have the data and tokens, we
2159 // might as well complete the memory request while we have the
2160 // chance (and then immediately forward on the data)
2162 transition(IM_L, Data_All_Tokens, MM_W) {
2164 q_updateTokensFromResponse;
2165 xx_external_store_hit;
2166 j_unsetReissueTimer;
2167 o_scheduleUseTimeout;
2171 transition(SM_L, Data_All_Tokens, S_L) {
2173 q_updateTokensFromResponse;
2174 xx_external_store_hit;
2175 ff_sendDataWithAllButNorOneTokens;
2177 j_unsetReissueTimer;
2181 transition(IS_L, Data_Shared, I_L) {
2183 q_updateTokensFromResponse;
2184 x_external_load_hit;
2186 e_sendAckWithCollectedTokens;
2187 p_informL2AboutTokenLoss;
2188 j_unsetReissueTimer;
2192 transition(IS_L, Data_Owner, I_L) {
2194 q_updateTokensFromResponse;
2195 x_external_load_hit;
2196 ee_sendDataWithAllTokens;
2198 p_informL2AboutTokenLoss;
2199 j_unsetReissueTimer;
2203 transition(IS_L, Data_All_Tokens, M_W) {
2205 q_updateTokensFromResponse;
2206 x_external_load_hit;
2207 j_unsetReissueTimer;
2208 o_scheduleUseTimeout;
2213 // Own_Lock_or_Unlock
2215 transition(I_L, Own_Lock_or_Unlock, I) {
2216 l_popPersistentQueue;
2219 transition(S_L, Own_Lock_or_Unlock, S) {
2220 l_popPersistentQueue;
2223 transition(IM_L, Own_Lock_or_Unlock, IM) {
2224 l_popPersistentQueue;
2227 transition(IS_L, Own_Lock_or_Unlock, IS) {
2228 l_popPersistentQueue;
2231 transition(SM_L, Own_Lock_or_Unlock, SM) {
2232 l_popPersistentQueue;