3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 machine(Directory, "Token protocol")
36 : DirectoryMemory * directory,
37 MemoryControl * memBuffer,
38 int l2_select_num_bits,
39 int directory_latency = 5,
40 bool distributed_persistent = true,
41 int fixed_timeout_latency = 100
44 MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true";
45 MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false";
46 MessageBuffer persistentFromDir, network="To", virtual_network="3", ordered="true";
47 MessageBuffer requestFromDir, network="To", virtual_network="1", ordered="false";
49 MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false";
50 MessageBuffer persistentToDir, network="From", virtual_network="3", ordered="true";
51 MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
52 MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true";
55 state_declaration(State, desc="Directory states", default="Directory_State_O") {
57 O, AccessPermission:Read_Only, desc="Owner, memory has valid data, but not necessarily all the tokens";
58 NO, AccessPermission:Invalid, desc="Not Owner";
59 L, AccessPermission:Busy, desc="Locked";
61 // Memory wait states - can block all messages including persistent requests
62 O_W, AccessPermission:Busy, desc="transitioning to Owner, waiting for memory write";
63 L_O_W, AccessPermission:Busy, desc="transitioning to Locked, waiting for memory read, could eventually return to O";
64 L_NO_W, AccessPermission:Busy, desc="transitioning to Locked, waiting for memory read, eventually return to NO";
65 DR_L_W, AccessPermission:Busy, desc="transitioning to Locked underneath a DMA read, waiting for memory data";
66 DW_L_W, AccessPermission:Busy, desc="transitioning to Locked underneath a DMA write, waiting for memory ack";
67 NO_W, AccessPermission:Busy, desc="transitioning to Not Owner, waiting for memory read";
68 O_DW_W, AccessPermission:Busy, desc="transitioning to Owner, waiting for memory before DMA ack";
69 O_DR_W, AccessPermission:Busy, desc="transitioning to Owner, waiting for memory before DMA data";
71 // DMA request transient states - must respond to persistent requests
72 O_DW, AccessPermission:Busy, desc="issued GETX for DMA write, waiting for all tokens";
73 NO_DW, AccessPermission:Busy, desc="issued GETX for DMA write, waiting for all tokens";
74 NO_DR, AccessPermission:Busy, desc="issued GETS for DMA read, waiting for data";
76 // DMA request in progress - competing with a CPU persistent request
77 DW_L, AccessPermission:Busy, desc="issued GETX for DMA write, CPU persistent request must complete first";
78 DR_L, AccessPermission:Busy, desc="issued GETS for DMA read, CPU persistent request must complete first";
83 enumeration(Event, desc="Directory events") {
84 GETX, desc="A GETX arrives";
85 GETS, desc="A GETS arrives";
86 Lockdown, desc="A lockdown request arrives";
87 Unlockdown, desc="An un-lockdown request arrives";
88 Own_Lock_or_Unlock, desc="own lock or unlock";
89 Own_Lock_or_Unlock_Tokens, desc="own lock or unlock with tokens";
90 Data_Owner, desc="Data arrive";
91 Data_All_Tokens, desc="Data and all tokens";
92 Ack_Owner, desc="Owner token arrived without data because it was clean";
93 Ack_Owner_All_Tokens, desc="All tokens including owner arrived without data because it was clean";
94 Tokens, desc="Tokens arrive";
95 Ack_All_Tokens, desc="All_Tokens arrive";
96 Request_Timeout, desc="A DMA request has timed out";
99 Memory_Data, desc="Fetched data from memory arrives";
100 Memory_Ack, desc="Writeback Ack from memory arrives";
103 DMA_READ, desc="A DMA Read memory request";
104 DMA_WRITE, desc="A DMA Write memory request";
105 DMA_WRITE_All_Tokens, desc="A DMA Write memory request, directory has all tokens";
111 structure(Entry, desc="...", interface="AbstractEntry") {
112 State DirectoryState, desc="Directory state";
113 DataBlock DataBlk, desc="data for the block";
114 int Tokens, default="max_tokens()", desc="Number of tokens for the line we're holding";
116 // The following state is provided to allow for bandwidth
117 // efficient directory-like operation. However all of this state
118 // is 'soft state' that does not need to be correct (as long as
119 // you're eventually willing to resort to broadcast.)
121 Set Owner, desc="Probable Owner of the line. More accurately, the set of processors who need to see a GetS or GetO. We use a Set for convenience, but only one bit is set at a time.";
122 Set Sharers, desc="Probable sharers of the line. More accurately, the set of processors who need to see a GetX";
125 external_type(PersistentTable) {
126 void persistentRequestLock(Address, MachineID, AccessType);
127 void persistentRequestUnlock(Address, MachineID);
128 bool okToIssueStarving(Address, MachineID);
129 MachineID findSmallest(Address);
130 AccessType typeOfSmallest(Address);
131 void markEntries(Address);
132 bool isLocked(Address);
133 int countStarvingForAddress(Address);
134 int countReadStarvingForAddress(Address);
137 // TBE entries for DMA requests
138 structure(TBE, desc="TBE entries for outstanding DMA requests") {
139 Address PhysicalAddress, desc="physical address";
140 State TBEState, desc="Transient State";
141 DataBlock DmaDataBlk, desc="DMA Data to be written. Partial blocks need to merged with system memory";
142 DataBlock DataBlk, desc="The current view of system memory";
144 MachineID DmaRequestor, desc="DMA requestor";
145 bool WentPersistent, desc="Did the DMA request require a persistent request";
148 external_type(TBETable) {
150 void allocate(Address);
151 void deallocate(Address);
152 bool isPresent(Address);
157 PersistentTable persistentTable;
158 TimerTable reissueTimerTable;
160 TBETable TBEs, template_hack="<Directory_TBE>";
162 bool starving, default="false";
163 int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
168 Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
169 return static_cast(Entry, directory[addr]);
172 State getState(TBE tbe, Address addr) {
176 return getDirectoryEntry(addr).DirectoryState;
180 void setState(TBE tbe, Address addr, State state) {
182 tbe.TBEState := state;
184 getDirectoryEntry(addr).DirectoryState := state;
186 if (state == State:L || state == State:DW_L || state == State:DR_L) {
187 assert(getDirectoryEntry(addr).Tokens == 0);
190 // We have one or zero owners
191 assert((getDirectoryEntry(addr).Owner.count() == 0) || (getDirectoryEntry(addr).Owner.count() == 1));
193 // Make sure the token count is in range
194 assert(getDirectoryEntry(addr).Tokens >= 0);
195 assert(getDirectoryEntry(addr).Tokens <= max_tokens());
197 if (state == State:O || state == State:O_W || state == State:O_DW) {
198 assert(getDirectoryEntry(addr).Tokens >= 1); // Must have at least one token
199 // assert(getDirectoryEntry(addr).Tokens >= (max_tokens() / 2)); // Only mostly true; this might not always hold
203 bool okToIssueStarving(Address addr, MachineID machinID) {
204 return persistentTable.okToIssueStarving(addr, machineID);
207 void markPersistentEntries(Address addr) {
208 persistentTable.markEntries(addr);
212 out_port(responseNetwork_out, ResponseMsg, responseFromDir);
213 out_port(persistentNetwork_out, PersistentMsg, persistentFromDir);
214 out_port(requestNetwork_out, RequestMsg, requestFromDir);
215 out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
218 // Memory buffer for memory controller to DIMM communication
220 out_port(memQueue_out, MemoryMsg, memBuffer);
224 // off-chip memory request/response is done
225 in_port(memQueue_in, MemoryMsg, memBuffer) {
226 if (memQueue_in.isReady()) {
227 peek(memQueue_in, MemoryMsg) {
228 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
229 trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
230 } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
231 trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
233 DPRINTF(RubySlicc, "%s\n", in_msg.Type);
234 error("Invalid message");
241 in_port(reissueTimerTable_in, Address, reissueTimerTable) {
242 if (reissueTimerTable_in.isReady()) {
243 trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
244 TBEs[reissueTimerTable.readyAddress()]);
248 in_port(responseNetwork_in, ResponseMsg, responseToDir) {
249 if (responseNetwork_in.isReady()) {
250 peek(responseNetwork_in, ResponseMsg) {
251 assert(in_msg.Destination.isElement(machineID));
252 if (getDirectoryEntry(in_msg.Address).Tokens + in_msg.Tokens == max_tokens()) {
253 if ((in_msg.Type == CoherenceResponseType:DATA_OWNER) ||
254 (in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
255 trigger(Event:Data_All_Tokens, in_msg.Address,
256 TBEs[in_msg.Address]);
257 } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
258 trigger(Event:Ack_Owner_All_Tokens, in_msg.Address,
259 TBEs[in_msg.Address]);
260 } else if (in_msg.Type == CoherenceResponseType:ACK) {
261 trigger(Event:Ack_All_Tokens, in_msg.Address,
262 TBEs[in_msg.Address]);
264 DPRINTF(RubySlicc, "%s\n", in_msg.Type);
265 error("Invalid message");
268 if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
269 trigger(Event:Data_Owner, in_msg.Address,
270 TBEs[in_msg.Address]);
271 } else if ((in_msg.Type == CoherenceResponseType:ACK) ||
272 (in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
273 trigger(Event:Tokens, in_msg.Address,
274 TBEs[in_msg.Address]);
275 } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
276 trigger(Event:Ack_Owner, in_msg.Address,
277 TBEs[in_msg.Address]);
279 DPRINTF(RubySlicc, "%s\n", in_msg.Type);
280 error("Invalid message");
287 in_port(persistentNetwork_in, PersistentMsg, persistentToDir) {
288 if (persistentNetwork_in.isReady()) {
289 peek(persistentNetwork_in, PersistentMsg) {
290 assert(in_msg.Destination.isElement(machineID));
292 if (distributed_persistent) {
293 // Apply the lockdown or unlockdown message to the table
294 if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
295 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
296 } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
297 persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
298 } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
299 persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
301 error("Invalid message");
304 // React to the message based on the current state of the table
305 if (persistentTable.isLocked(in_msg.Address)) {
306 if (persistentTable.findSmallest(in_msg.Address) == machineID) {
307 if (getDirectoryEntry(in_msg.Address).Tokens > 0) {
308 trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Address,
309 TBEs[in_msg.Address]);
311 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
312 TBEs[in_msg.Address]);
316 trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
320 trigger(Event:Unlockdown, in_msg.Address, TBEs[in_msg.Address]);
324 if (persistentTable.findSmallest(in_msg.Address) == machineID) {
325 if (getDirectoryEntry(in_msg.Address).Tokens > 0) {
326 trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Address,
327 TBEs[in_msg.Address]);
329 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
330 TBEs[in_msg.Address]);
332 } else if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
334 trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
335 } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
337 trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
338 } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
340 trigger(Event:Unlockdown, in_msg.Address, TBEs[in_msg.Address]);
342 error("Invalid message");
349 in_port(requestNetwork_in, RequestMsg, requestToDir) {
350 if (requestNetwork_in.isReady()) {
351 peek(requestNetwork_in, RequestMsg) {
352 assert(in_msg.Destination.isElement(machineID));
353 if (in_msg.Type == CoherenceRequestType:GETS) {
354 trigger(Event:GETS, in_msg.Address, TBEs[in_msg.Address]);
355 } else if (in_msg.Type == CoherenceRequestType:GETX) {
356 trigger(Event:GETX, in_msg.Address, TBEs[in_msg.Address]);
358 error("Invalid message");
364 in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
365 if (dmaRequestQueue_in.isReady()) {
366 peek(dmaRequestQueue_in, DMARequestMsg) {
367 if (in_msg.Type == DMARequestType:READ) {
368 trigger(Event:DMA_READ, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
369 } else if (in_msg.Type == DMARequestType:WRITE) {
370 if (getDirectoryEntry(in_msg.LineAddress).Tokens == max_tokens()) {
371 trigger(Event:DMA_WRITE_All_Tokens, in_msg.LineAddress,
372 TBEs[in_msg.LineAddress]);
374 trigger(Event:DMA_WRITE, in_msg.LineAddress,
375 TBEs[in_msg.LineAddress]);
378 error("Invalid message");
386 action(a_sendTokens, "a", desc="Send tokens to requestor") {
387 // Only send a message if we have tokens to send
388 if (getDirectoryEntry(address).Tokens > 0) {
389 peek(requestNetwork_in, RequestMsg) {
390 // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
391 enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME?
392 out_msg.Address := address;
393 out_msg.Type := CoherenceResponseType:ACK;
394 out_msg.Sender := machineID;
395 out_msg.Destination.add(in_msg.Requestor);
396 out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
397 out_msg.MessageSize := MessageSizeType:Response_Control;
400 getDirectoryEntry(address).Tokens := 0;
404 action(px_tryIssuingPersistentGETXRequest, "px", desc="...") {
405 if (okToIssueStarving(address, machineID) && (starving == false)) {
406 enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
407 out_msg.Address := address;
408 out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
409 out_msg.Requestor := machineID;
410 out_msg.Destination.broadcast(MachineType:L1Cache);
413 // Currently the configuration system limits the system to only one
414 // chip. Therefore, if we assume one shared L2 cache, then only one
415 // pertinent L2 cache exist.
417 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
419 out_msg.Destination.add(mapAddressToRange(address,
422 l2_select_num_bits));
424 out_msg.Destination.add(map_Address_to_Directory(address));
425 out_msg.MessageSize := MessageSizeType:Persistent_Control;
426 out_msg.Prefetch := PrefetchBit:No;
427 out_msg.AccessMode := AccessModeType:SupervisorMode;
429 markPersistentEntries(address);
432 tbe.WentPersistent := true;
434 // Do not schedule a wakeup, a persistent requests will always complete
437 // We'd like to issue a persistent request, but are not allowed
438 // to issue a P.R. right now. This, we do not increment the
441 // Set a wakeup timer
442 reissueTimerTable.set(address, 10);
446 action(bw_broadcastWrite, "bw", desc="Broadcast GETX if we need tokens") {
447 peek(dmaRequestQueue_in, DMARequestMsg) {
449 // Assser that we only send message if we don't already have all the tokens
451 assert(getDirectoryEntry(address).Tokens != max_tokens());
452 enqueue(requestNetwork_out, RequestMsg, latency = "1") {
453 out_msg.Address := address;
454 out_msg.Type := CoherenceRequestType:GETX;
455 out_msg.Requestor := machineID;
458 // Since only one chip, assuming all L1 caches are local
460 out_msg.Destination.broadcast(MachineType:L1Cache);
461 out_msg.Destination.add(mapAddressToRange(address,
464 l2_select_num_bits));
466 out_msg.RetryNum := 0;
467 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
468 out_msg.Prefetch := PrefetchBit:No;
469 out_msg.AccessMode := AccessModeType:SupervisorMode;
474 action(ps_tryIssuingPersistentGETSRequest, "ps", desc="...") {
475 if (okToIssueStarving(address, machineID) && (starving == false)) {
476 enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
477 out_msg.Address := address;
478 out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
479 out_msg.Requestor := machineID;
480 out_msg.Destination.broadcast(MachineType:L1Cache);
483 // Currently the configuration system limits the system to only one
484 // chip. Therefore, if we assume one shared L2 cache, then only one
485 // pertinent L2 cache exist.
487 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
489 out_msg.Destination.add(mapAddressToRange(address,
492 l2_select_num_bits));
494 out_msg.Destination.add(map_Address_to_Directory(address));
495 out_msg.MessageSize := MessageSizeType:Persistent_Control;
496 out_msg.Prefetch := PrefetchBit:No;
497 out_msg.AccessMode := AccessModeType:SupervisorMode;
499 markPersistentEntries(address);
502 tbe.WentPersistent := true;
504 // Do not schedule a wakeup, a persistent requests will always complete
507 // We'd like to issue a persistent request, but are not allowed
508 // to issue a P.R. right now. This, we do not increment the
511 // Set a wakeup timer
512 reissueTimerTable.set(address, 10);
516 action(br_broadcastRead, "br", desc="Broadcast GETS for data") {
517 peek(dmaRequestQueue_in, DMARequestMsg) {
518 enqueue(requestNetwork_out, RequestMsg, latency = "1") {
519 out_msg.Address := address;
520 out_msg.Type := CoherenceRequestType:GETS;
521 out_msg.Requestor := machineID;
524 // Since only one chip, assuming all L1 caches are local
526 out_msg.Destination.broadcast(MachineType:L1Cache);
527 out_msg.Destination.add(mapAddressToRange(address,
530 l2_select_num_bits));
532 out_msg.RetryNum := 0;
533 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
534 out_msg.Prefetch := PrefetchBit:No;
535 out_msg.AccessMode := AccessModeType:SupervisorMode;
540 action(aa_sendTokensToStarver, "\a", desc="Send tokens to starver") {
541 // Only send a message if we have tokens to send
542 if (getDirectoryEntry(address).Tokens > 0) {
543 // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
544 enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME?
545 out_msg.Address := address;
546 out_msg.Type := CoherenceResponseType:ACK;
547 out_msg.Sender := machineID;
548 out_msg.Destination.add(persistentTable.findSmallest(address));
549 out_msg.Tokens := getDirectoryEntry(address).Tokens;
550 out_msg.MessageSize := MessageSizeType:Response_Control;
552 getDirectoryEntry(address).Tokens := 0;
556 action(d_sendMemoryDataWithAllTokens, "d", desc="Send data and tokens to requestor") {
557 peek(memQueue_in, MemoryMsg) {
558 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
559 out_msg.Address := address;
560 out_msg.Type := CoherenceResponseType:DATA_OWNER;
561 out_msg.Sender := machineID;
562 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
563 assert(getDirectoryEntry(address).Tokens > 0);
564 out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
565 out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
566 out_msg.Dirty := false;
567 out_msg.MessageSize := MessageSizeType:Response_Data;
570 getDirectoryEntry(address).Tokens := 0;
573 action(dd_sendMemDataToStarver, "\d", desc="Send data and tokens to starver") {
574 peek(memQueue_in, MemoryMsg) {
575 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
576 out_msg.Address := address;
577 out_msg.Type := CoherenceResponseType:DATA_OWNER;
578 out_msg.Sender := machineID;
579 out_msg.Destination.add(persistentTable.findSmallest(address));
580 assert(getDirectoryEntry(address).Tokens > 0);
581 out_msg.Tokens := getDirectoryEntry(address).Tokens;
582 out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
583 out_msg.Dirty := false;
584 out_msg.MessageSize := MessageSizeType:Response_Data;
587 getDirectoryEntry(address).Tokens := 0;
590 action(de_sendTbeDataToStarver, "de", desc="Send data and tokens to starver") {
591 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
592 out_msg.Address := address;
593 out_msg.Type := CoherenceResponseType:DATA_OWNER;
594 out_msg.Sender := machineID;
595 out_msg.Destination.add(persistentTable.findSmallest(address));
596 assert(getDirectoryEntry(address).Tokens > 0);
597 out_msg.Tokens := getDirectoryEntry(address).Tokens;
598 out_msg.DataBlk := tbe.DataBlk;
599 out_msg.Dirty := false;
600 out_msg.MessageSize := MessageSizeType:Response_Data;
602 getDirectoryEntry(address).Tokens := 0;
605 action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
606 peek(requestNetwork_in, RequestMsg) {
607 enqueue(memQueue_out, MemoryMsg, latency="1") {
608 out_msg.Address := address;
609 out_msg.Type := MemoryRequestType:MEMORY_READ;
610 out_msg.Sender := machineID;
611 out_msg.OriginalRequestorMachId := in_msg.Requestor;
612 out_msg.MessageSize := in_msg.MessageSize;
613 out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
614 DPRINTF(RubySlicc, "%s\n", out_msg);
619 action(qp_queueMemoryForPersistent, "qp", desc="Queue off-chip fetch request") {
620 enqueue(memQueue_out, MemoryMsg, latency="1") {
621 out_msg.Address := address;
622 out_msg.Type := MemoryRequestType:MEMORY_READ;
623 out_msg.Sender := machineID;
624 out_msg.OriginalRequestorMachId := persistentTable.findSmallest(address);
625 out_msg.MessageSize := MessageSizeType:Request_Control;
626 out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
627 DPRINTF(RubySlicc, "%s\n", out_msg);
631 action(fd_memoryDma, "fd", desc="Queue off-chip fetch request") {
632 peek(dmaRequestQueue_in, DMARequestMsg) {
633 enqueue(memQueue_out, MemoryMsg, latency="1") {
634 out_msg.Address := address;
635 out_msg.Type := MemoryRequestType:MEMORY_READ;
636 out_msg.Sender := machineID;
637 out_msg.OriginalRequestorMachId := in_msg.Requestor;
638 out_msg.MessageSize := in_msg.MessageSize;
639 out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
640 DPRINTF(RubySlicc, "%s\n", out_msg);
645 action(lq_queueMemoryWbRequest, "lq", desc="Write data to memory") {
646 enqueue(memQueue_out, MemoryMsg, latency="1") {
647 out_msg.Address := address;
648 out_msg.Type := MemoryRequestType:MEMORY_WB;
649 DPRINTF(RubySlicc, "%s\n", out_msg);
653 action(ld_queueMemoryDmaWriteFromTbe, "ld", desc="Write DMA data to memory") {
654 enqueue(memQueue_out, MemoryMsg, latency="1") {
655 out_msg.Address := address;
656 out_msg.Type := MemoryRequestType:MEMORY_WB;
657 // first, initialize the data blk to the current version of system memory
658 out_msg.DataBlk := tbe.DataBlk;
659 // then add the dma write data
660 out_msg.DataBlk.copyPartial(tbe.DmaDataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
661 DPRINTF(RubySlicc, "%s\n", out_msg);
665 action(lr_queueMemoryDmaReadWriteback, "lr", desc="Write DMA data from read to memory") {
666 enqueue(memQueue_out, MemoryMsg, latency="1") {
667 out_msg.Address := address;
668 out_msg.Type := MemoryRequestType:MEMORY_WB;
669 // first, initialize the data blk to the current version of system memory
670 out_msg.DataBlk := tbe.DataBlk;
671 DPRINTF(RubySlicc, "%s\n", out_msg);
675 action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
676 peek(dmaRequestQueue_in, DMARequestMsg) {
677 TBEs.allocate(address);
678 set_tbe(TBEs[address]);
679 tbe.DmaDataBlk := in_msg.DataBlk;
680 tbe.PhysicalAddress := in_msg.PhysicalAddress;
681 tbe.Len := in_msg.Len;
682 tbe.DmaRequestor := in_msg.Requestor;
683 tbe.WentPersistent := false;
687 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
689 if (tbe.WentPersistent) {
690 assert(starving == true);
692 enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
693 out_msg.Address := address;
694 out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
695 out_msg.Requestor := machineID;
696 out_msg.Destination.broadcast(MachineType:L1Cache);
699 // Currently the configuration system limits the system to only one
700 // chip. Therefore, if we assume one shared L2 cache, then only one
701 // pertinent L2 cache exist.
703 //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
705 out_msg.Destination.add(mapAddressToRange(address,
708 l2_select_num_bits));
710 out_msg.Destination.add(map_Address_to_Directory(address));
711 out_msg.MessageSize := MessageSizeType:Persistent_Control;
716 TBEs.deallocate(address);
720 action(rd_recordDataInTbe, "rd", desc="Record data in TBE") {
721 peek(responseNetwork_in, ResponseMsg) {
722 tbe.DataBlk := in_msg.DataBlk;
726 action(cd_writeCleanDataToTbe, "cd", desc="Write clean memory data to TBE") {
727 tbe.DataBlk := getDirectoryEntry(address).DataBlk;
730 action(dwt_writeDmaDataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
731 getDirectoryEntry(address).DataBlk := tbe.DataBlk;
732 getDirectoryEntry(address).DataBlk.copyPartial(tbe.DmaDataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
735 action(f_incrementTokens, "f", desc="Increment the number of tokens we're tracking") {
736 peek(responseNetwork_in, ResponseMsg) {
737 assert(in_msg.Tokens >= 1);
738 getDirectoryEntry(address).Tokens := getDirectoryEntry(address).Tokens + in_msg.Tokens;
742 action(aat_assertAllTokens, "aat", desc="assert that we have all tokens") {
743 assert(getDirectoryEntry(address).Tokens == max_tokens());
746 action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
747 requestNetwork_in.dequeue();
750 action(z_recycleRequest, "z", desc="Recycle the request queue") {
751 requestNetwork_in.recycle();
754 action(k_popIncomingResponseQueue, "k", desc="Pop incoming response queue") {
755 responseNetwork_in.dequeue();
758 action(kz_recycleResponse, "kz", desc="Recycle incoming response queue") {
759 responseNetwork_in.recycle();
762 action(l_popIncomingPersistentQueue, "l", desc="Pop incoming persistent queue") {
763 persistentNetwork_in.dequeue();
766 action(p_popDmaRequestQueue, "pd", desc="pop dma request queue") {
767 dmaRequestQueue_in.dequeue();
770 action(y_recycleDmaRequestQueue, "y", desc="recycle dma request queue") {
771 dmaRequestQueue_in.recycle();
774 action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
775 memQueue_in.dequeue();
778 action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
779 peek(responseNetwork_in, ResponseMsg) {
780 getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
781 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
782 in_msg.Address, in_msg.DataBlk);
786 action(n_checkData, "n", desc="Check incoming clean data message") {
787 peek(responseNetwork_in, ResponseMsg) {
788 assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
792 action(r_bounceResponse, "r", desc="Bounce response to starving processor") {
793 peek(responseNetwork_in, ResponseMsg) {
794 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
795 out_msg.Address := address;
796 out_msg.Type := in_msg.Type;
797 out_msg.Sender := machineID;
798 out_msg.Destination.add(persistentTable.findSmallest(address));
799 out_msg.Tokens := in_msg.Tokens;
800 out_msg.MessageSize := in_msg.MessageSize;
801 out_msg.DataBlk := in_msg.DataBlk;
802 out_msg.Dirty := in_msg.Dirty;
807 action(rs_resetScheduleTimeout, "rs", desc="Reschedule Schedule Timeout") {
809 // currently only support a fixed timeout latency
811 if (reissueTimerTable.isSet(address)) {
812 reissueTimerTable.unset(address);
813 reissueTimerTable.set(address, fixed_timeout_latency);
817 action(st_scheduleTimeout, "st", desc="Schedule Timeout") {
819 // currently only support a fixed timeout latency
821 reissueTimerTable.set(address, fixed_timeout_latency);
824 action(ut_unsetReissueTimer, "ut", desc="Unset reissue timer.") {
825 if (reissueTimerTable.isSet(address)) {
826 reissueTimerTable.unset(address);
830 action(bd_bounceDatalessOwnerToken, "bd", desc="Bounce clean owner token to starving processor") {
831 peek(responseNetwork_in, ResponseMsg) {
832 assert(in_msg.Type == CoherenceResponseType:ACK_OWNER);
833 assert(in_msg.Dirty == false);
834 assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
836 // NOTE: The following check would not be valid in a real
837 // implementation. We include the data in the "dataless"
838 // message so we can assert the clean data matches the datablock
840 assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
842 // Bounce the message, but "re-associate" the data and the owner
843 // token. In essence we're converting an ACK_OWNER message to a
844 // DATA_OWNER message, keeping the number of tokens the same.
845 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
846 out_msg.Address := address;
847 out_msg.Type := CoherenceResponseType:DATA_OWNER;
848 out_msg.Sender := machineID;
849 out_msg.Destination.add(persistentTable.findSmallest(address));
850 out_msg.Tokens := in_msg.Tokens;
851 out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
852 out_msg.Dirty := in_msg.Dirty;
853 out_msg.MessageSize := MessageSizeType:Response_Data;
858 action(da_sendDmaAck, "da", desc="Send Ack to DMA controller") {
859 enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
860 out_msg.PhysicalAddress := address;
861 out_msg.LineAddress := address;
862 out_msg.Type := DMAResponseType:ACK;
863 out_msg.Destination.add(tbe.DmaRequestor);
864 out_msg.MessageSize := MessageSizeType:Writeback_Control;
868 action(dm_sendMemoryDataToDma, "dm", desc="Send Data to DMA controller from memory") {
869 peek(memQueue_in, MemoryMsg) {
870 enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
871 out_msg.PhysicalAddress := address;
872 out_msg.LineAddress := address;
873 out_msg.Type := DMAResponseType:DATA;
875 // we send the entire data block and rely on the dma controller to
876 // split it up if need be
878 out_msg.DataBlk := in_msg.DataBlk;
879 out_msg.Destination.add(tbe.DmaRequestor);
880 out_msg.MessageSize := MessageSizeType:Response_Data;
885 action(dd_sendDmaData, "dd", desc="Send Data to DMA controller") {
886 peek(responseNetwork_in, ResponseMsg) {
887 enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
888 out_msg.PhysicalAddress := address;
889 out_msg.LineAddress := address;
890 out_msg.Type := DMAResponseType:DATA;
892 // we send the entire data block and rely on the dma controller to
893 // split it up if need be
895 out_msg.DataBlk := in_msg.DataBlk;
896 out_msg.Destination.add(tbe.DmaRequestor);
897 out_msg.MessageSize := MessageSizeType:Response_Data;
905 // Trans. from base state O
906 // the directory has valid data
908 transition(O, GETX, NO_W) {
909 qf_queueMemoryFetchRequest;
910 j_popIncomingRequestQueue;
913 transition(O, DMA_WRITE, O_DW) {
914 vd_allocateDmaRequestInTBE;
915 cd_writeCleanDataToTbe;
918 p_popDmaRequestQueue;
921 transition(O, DMA_WRITE_All_Tokens, O_DW_W) {
922 vd_allocateDmaRequestInTBE;
923 cd_writeCleanDataToTbe;
924 dwt_writeDmaDataFromTBE;
925 ld_queueMemoryDmaWriteFromTbe;
926 p_popDmaRequestQueue;
929 transition(O, GETS, NO_W) {
930 qf_queueMemoryFetchRequest;
931 j_popIncomingRequestQueue;
934 transition(O, DMA_READ, O_DR_W) {
935 vd_allocateDmaRequestInTBE;
938 p_popDmaRequestQueue;
941 transition(O, Lockdown, L_O_W) {
942 qp_queueMemoryForPersistent;
943 l_popIncomingPersistentQueue;
946 transition(O, {Tokens, Ack_All_Tokens}) {
948 k_popIncomingResponseQueue;
951 transition(O, {Data_Owner, Data_All_Tokens}) {
954 k_popIncomingResponseQueue;
957 transition({O, NO}, Unlockdown) {
958 l_popIncomingPersistentQueue;
962 // transitioning to Owner, waiting for memory before DMA ack
963 // All other events should recycle/stall
965 transition(O_DR_W, Memory_Data, O) {
966 dm_sendMemoryDataToDma;
967 ut_unsetReissueTimer;
973 // issued GETX for DMA write, waiting for all tokens
975 transition(O_DW, Request_Timeout) {
976 ut_unsetReissueTimer;
977 px_tryIssuingPersistentGETXRequest;
980 transition(O_DW, Tokens) {
982 k_popIncomingResponseQueue;
985 transition(O_DW, Data_Owner) {
988 k_popIncomingResponseQueue;
991 transition(O_DW, Ack_Owner) {
993 cd_writeCleanDataToTbe;
994 k_popIncomingResponseQueue;
997 transition(O_DW, Lockdown, DW_L) {
998 de_sendTbeDataToStarver;
999 l_popIncomingPersistentQueue;
1002 transition({NO_DW, O_DW}, Data_All_Tokens, O_DW_W) {
1005 dwt_writeDmaDataFromTBE;
1006 ld_queueMemoryDmaWriteFromTbe;
1007 ut_unsetReissueTimer;
1008 k_popIncomingResponseQueue;
1011 transition(O_DW, Ack_All_Tokens, O_DW_W) {
1013 dwt_writeDmaDataFromTBE;
1014 ld_queueMemoryDmaWriteFromTbe;
1015 ut_unsetReissueTimer;
1016 k_popIncomingResponseQueue;
1019 transition(O_DW, Ack_Owner_All_Tokens, O_DW_W) {
1021 cd_writeCleanDataToTbe;
1022 dwt_writeDmaDataFromTBE;
1023 ld_queueMemoryDmaWriteFromTbe;
1024 ut_unsetReissueTimer;
1025 k_popIncomingResponseQueue;
1028 transition(O_DW_W, Memory_Ack, O) {
1036 // The direcotry does not have valid data, but may have some tokens
1038 transition(NO, GETX) {
1040 j_popIncomingRequestQueue;
1043 transition(NO, DMA_WRITE, NO_DW) {
1044 vd_allocateDmaRequestInTBE;
1047 p_popDmaRequestQueue;
1050 transition(NO, GETS) {
1051 j_popIncomingRequestQueue;
1054 transition(NO, DMA_READ, NO_DR) {
1055 vd_allocateDmaRequestInTBE;
1058 p_popDmaRequestQueue;
1061 transition(NO, Lockdown, L) {
1062 aa_sendTokensToStarver;
1063 l_popIncomingPersistentQueue;
1066 transition(NO, {Data_Owner, Data_All_Tokens}, O_W) {
1067 m_writeDataToMemory;
1069 lq_queueMemoryWbRequest;
1070 k_popIncomingResponseQueue;
1073 transition(NO, {Ack_Owner, Ack_Owner_All_Tokens}, O) {
1076 k_popIncomingResponseQueue;
1079 transition(NO, Tokens) {
1081 k_popIncomingResponseQueue;
1084 transition(NO_W, Memory_Data, NO) {
1085 d_sendMemoryDataWithAllTokens;
1089 // Trans. from NO_DW
1090 transition(NO_DW, Request_Timeout) {
1091 ut_unsetReissueTimer;
1092 px_tryIssuingPersistentGETXRequest;
1095 transition(NO_DW, Lockdown, DW_L) {
1096 aa_sendTokensToStarver;
1097 l_popIncomingPersistentQueue;
1100 // Note: NO_DW, Data_All_Tokens transition is combined with O_DW
1101 // Note: NO_DW should not receive the action Ack_All_Tokens because the
1102 // directory does not have valid data
1104 transition(NO_DW, Data_Owner, O_DW) {
1107 k_popIncomingResponseQueue;
1110 transition({NO_DW, NO_DR}, Tokens) {
1112 k_popIncomingResponseQueue;
1115 // Trans. from NO_DR
1116 transition(NO_DR, Request_Timeout) {
1117 ut_unsetReissueTimer;
1118 ps_tryIssuingPersistentGETSRequest;
1121 transition(NO_DR, Lockdown, DR_L) {
1122 aa_sendTokensToStarver;
1123 l_popIncomingPersistentQueue;
1126 transition(NO_DR, {Data_Owner, Data_All_Tokens}, O_W) {
1127 m_writeDataToMemory;
1130 lr_queueMemoryDmaReadWriteback;
1131 ut_unsetReissueTimer;
1133 k_popIncomingResponseQueue;
1137 transition({L, DW_L, DR_L}, {GETX, GETS}) {
1138 j_popIncomingRequestQueue;
1141 transition({L, DW_L, DR_L, L_O_W, L_NO_W, DR_L_W, DW_L_W}, Lockdown) {
1142 l_popIncomingPersistentQueue;
1146 // Received data for lockdown blocks
1147 // For blocks with outstanding dma requests to them
1148 // ...we could change this to write the data to memory and send it cleanly
1149 // ...we could also proactively complete our DMA requests
1150 // However, to keep my mind from spinning out-of-control, we won't for now :)
1152 transition({DW_L, DR_L, L}, {Data_Owner, Data_All_Tokens}) {
1154 k_popIncomingResponseQueue;
1157 transition({DW_L, DR_L, L}, Tokens) {
1159 k_popIncomingResponseQueue;
1162 transition({DW_L, DR_L, L}, {Ack_Owner_All_Tokens, Ack_Owner}) {
1163 bd_bounceDatalessOwnerToken;
1164 k_popIncomingResponseQueue;
1167 transition(L, {Unlockdown, Own_Lock_or_Unlock}, NO) {
1168 l_popIncomingPersistentQueue;
1171 transition(L, Own_Lock_or_Unlock_Tokens, O) {
1172 l_popIncomingPersistentQueue;
1175 transition({L_NO_W, L_O_W}, Memory_Data, L) {
1176 dd_sendMemDataToStarver;
1180 transition(L_O_W, Memory_Ack) {
1181 qp_queueMemoryForPersistent;
1185 transition(L_O_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, O_W) {
1186 l_popIncomingPersistentQueue;
1189 transition(L_NO_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, NO_W) {
1190 l_popIncomingPersistentQueue;
1193 transition(DR_L_W, Memory_Data, DR_L) {
1194 dd_sendMemDataToStarver;
1198 transition(DW_L_W, Memory_Ack, L) {
1199 aat_assertAllTokens;
1202 dd_sendMemDataToStarver;
1206 transition(DW_L, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, NO_DW) {
1207 l_popIncomingPersistentQueue;
1210 transition(DR_L_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, O_DR_W) {
1211 l_popIncomingPersistentQueue;
1214 transition(DW_L_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, O_DW_W) {
1215 l_popIncomingPersistentQueue;
1218 transition({DW_L, DR_L_W, DW_L_W}, Request_Timeout) {
1219 ut_unsetReissueTimer;
1220 px_tryIssuingPersistentGETXRequest;
1223 transition(DR_L, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, NO_DR) {
1224 l_popIncomingPersistentQueue;
1227 transition(DR_L, Request_Timeout) {
1228 ut_unsetReissueTimer;
1229 ps_tryIssuingPersistentGETSRequest;
1233 // The O_W + Memory_Data > O transistion is confusing, but it can happen if a
1234 // presistent request is issued and resolve before memory returns with data
1236 transition(O_W, {Memory_Ack, Memory_Data}, O) {
1240 transition({O, NO}, {Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}) {
1241 l_popIncomingPersistentQueue;
1245 transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, DW_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR}, {GETX, GETS}) {
1249 transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, DW_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR, L, DW_L, DR_L}, {DMA_READ, DMA_WRITE, DMA_WRITE_All_Tokens}) {
1250 y_recycleDmaRequestQueue;
1253 transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, DW_L_W, O_DW_W, O_DR_W}, {Data_Owner, Ack_Owner, Tokens, Data_All_Tokens, Ack_All_Tokens}) {
1258 // If we receive a request timeout while waiting for memory, it is likely that
1259 // the request will be satisfied and issuing a presistent request will do us
1260 // no good. Just wait.
1262 transition({O_DW_W, O_DR_W}, Request_Timeout) {
1263 rs_resetScheduleTimeout;
1266 transition(NO_W, Lockdown, L_NO_W) {
1267 l_popIncomingPersistentQueue;
1270 transition(O_W, Lockdown, L_O_W) {
1271 l_popIncomingPersistentQueue;
1274 transition(O_DR_W, Lockdown, DR_L_W) {
1275 l_popIncomingPersistentQueue;
1278 transition(O_DW_W, Lockdown, DW_L_W) {
1279 l_popIncomingPersistentQueue;
1282 transition({NO_W, O_W, O_DR_W, O_DW_W, O_DW, NO_DR, NO_DW}, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}) {
1283 l_popIncomingPersistentQueue;