src/mem/protocol/MOESI_CMP_token-dir.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  */
  33
  34
  35 machine(Directory, "Token protocol")
  36  : DirectoryMemory * directory,
  37    MemoryControl * memBuffer,
  38    int l2_select_num_bits,
  39    int directory_latency = 5,
  40    bool distributed_persistent = true,
  41    int fixed_timeout_latency = 100
  42 {
  43
  44   MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true", vnet_type="response";
  45   MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false", vnet_type="response";
  46   MessageBuffer persistentFromDir, network="To", virtual_network="3", ordered="true", vnet_type="persistent";
  47   MessageBuffer requestFromDir, network="To", virtual_network="1", ordered="false", vnet_type="request";
  48
  49   MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false", vnet_type="response";
  50   MessageBuffer persistentToDir, network="From", virtual_network="3", ordered="true", vnet_type="persistent";
  51   MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false", vnet_type="request";
  52   MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true", vnet_type="request";
  53
  54   // STATES
  55   state_declaration(State, desc="Directory states", default="Directory_State_O") {
  56     // Base states
  57     O, AccessPermission:Read_Only, desc="Owner, memory has valid data, but not necessarily all the tokens";
  58     NO, AccessPermission:Maybe_Stale, desc="Not Owner";
  59     L, AccessPermission:Busy, desc="Locked";
  60
  61     // Memory wait states - can block all messages including persistent requests
  62     O_W, AccessPermission:Busy, desc="transitioning to Owner, waiting for memory write";
  63     L_O_W, AccessPermission:Busy, desc="transitioning to Locked, waiting for memory read, could eventually return to O";
  64     L_NO_W, AccessPermission:Busy, desc="transitioning to Locked, waiting for memory read, eventually return to NO";
  65     DR_L_W, AccessPermission:Busy, desc="transitioning to Locked underneath a DMA read, waiting for memory data";
  66     DW_L_W, AccessPermission:Busy, desc="transitioning to Locked underneath a DMA write, waiting for memory ack";
  67     NO_W, AccessPermission:Busy, desc="transitioning to Not Owner, waiting for memory read";
  68     O_DW_W, AccessPermission:Busy, desc="transitioning to Owner, waiting for memory before DMA ack";
  69     O_DR_W, AccessPermission:Busy, desc="transitioning to Owner, waiting for memory before DMA data";
  70
  71     // DMA request transient states - must respond to persistent requests
  72     O_DW, AccessPermission:Busy, desc="issued GETX for DMA write, waiting for all tokens";
  73     NO_DW, AccessPermission:Busy, desc="issued GETX for DMA write, waiting for all tokens";
  74     NO_DR, AccessPermission:Busy, desc="issued GETS for DMA read, waiting for data";
  75
  76     // DMA request in progress - competing with a CPU persistent request
  77     DW_L, AccessPermission:Busy, desc="issued GETX for DMA write, CPU persistent request must complete first";
  78     DR_L, AccessPermission:Busy, desc="issued GETS for DMA read, CPU persistent request must complete first";
  79
  80   }
  81
  82   // Events
  83   enumeration(Event, desc="Directory events") {
  84     GETX, desc="A GETX arrives";
  85     GETS, desc="A GETS arrives";
  86     Lockdown, desc="A lockdown request arrives";
  87     Unlockdown, desc="An un-lockdown request arrives";
  88     Own_Lock_or_Unlock, desc="own lock or unlock";
  89     Own_Lock_or_Unlock_Tokens, desc="own lock or unlock with tokens";
  90     Data_Owner, desc="Data arrive";
  91     Data_All_Tokens, desc="Data and all tokens";
  92     Ack_Owner, desc="Owner token arrived without data because it was clean";
  93     Ack_Owner_All_Tokens, desc="All tokens including owner arrived without data because it was clean";
  94     Tokens, desc="Tokens arrive";
  95     Ack_All_Tokens, desc="All_Tokens arrive";
  96     Request_Timeout, desc="A DMA request has timed out";
  97
  98     // Memory Controller
  99     Memory_Data, desc="Fetched data from memory arrives";
 100     Memory_Ack, desc="Writeback Ack from memory arrives";
 101
 102     // DMA requests
 103     DMA_READ, desc="A DMA Read memory request";
 104     DMA_WRITE, desc="A DMA Write memory request";
 105     DMA_WRITE_All_Tokens, desc="A DMA Write memory request, directory has all tokens";
 106   }
 107
 108   // TYPES
 109
 110   // DirectoryEntry
 111   structure(Entry, desc="...", interface="AbstractEntry") {
 112     State DirectoryState,          desc="Directory state";
 113     DataBlock DataBlk,             desc="data for the block";
 114     int Tokens, default="max_tokens()", desc="Number of tokens for the line we're holding";
 115
 116     // The following state is provided to allow for bandwidth
 117     // efficient directory-like operation.  However all of this state
 118     // is 'soft state' that does not need to be correct (as long as
 119     // you're eventually willing to resort to broadcast.)
 120
 121     Set Owner,                     desc="Probable Owner of the line.  More accurately, the set of processors who need to see a GetS or GetO.  We use a Set for convenience, but only one bit is set at a time.";
 122     Set Sharers,                   desc="Probable sharers of the line.  More accurately, the set of processors who need to see a GetX";
 123   }
 124
 125   structure(PersistentTable, external="yes") {
 126     void persistentRequestLock(Address, MachineID, AccessType);
 127     void persistentRequestUnlock(Address, MachineID);
 128     bool okToIssueStarving(Address, MachineID);
 129     MachineID findSmallest(Address);
 130     AccessType typeOfSmallest(Address);
 131     void markEntries(Address);
 132     bool isLocked(Address);
 133     int countStarvingForAddress(Address);
 134     int countReadStarvingForAddress(Address);
 135   }
 136
 137   // TBE entries for DMA requests
 138   structure(TBE, desc="TBE entries for outstanding DMA requests") {
 139     Address PhysicalAddress, desc="physical address";
 140     State TBEState,        desc="Transient State";
 141     DataBlock DmaDataBlk,  desc="DMA Data to be written.  Partial blocks need to merged with system memory";
 142     DataBlock DataBlk,     desc="The current view of system memory";
 143     int Len,               desc="...";
 144     MachineID DmaRequestor, desc="DMA requestor";
 145     bool WentPersistent,   desc="Did the DMA request require a persistent request";
 146   }
 147
 148   structure(TBETable, external="yes") {
 149     TBE lookup(Address);
 150     void allocate(Address);
 151     void deallocate(Address);
 152     bool isPresent(Address);
 153   }
 154
 155   // ** OBJECTS **
 156
 157   PersistentTable persistentTable;
 158   TimerTable reissueTimerTable;
 159
 160   TBETable TBEs, template_hack="<Directory_TBE>";
 161
 162   bool starving, default="false";
 163   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 164
 165   void set_tbe(TBE b);
 166   void unset_tbe();
 167
 168   Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
 169     Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
 170
 171     if (is_valid(dir_entry)) {
 172       return dir_entry;
 173     }
 174
 175     dir_entry :=  static_cast(Entry, "pointer",
 176                               directory.allocate(addr, new Entry));
 177     return dir_entry;
 178   }
 179
 180   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 181     return getDirectoryEntry(addr).DataBlk;
 182   }
 183
 184   State getState(TBE tbe, Address addr) {
 185     if (is_valid(tbe)) {
 186       return tbe.TBEState;
 187     } else {
 188       return getDirectoryEntry(addr).DirectoryState;
 189     }
 190   }
 191
 192   void setState(TBE tbe, Address addr, State state) {
 193     if (is_valid(tbe)) {
 194       tbe.TBEState := state;
 195     }
 196     getDirectoryEntry(addr).DirectoryState := state;
 197
 198     if (state == State:L || state == State:DW_L || state == State:DR_L) {
 199       assert(getDirectoryEntry(addr).Tokens == 0);
 200     }
 201
 202     // We have one or zero owners
 203     assert((getDirectoryEntry(addr).Owner.count() == 0) || (getDirectoryEntry(addr).Owner.count() == 1));
 204
 205     // Make sure the token count is in range
 206     assert(getDirectoryEntry(addr).Tokens >= 0);
 207     assert(getDirectoryEntry(addr).Tokens <= max_tokens());
 208
 209     if (state == State:O || state == State:O_W || state == State:O_DW) {
 210       assert(getDirectoryEntry(addr).Tokens >= 1); // Must have at least one token
 211       // assert(getDirectoryEntry(addr).Tokens >= (max_tokens() / 2)); // Only mostly true; this might not always hold
 212     }
 213   }
 214
 215   AccessPermission getAccessPermission(Address addr) {
 216     TBE tbe := TBEs[addr];
 217     if(is_valid(tbe)) {
 218       return Directory_State_to_permission(tbe.TBEState);
 219     }
 220
 221     if (directory.isPresent(addr)) {
 222       DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
 223       return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
 224     }
 225
 226     DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
 227     return AccessPermission:NotPresent;
 228   }
 229
 230   void setAccessPermission(Address addr, State state) {
 231     getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
 232   }
 233
 234   bool okToIssueStarving(Address addr, MachineID machinID) {
 235     return persistentTable.okToIssueStarving(addr, machineID);
 236   }
 237
 238   void markPersistentEntries(Address addr) {
 239     persistentTable.markEntries(addr);
 240   }
 241
 242   // ** OUT_PORTS **
 243   out_port(responseNetwork_out, ResponseMsg, responseFromDir);
 244   out_port(persistentNetwork_out, PersistentMsg, persistentFromDir);
 245   out_port(requestNetwork_out, RequestMsg, requestFromDir);
 246   out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
 247
 248   //
 249   // Memory buffer for memory controller to DIMM communication
 250   //
 251   out_port(memQueue_out, MemoryMsg, memBuffer);
 252
 253   // ** IN_PORTS **
 254
 255   // off-chip memory request/response is done
 256   in_port(memQueue_in, MemoryMsg, memBuffer) {
 257     if (memQueue_in.isReady()) {
 258       peek(memQueue_in, MemoryMsg) {
 259         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
 260           trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
 261         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
 262           trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
 263         } else {
 264           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
 265           error("Invalid message");
 266         }
 267       }
 268     }
 269   }
 270
 271   // Reissue Timer
 272   in_port(reissueTimerTable_in, Address, reissueTimerTable) {
 273     if (reissueTimerTable_in.isReady()) {
 274       trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
 275               TBEs[reissueTimerTable.readyAddress()]);
 276     }
 277   }
 278
 279   in_port(responseNetwork_in, ResponseMsg, responseToDir) {
 280     if (responseNetwork_in.isReady()) {
 281       peek(responseNetwork_in, ResponseMsg) {
 282         assert(in_msg.Destination.isElement(machineID));
 283         if (getDirectoryEntry(in_msg.Address).Tokens + in_msg.Tokens == max_tokens()) {
 284           if ((in_msg.Type == CoherenceResponseType:DATA_OWNER) ||
 285               (in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
 286             trigger(Event:Data_All_Tokens, in_msg.Address,
 287                     TBEs[in_msg.Address]);
 288           } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
 289             trigger(Event:Ack_Owner_All_Tokens, in_msg.Address,
 290                     TBEs[in_msg.Address]);
 291           } else if (in_msg.Type == CoherenceResponseType:ACK) {
 292             trigger(Event:Ack_All_Tokens, in_msg.Address,
 293                     TBEs[in_msg.Address]);
 294           } else {
 295             DPRINTF(RubySlicc, "%s\n", in_msg.Type);
 296             error("Invalid message");
 297           }
 298         } else {
 299           if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
 300             trigger(Event:Data_Owner, in_msg.Address,
 301                     TBEs[in_msg.Address]);
 302           } else if ((in_msg.Type == CoherenceResponseType:ACK) ||
 303                      (in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
 304             trigger(Event:Tokens, in_msg.Address,
 305                     TBEs[in_msg.Address]);
 306           } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
 307             trigger(Event:Ack_Owner, in_msg.Address,
 308                     TBEs[in_msg.Address]);
 309           } else {
 310             DPRINTF(RubySlicc, "%s\n", in_msg.Type);
 311             error("Invalid message");
 312           }
 313         }
 314       }
 315     }
 316   }
 317
 318   in_port(persistentNetwork_in, PersistentMsg, persistentToDir) {
 319     if (persistentNetwork_in.isReady()) {
 320       peek(persistentNetwork_in, PersistentMsg) {
 321         assert(in_msg.Destination.isElement(machineID));
 322
 323         if (distributed_persistent) {
 324           // Apply the lockdown or unlockdown message to the table
 325           if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
 326             persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
 327           } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
 328             persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
 329           } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
 330             persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
 331           } else {
 332             error("Invalid message");
 333           }
 334
 335           // React to the message based on the current state of the table
 336           if (persistentTable.isLocked(in_msg.Address)) {
 337             if (persistentTable.findSmallest(in_msg.Address) == machineID) {
 338               if (getDirectoryEntry(in_msg.Address).Tokens > 0) {
 339                 trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Address,
 340                         TBEs[in_msg.Address]);
 341               } else {
 342                 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 343                         TBEs[in_msg.Address]);
 344               }
 345             } else {
 346               // locked
 347               trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
 348             }
 349           } else {
 350             // unlocked
 351             trigger(Event:Unlockdown, in_msg.Address, TBEs[in_msg.Address]);
 352           }
 353         }
 354         else {
 355           if (persistentTable.findSmallest(in_msg.Address) == machineID) {
 356               if (getDirectoryEntry(in_msg.Address).Tokens > 0) {
 357                 trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Address,
 358                         TBEs[in_msg.Address]);
 359               } else {
 360                 trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
 361                         TBEs[in_msg.Address]);
 362               }
 363           } else if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
 364             // locked
 365             trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
 366           } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
 367             // locked
 368             trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
 369           } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
 370             // unlocked
 371             trigger(Event:Unlockdown, in_msg.Address, TBEs[in_msg.Address]);
 372           } else {
 373             error("Invalid message");
 374           }
 375         }
 376       }
 377     }
 378   }
 379
 380   in_port(requestNetwork_in, RequestMsg, requestToDir) {
 381     if (requestNetwork_in.isReady()) {
 382       peek(requestNetwork_in, RequestMsg) {
 383         assert(in_msg.Destination.isElement(machineID));
 384         if (in_msg.Type == CoherenceRequestType:GETS) {
 385           trigger(Event:GETS, in_msg.Address, TBEs[in_msg.Address]);
 386         } else if (in_msg.Type == CoherenceRequestType:GETX) {
 387           trigger(Event:GETX, in_msg.Address, TBEs[in_msg.Address]);
 388         } else {
 389           error("Invalid message");
 390         }
 391       }
 392     }
 393   }
 394
 395   in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
 396     if (dmaRequestQueue_in.isReady()) {
 397       peek(dmaRequestQueue_in, DMARequestMsg) {
 398         if (in_msg.Type == DMARequestType:READ) {
 399           trigger(Event:DMA_READ, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
 400         } else if (in_msg.Type == DMARequestType:WRITE) {
 401           if (getDirectoryEntry(in_msg.LineAddress).Tokens == max_tokens()) {
 402             trigger(Event:DMA_WRITE_All_Tokens, in_msg.LineAddress,
 403                     TBEs[in_msg.LineAddress]);
 404           } else {
 405             trigger(Event:DMA_WRITE, in_msg.LineAddress,
 406                     TBEs[in_msg.LineAddress]);
 407           }
 408         } else {
 409           error("Invalid message");
 410         }
 411       }
 412     }
 413   }
 414
 415   // Actions
 416
 417   action(a_sendTokens, "a", desc="Send tokens to requestor") {
 418     // Only send a message if we have tokens to send
 419     if (getDirectoryEntry(address).Tokens > 0) {
 420       peek(requestNetwork_in, RequestMsg) {
 421         // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
 422         enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME?
 423           out_msg.Address := address;
 424           out_msg.Type := CoherenceResponseType:ACK;
 425           out_msg.Sender := machineID;
 426           out_msg.Destination.add(in_msg.Requestor);
 427           out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
 428           out_msg.MessageSize := MessageSizeType:Response_Control;
 429         }
 430       }
 431       getDirectoryEntry(address).Tokens := 0;
 432     }
 433   }
 434
 435   action(px_tryIssuingPersistentGETXRequest, "px", desc="...") {
 436     if (okToIssueStarving(address, machineID) && (starving == false)) {
 437       enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
 438         out_msg.Address := address;
 439         out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
 440         out_msg.Requestor := machineID;
 441         out_msg.Destination.broadcast(MachineType:L1Cache);
 442
 443         //
 444         // Currently the configuration system limits the system to only one
 445         // chip.  Therefore, if we assume one shared L2 cache, then only one
 446         // pertinent L2 cache exist.
 447         //
 448         //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 449
 450         out_msg.Destination.add(mapAddressToRange(address,
 451                                                   MachineType:L2Cache,
 452                                                   l2_select_low_bit,
 453                                                   l2_select_num_bits));
 454
 455         out_msg.Destination.add(map_Address_to_Directory(address));
 456         out_msg.MessageSize := MessageSizeType:Persistent_Control;
 457         out_msg.Prefetch := PrefetchBit:No;
 458         out_msg.AccessMode := RubyAccessMode:Supervisor;
 459       }
 460       markPersistentEntries(address);
 461       starving := true;
 462
 463       tbe.WentPersistent := true;
 464
 465       // Do not schedule a wakeup, a persistent requests will always complete
 466     } else {
 467
 468       // We'd like to issue a persistent request, but are not allowed
 469       // to issue a P.R. right now.  This, we do not increment the
 470       // IssueCount.
 471
 472       // Set a wakeup timer
 473       reissueTimerTable.set(address, 10);
 474     }
 475   }
 476
 477   action(bw_broadcastWrite, "bw", desc="Broadcast GETX if we need tokens") {
 478     peek(dmaRequestQueue_in, DMARequestMsg) {
 479       //
 480       // Assser that we only send message if we don't already have all the tokens
 481       //
 482       assert(getDirectoryEntry(address).Tokens != max_tokens());
 483       enqueue(requestNetwork_out, RequestMsg, latency = "1") {
 484         out_msg.Address := address;
 485         out_msg.Type := CoherenceRequestType:GETX;
 486         out_msg.Requestor := machineID;
 487
 488         //
 489         // Since only one chip, assuming all L1 caches are local
 490         //
 491         out_msg.Destination.broadcast(MachineType:L1Cache);
 492         out_msg.Destination.add(mapAddressToRange(address,
 493                                                   MachineType:L2Cache,
 494                                                   l2_select_low_bit,
 495                                                   l2_select_num_bits));
 496
 497         out_msg.RetryNum := 0;
 498         out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 499         out_msg.Prefetch := PrefetchBit:No;
 500         out_msg.AccessMode := RubyAccessMode:Supervisor;
 501       }
 502     }
 503   }
 504
 505   action(ps_tryIssuingPersistentGETSRequest, "ps", desc="...") {
 506     if (okToIssueStarving(address, machineID) && (starving == false)) {
 507       enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
 508         out_msg.Address := address;
 509         out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
 510         out_msg.Requestor := machineID;
 511         out_msg.Destination.broadcast(MachineType:L1Cache);
 512
 513         //
 514         // Currently the configuration system limits the system to only one
 515         // chip.  Therefore, if we assume one shared L2 cache, then only one
 516         // pertinent L2 cache exist.
 517         //
 518         //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 519
 520         out_msg.Destination.add(mapAddressToRange(address,
 521                                                   MachineType:L2Cache,
 522                                                   l2_select_low_bit,
 523                                                   l2_select_num_bits));
 524
 525         out_msg.Destination.add(map_Address_to_Directory(address));
 526         out_msg.MessageSize := MessageSizeType:Persistent_Control;
 527         out_msg.Prefetch := PrefetchBit:No;
 528         out_msg.AccessMode := RubyAccessMode:Supervisor;
 529       }
 530       markPersistentEntries(address);
 531       starving := true;
 532
 533       tbe.WentPersistent := true;
 534
 535       // Do not schedule a wakeup, a persistent requests will always complete
 536     } else {
 537
 538       // We'd like to issue a persistent request, but are not allowed
 539       // to issue a P.R. right now.  This, we do not increment the
 540       // IssueCount.
 541
 542       // Set a wakeup timer
 543       reissueTimerTable.set(address, 10);
 544     }
 545   }
 546
 547   action(br_broadcastRead, "br", desc="Broadcast GETS for data") {
 548     peek(dmaRequestQueue_in, DMARequestMsg) {
 549       enqueue(requestNetwork_out, RequestMsg, latency = "1") {
 550         out_msg.Address := address;
 551         out_msg.Type := CoherenceRequestType:GETS;
 552         out_msg.Requestor := machineID;
 553
 554         //
 555         // Since only one chip, assuming all L1 caches are local
 556         //
 557         out_msg.Destination.broadcast(MachineType:L1Cache);
 558         out_msg.Destination.add(mapAddressToRange(address,
 559                                                   MachineType:L2Cache,
 560                                                   l2_select_low_bit,
 561                                                   l2_select_num_bits));
 562
 563         out_msg.RetryNum := 0;
 564         out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 565         out_msg.Prefetch := PrefetchBit:No;
 566         out_msg.AccessMode := RubyAccessMode:Supervisor;
 567       }
 568     }
 569   }
 570
 571   action(aa_sendTokensToStarver, "\a", desc="Send tokens to starver") {
 572     // Only send a message if we have tokens to send
 573     if (getDirectoryEntry(address).Tokens > 0) {
 574       // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
 575       enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME?
 576         out_msg.Address := address;
 577         out_msg.Type := CoherenceResponseType:ACK;
 578         out_msg.Sender := machineID;
 579         out_msg.Destination.add(persistentTable.findSmallest(address));
 580         out_msg.Tokens := getDirectoryEntry(address).Tokens;
 581         out_msg.MessageSize := MessageSizeType:Response_Control;
 582       }
 583       getDirectoryEntry(address).Tokens := 0;
 584     }
 585   }
 586
 587   action(d_sendMemoryDataWithAllTokens, "d", desc="Send data and tokens to requestor") {
 588     peek(memQueue_in, MemoryMsg) {
 589       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 590         out_msg.Address := address;
 591         out_msg.Type := CoherenceResponseType:DATA_OWNER;
 592         out_msg.Sender := machineID;
 593         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
 594         assert(getDirectoryEntry(address).Tokens > 0);
 595         out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
 596         out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
 597         out_msg.Dirty := false;
 598         out_msg.MessageSize := MessageSizeType:Response_Data;
 599       }
 600     }
 601     getDirectoryEntry(address).Tokens := 0;
 602   }
 603
 604   action(dd_sendMemDataToStarver, "\d", desc="Send data and tokens to starver") {
 605     peek(memQueue_in, MemoryMsg) {
 606       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 607         out_msg.Address := address;
 608         out_msg.Type := CoherenceResponseType:DATA_OWNER;
 609         out_msg.Sender := machineID;
 610         out_msg.Destination.add(persistentTable.findSmallest(address));
 611         assert(getDirectoryEntry(address).Tokens > 0);
 612         out_msg.Tokens := getDirectoryEntry(address).Tokens;
 613         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
 614         out_msg.Dirty := false;
 615         out_msg.MessageSize := MessageSizeType:Response_Data;
 616       }
 617     }
 618     getDirectoryEntry(address).Tokens := 0;
 619   }
 620
 621   action(de_sendTbeDataToStarver, "de", desc="Send data and tokens to starver") {
 622     enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 623       out_msg.Address := address;
 624       out_msg.Type := CoherenceResponseType:DATA_OWNER;
 625       out_msg.Sender := machineID;
 626       out_msg.Destination.add(persistentTable.findSmallest(address));
 627       assert(getDirectoryEntry(address).Tokens > 0);
 628       out_msg.Tokens := getDirectoryEntry(address).Tokens;
 629       out_msg.DataBlk := tbe.DataBlk;
 630       out_msg.Dirty := false;
 631       out_msg.MessageSize := MessageSizeType:Response_Data;
 632     }
 633     getDirectoryEntry(address).Tokens := 0;
 634   }
 635
 636   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
 637     peek(requestNetwork_in, RequestMsg) {
 638       enqueue(memQueue_out, MemoryMsg, latency="1") {
 639         out_msg.Address := address;
 640         out_msg.Type := MemoryRequestType:MEMORY_READ;
 641         out_msg.Sender := machineID;
 642         out_msg.OriginalRequestorMachId := in_msg.Requestor;
 643         out_msg.MessageSize := in_msg.MessageSize;
 644         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
 645         DPRINTF(RubySlicc, "%s\n", out_msg);
 646       }
 647     }
 648   }
 649
 650   action(qp_queueMemoryForPersistent, "qp", desc="Queue off-chip fetch request") {
 651     enqueue(memQueue_out, MemoryMsg, latency="1") {
 652       out_msg.Address := address;
 653       out_msg.Type := MemoryRequestType:MEMORY_READ;
 654       out_msg.Sender := machineID;
 655       out_msg.OriginalRequestorMachId := persistentTable.findSmallest(address);
 656       out_msg.MessageSize := MessageSizeType:Request_Control;
 657       out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
 658       DPRINTF(RubySlicc, "%s\n", out_msg);
 659     }
 660   }
 661
 662   action(fd_memoryDma, "fd", desc="Queue off-chip fetch request") {
 663     peek(dmaRequestQueue_in, DMARequestMsg) {
 664       enqueue(memQueue_out, MemoryMsg, latency="1") {
 665         out_msg.Address := address;
 666         out_msg.Type := MemoryRequestType:MEMORY_READ;
 667         out_msg.Sender := machineID;
 668         out_msg.OriginalRequestorMachId := in_msg.Requestor;
 669         out_msg.MessageSize := in_msg.MessageSize;
 670         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
 671         DPRINTF(RubySlicc, "%s\n", out_msg);
 672       }
 673     }
 674   }
 675
 676   action(lq_queueMemoryWbRequest, "lq", desc="Write data to memory") {
 677     enqueue(memQueue_out, MemoryMsg, latency="1") {
 678       out_msg.Address := address;
 679       out_msg.Type := MemoryRequestType:MEMORY_WB;
 680       DPRINTF(RubySlicc, "%s\n", out_msg);
 681     }
 682   }
 683
 684   action(ld_queueMemoryDmaWriteFromTbe, "ld", desc="Write DMA data to memory") {
 685     enqueue(memQueue_out, MemoryMsg, latency="1") {
 686       out_msg.Address := address;
 687       out_msg.Type := MemoryRequestType:MEMORY_WB;
 688       // first, initialize the data blk to the current version of system memory
 689       out_msg.DataBlk := tbe.DataBlk;
 690       // then add the dma write data
 691       out_msg.DataBlk.copyPartial(tbe.DmaDataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
 692       DPRINTF(RubySlicc, "%s\n", out_msg);
 693     }
 694   }
 695
 696   action(lr_queueMemoryDmaReadWriteback, "lr", desc="Write DMA data from read to memory") {
 697     enqueue(memQueue_out, MemoryMsg, latency="1") {
 698       out_msg.Address := address;
 699       out_msg.Type := MemoryRequestType:MEMORY_WB;
 700       // first, initialize the data blk to the current version of system memory
 701       out_msg.DataBlk := tbe.DataBlk;
 702       DPRINTF(RubySlicc, "%s\n", out_msg);
 703     }
 704   }
 705
 706   action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
 707     peek(dmaRequestQueue_in, DMARequestMsg) {
 708       TBEs.allocate(address);
 709       set_tbe(TBEs[address]);
 710       tbe.DmaDataBlk := in_msg.DataBlk;
 711       tbe.PhysicalAddress := in_msg.PhysicalAddress;
 712       tbe.Len := in_msg.Len;
 713       tbe.DmaRequestor := in_msg.Requestor;
 714       tbe.WentPersistent := false;
 715     }
 716   }
 717
 718   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 719
 720     if (tbe.WentPersistent) {
 721       assert(starving == true);
 722
 723       enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
 724         out_msg.Address := address;
 725         out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
 726         out_msg.Requestor := machineID;
 727         out_msg.Destination.broadcast(MachineType:L1Cache);
 728
 729         //
 730         // Currently the configuration system limits the system to only one
 731         // chip.  Therefore, if we assume one shared L2 cache, then only one
 732         // pertinent L2 cache exist.
 733         //
 734         //out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
 735
 736         out_msg.Destination.add(mapAddressToRange(address,
 737                                                   MachineType:L2Cache,
 738                                                   l2_select_low_bit,
 739                                                   l2_select_num_bits));
 740
 741         out_msg.Destination.add(map_Address_to_Directory(address));
 742         out_msg.MessageSize := MessageSizeType:Persistent_Control;
 743       }
 744       starving := false;
 745     }
 746
 747     TBEs.deallocate(address);
 748     unset_tbe();
 749   }
 750
 751   action(rd_recordDataInTbe, "rd", desc="Record data in TBE") {
 752     peek(responseNetwork_in, ResponseMsg) {
 753       tbe.DataBlk := in_msg.DataBlk;
 754     }
 755   }
 756
 757   action(cd_writeCleanDataToTbe, "cd", desc="Write clean memory data to TBE") {
 758     tbe.DataBlk := getDirectoryEntry(address).DataBlk;
 759   }
 760
 761   action(dwt_writeDmaDataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
 762     getDirectoryEntry(address).DataBlk := tbe.DataBlk;
 763     getDirectoryEntry(address).DataBlk.copyPartial(tbe.DmaDataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
 764   }
 765
 766   action(f_incrementTokens, "f", desc="Increment the number of tokens we're tracking") {
 767     peek(responseNetwork_in, ResponseMsg) {
 768       assert(in_msg.Tokens >= 1);
 769       getDirectoryEntry(address).Tokens := getDirectoryEntry(address).Tokens + in_msg.Tokens;
 770     }
 771   }
 772
 773   action(aat_assertAllTokens, "aat", desc="assert that we have all tokens") {
 774     assert(getDirectoryEntry(address).Tokens == max_tokens());
 775   }
 776
 777   action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
 778     requestNetwork_in.dequeue();
 779   }
 780
 781   action(z_recycleRequest, "z", desc="Recycle the request queue") {
 782     requestNetwork_in.recycle();
 783   }
 784
 785   action(k_popIncomingResponseQueue, "k", desc="Pop incoming response queue") {
 786     responseNetwork_in.dequeue();
 787   }
 788
 789   action(kz_recycleResponse, "kz", desc="Recycle incoming response queue") {
 790     responseNetwork_in.recycle();
 791   }
 792
 793   action(l_popIncomingPersistentQueue, "l", desc="Pop incoming persistent queue") {
 794     persistentNetwork_in.dequeue();
 795   }
 796
 797   action(p_popDmaRequestQueue, "pd", desc="pop dma request queue") {
 798     dmaRequestQueue_in.dequeue();
 799   }
 800
 801   action(y_recycleDmaRequestQueue, "y", desc="recycle dma request queue") {
 802     dmaRequestQueue_in.recycle();
 803   }
 804
 805   action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
 806     memQueue_in.dequeue();
 807   }
 808
 809   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
 810     peek(responseNetwork_in, ResponseMsg) {
 811       getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
 812       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
 813               in_msg.Address, in_msg.DataBlk);
 814     }
 815   }
 816
 817   action(n_checkData, "n", desc="Check incoming clean data message") {
 818     peek(responseNetwork_in, ResponseMsg) {
 819       assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
 820     }
 821   }
 822
 823   action(r_bounceResponse, "r", desc="Bounce response to starving processor") {
 824     peek(responseNetwork_in, ResponseMsg) {
 825       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 826         out_msg.Address := address;
 827         out_msg.Type := in_msg.Type;
 828         out_msg.Sender := machineID;
 829         out_msg.Destination.add(persistentTable.findSmallest(address));
 830         out_msg.Tokens := in_msg.Tokens;
 831         out_msg.MessageSize := in_msg.MessageSize;
 832         out_msg.DataBlk := in_msg.DataBlk;
 833         out_msg.Dirty := in_msg.Dirty;
 834       }
 835     }
 836   }
 837
 838   action(rs_resetScheduleTimeout, "rs", desc="Reschedule Schedule Timeout") {
 839     //
 840     // currently only support a fixed timeout latency
 841     //
 842     if (reissueTimerTable.isSet(address)) {
 843       reissueTimerTable.unset(address);
 844       reissueTimerTable.set(address, fixed_timeout_latency);
 845     }
 846   }
 847
 848   action(st_scheduleTimeout, "st", desc="Schedule Timeout") {
 849     //
 850     // currently only support a fixed timeout latency
 851     //
 852     reissueTimerTable.set(address, fixed_timeout_latency);
 853   }
 854
 855   action(ut_unsetReissueTimer, "ut", desc="Unset reissue timer.") {
 856     if (reissueTimerTable.isSet(address)) {
 857       reissueTimerTable.unset(address);
 858     }
 859   }
 860
 861   action(bd_bounceDatalessOwnerToken, "bd", desc="Bounce clean owner token to starving processor") {
 862     peek(responseNetwork_in, ResponseMsg) {
 863       assert(in_msg.Type == CoherenceResponseType:ACK_OWNER);
 864       assert(in_msg.Dirty == false);
 865       assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
 866
 867       // NOTE: The following check would not be valid in a real
 868       // implementation.  We include the data in the "dataless"
 869       // message so we can assert the clean data matches the datablock
 870       // in memory
 871       assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
 872
 873       // Bounce the message, but "re-associate" the data and the owner
 874       // token.  In essence we're converting an ACK_OWNER message to a
 875       // DATA_OWNER message, keeping the number of tokens the same.
 876       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 877         out_msg.Address := address;
 878         out_msg.Type := CoherenceResponseType:DATA_OWNER;
 879         out_msg.Sender := machineID;
 880         out_msg.Destination.add(persistentTable.findSmallest(address));
 881         out_msg.Tokens := in_msg.Tokens;
 882         out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
 883         out_msg.Dirty := in_msg.Dirty;
 884         out_msg.MessageSize := MessageSizeType:Response_Data;
 885       }
 886     }
 887   }
 888
 889   action(da_sendDmaAck, "da", desc="Send Ack to DMA controller") {
 890     enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
 891       out_msg.PhysicalAddress := address;
 892       out_msg.LineAddress := address;
 893       out_msg.Type := DMAResponseType:ACK;
 894       out_msg.Destination.add(tbe.DmaRequestor);
 895       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 896     }
 897   }
 898
 899   action(dm_sendMemoryDataToDma, "dm", desc="Send Data to DMA controller from memory") {
 900     peek(memQueue_in, MemoryMsg) {
 901       enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
 902         out_msg.PhysicalAddress := address;
 903         out_msg.LineAddress := address;
 904         out_msg.Type := DMAResponseType:DATA;
 905         //
 906         // we send the entire data block and rely on the dma controller to
 907         // split it up if need be
 908         //
 909         out_msg.DataBlk := in_msg.DataBlk;
 910         out_msg.Destination.add(tbe.DmaRequestor);
 911         out_msg.MessageSize := MessageSizeType:Response_Data;
 912       }
 913     }
 914   }
 915
 916   action(dd_sendDmaData, "dd", desc="Send Data to DMA controller") {
 917     peek(responseNetwork_in, ResponseMsg) {
 918       enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
 919         out_msg.PhysicalAddress := address;
 920         out_msg.LineAddress := address;
 921         out_msg.Type := DMAResponseType:DATA;
 922         //
 923         // we send the entire data block and rely on the dma controller to
 924         // split it up if need be
 925         //
 926         out_msg.DataBlk := in_msg.DataBlk;
 927         out_msg.Destination.add(tbe.DmaRequestor);
 928         out_msg.MessageSize := MessageSizeType:Response_Data;
 929       }
 930     }
 931   }
 932
 933   // TRANSITIONS
 934
 935   //
 936   // Trans. from base state O
 937   // the directory has valid data
 938   //
 939   transition(O, GETX, NO_W) {
 940     qf_queueMemoryFetchRequest;
 941     j_popIncomingRequestQueue;
 942   }
 943
 944   transition(O, DMA_WRITE, O_DW) {
 945     vd_allocateDmaRequestInTBE;
 946     cd_writeCleanDataToTbe;
 947     bw_broadcastWrite;
 948     st_scheduleTimeout;
 949     p_popDmaRequestQueue;
 950   }
 951
 952   transition(O, DMA_WRITE_All_Tokens, O_DW_W) {
 953     vd_allocateDmaRequestInTBE;
 954     cd_writeCleanDataToTbe;
 955     dwt_writeDmaDataFromTBE;
 956     ld_queueMemoryDmaWriteFromTbe;
 957     p_popDmaRequestQueue;
 958   }
 959
 960   transition(O, GETS, NO_W) {
 961     qf_queueMemoryFetchRequest;
 962     j_popIncomingRequestQueue;
 963   }
 964
 965   transition(O, DMA_READ, O_DR_W) {
 966     vd_allocateDmaRequestInTBE;
 967     fd_memoryDma;
 968     st_scheduleTimeout;
 969     p_popDmaRequestQueue;
 970   }
 971
 972   transition(O, Lockdown, L_O_W) {
 973     qp_queueMemoryForPersistent;
 974     l_popIncomingPersistentQueue;
 975   }
 976
 977   transition(O, {Tokens, Ack_All_Tokens}) {
 978     f_incrementTokens;
 979     k_popIncomingResponseQueue;
 980   }
 981
 982   transition(O, {Data_Owner, Data_All_Tokens}) {
 983     n_checkData;
 984     f_incrementTokens;
 985     k_popIncomingResponseQueue;
 986   }
 987
 988   transition({O, NO}, Unlockdown) {
 989     l_popIncomingPersistentQueue;
 990   }
 991
 992   //
 993   // transitioning to Owner, waiting for memory before DMA ack
 994   // All other events should recycle/stall
 995   //
 996   transition(O_DR_W, Memory_Data, O) {
 997     dm_sendMemoryDataToDma;
 998     ut_unsetReissueTimer;
 999     s_deallocateTBE;
1000     l_popMemQueue;
1001   }
1002
1003   //
1004   // issued GETX for DMA write, waiting for all tokens
1005   //
1006   transition(O_DW, Request_Timeout) {
1007     ut_unsetReissueTimer;
1008     px_tryIssuingPersistentGETXRequest;
1009   }
1010
1011   transition(O_DW, Tokens) {
1012     f_incrementTokens;
1013     k_popIncomingResponseQueue;
1014   }
1015
1016   transition(O_DW, Data_Owner) {
1017     f_incrementTokens;
1018     rd_recordDataInTbe;
1019     k_popIncomingResponseQueue;
1020   }
1021
1022   transition(O_DW, Ack_Owner) {
1023     f_incrementTokens;
1024     cd_writeCleanDataToTbe;
1025     k_popIncomingResponseQueue;
1026   }
1027
1028   transition(O_DW, Lockdown, DW_L) {
1029     de_sendTbeDataToStarver;
1030     l_popIncomingPersistentQueue;
1031   }
1032
1033   transition({NO_DW, O_DW}, Data_All_Tokens, O_DW_W) {
1034     f_incrementTokens;
1035     rd_recordDataInTbe;
1036     dwt_writeDmaDataFromTBE;
1037     ld_queueMemoryDmaWriteFromTbe;
1038     ut_unsetReissueTimer;
1039     k_popIncomingResponseQueue;
1040   }
1041
1042   transition(O_DW, Ack_All_Tokens, O_DW_W) {
1043     f_incrementTokens;
1044     dwt_writeDmaDataFromTBE;
1045     ld_queueMemoryDmaWriteFromTbe;
1046     ut_unsetReissueTimer;
1047     k_popIncomingResponseQueue;
1048   }
1049
1050   transition(O_DW, Ack_Owner_All_Tokens, O_DW_W) {
1051     f_incrementTokens;
1052     cd_writeCleanDataToTbe;
1053     dwt_writeDmaDataFromTBE;
1054     ld_queueMemoryDmaWriteFromTbe;
1055     ut_unsetReissueTimer;
1056     k_popIncomingResponseQueue;
1057   }
1058
1059   transition(O_DW_W, Memory_Ack, O) {
1060     da_sendDmaAck;
1061     s_deallocateTBE;
1062     l_popMemQueue;
1063   }
1064
1065   //
1066   // Trans. from NO
1067   // The direcotry does not have valid data, but may have some tokens
1068   //
1069   transition(NO, GETX) {
1070     a_sendTokens;
1071     j_popIncomingRequestQueue;
1072   }
1073
1074   transition(NO, DMA_WRITE, NO_DW) {
1075     vd_allocateDmaRequestInTBE;
1076     bw_broadcastWrite;
1077     st_scheduleTimeout;
1078     p_popDmaRequestQueue;
1079   }
1080
1081   transition(NO, GETS) {
1082     j_popIncomingRequestQueue;
1083   }
1084
1085   transition(NO, DMA_READ, NO_DR) {
1086     vd_allocateDmaRequestInTBE;
1087     br_broadcastRead;
1088     st_scheduleTimeout;
1089     p_popDmaRequestQueue;
1090   }
1091
1092   transition(NO, Lockdown, L) {
1093     aa_sendTokensToStarver;
1094     l_popIncomingPersistentQueue;
1095   }
1096
1097   transition(NO, {Data_Owner, Data_All_Tokens}, O_W) {
1098     m_writeDataToMemory;
1099     f_incrementTokens;
1100     lq_queueMemoryWbRequest;
1101     k_popIncomingResponseQueue;
1102   }
1103
1104   transition(NO, {Ack_Owner, Ack_Owner_All_Tokens}, O) {
1105     n_checkData;
1106     f_incrementTokens;
1107     k_popIncomingResponseQueue;
1108   }
1109
1110   transition(NO, Tokens) {
1111     f_incrementTokens;
1112     k_popIncomingResponseQueue;
1113   }
1114
1115   transition(NO_W, Memory_Data, NO) {
1116     d_sendMemoryDataWithAllTokens;
1117     l_popMemQueue;
1118   }
1119
1120   // Trans. from NO_DW
1121   transition(NO_DW, Request_Timeout) {
1122     ut_unsetReissueTimer;
1123     px_tryIssuingPersistentGETXRequest;
1124   }
1125
1126   transition(NO_DW, Lockdown, DW_L) {
1127     aa_sendTokensToStarver;
1128     l_popIncomingPersistentQueue;
1129   }
1130
1131   // Note: NO_DW, Data_All_Tokens transition is combined with O_DW
1132   // Note: NO_DW should not receive the action Ack_All_Tokens because the
1133   // directory does not have valid data
1134
1135   transition(NO_DW, Data_Owner, O_DW) {
1136     f_incrementTokens;
1137     rd_recordDataInTbe;
1138     k_popIncomingResponseQueue;
1139   }
1140
1141   transition({NO_DW, NO_DR}, Tokens) {
1142     f_incrementTokens;
1143     k_popIncomingResponseQueue;
1144   }
1145
1146   // Trans. from NO_DR
1147   transition(NO_DR, Request_Timeout) {
1148     ut_unsetReissueTimer;
1149     ps_tryIssuingPersistentGETSRequest;
1150   }
1151
1152   transition(NO_DR, Lockdown, DR_L) {
1153     aa_sendTokensToStarver;
1154     l_popIncomingPersistentQueue;
1155   }
1156
1157   transition(NO_DR, {Data_Owner, Data_All_Tokens}, O_W) {
1158     m_writeDataToMemory;
1159     f_incrementTokens;
1160     dd_sendDmaData;
1161     lr_queueMemoryDmaReadWriteback;
1162     ut_unsetReissueTimer;
1163     s_deallocateTBE;
1164     k_popIncomingResponseQueue;
1165   }
1166
1167   // Trans. from L
1168   transition({L, DW_L, DR_L}, {GETX, GETS}) {
1169     j_popIncomingRequestQueue;
1170   }
1171
1172   transition({L, DW_L, DR_L, L_O_W, L_NO_W, DR_L_W, DW_L_W}, Lockdown) {
1173     l_popIncomingPersistentQueue;
1174   }
1175
1176   //
1177   // Received data for lockdown blocks
1178   // For blocks with outstanding dma requests to them
1179   // ...we could change this to write the data to memory and send it cleanly
1180   // ...we could also proactively complete our DMA requests
1181   // However, to keep my mind from spinning out-of-control, we won't for now :)
1182   //
1183   transition({DW_L, DR_L, L}, {Data_Owner, Data_All_Tokens}) {
1184     r_bounceResponse;
1185     k_popIncomingResponseQueue;
1186   }
1187
1188   transition({DW_L, DR_L, L}, Tokens) {
1189     r_bounceResponse;
1190     k_popIncomingResponseQueue;
1191   }
1192
1193   transition({DW_L, DR_L, L}, {Ack_Owner_All_Tokens, Ack_Owner}) {
1194     bd_bounceDatalessOwnerToken;
1195     k_popIncomingResponseQueue;
1196   }
1197
1198   transition(L, {Unlockdown, Own_Lock_or_Unlock}, NO) {
1199     l_popIncomingPersistentQueue;
1200   }
1201
1202   transition(L, Own_Lock_or_Unlock_Tokens, O) {
1203     l_popIncomingPersistentQueue;
1204   }
1205
1206   transition({L_NO_W, L_O_W}, Memory_Data, L) {
1207     dd_sendMemDataToStarver;
1208     l_popMemQueue;
1209   }
1210
1211   transition(L_O_W, Memory_Ack) {
1212     qp_queueMemoryForPersistent;
1213     l_popMemQueue;
1214   }
1215
1216   transition(L_O_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, O_W) {
1217     l_popIncomingPersistentQueue;
1218   }
1219
1220   transition(L_NO_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, NO_W) {
1221     l_popIncomingPersistentQueue;
1222   }
1223
1224   transition(DR_L_W, Memory_Data, DR_L) {
1225     dd_sendMemDataToStarver;
1226     l_popMemQueue;
1227   }
1228
1229   transition(DW_L_W, Memory_Ack, L) {
1230     aat_assertAllTokens;
1231     da_sendDmaAck;
1232     s_deallocateTBE;
1233     dd_sendMemDataToStarver;
1234     l_popMemQueue;
1235   }
1236
1237   transition(DW_L, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, NO_DW) {
1238     l_popIncomingPersistentQueue;
1239   }
1240
1241   transition(DR_L_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, O_DR_W) {
1242     l_popIncomingPersistentQueue;
1243   }
1244
1245   transition(DW_L_W, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, O_DW_W) {
1246     l_popIncomingPersistentQueue;
1247   }
1248
1249   transition({DW_L, DR_L_W, DW_L_W}, Request_Timeout) {
1250     ut_unsetReissueTimer;
1251     px_tryIssuingPersistentGETXRequest;
1252   }
1253
1254   transition(DR_L, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}, NO_DR) {
1255     l_popIncomingPersistentQueue;
1256   }
1257
1258   transition(DR_L, Request_Timeout) {
1259     ut_unsetReissueTimer;
1260     ps_tryIssuingPersistentGETSRequest;
1261   }
1262
1263   //
1264   // The O_W + Memory_Data > O transistion is confusing, but it can happen if a
1265   // presistent request is issued and resolve before memory returns with data
1266   //
1267   transition(O_W, {Memory_Ack, Memory_Data}, O) {
1268     l_popMemQueue;
1269   }
1270
1271   transition({O, NO}, {Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}) {
1272     l_popIncomingPersistentQueue;
1273   }
1274
1275   // Blocked states
1276   transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, DW_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR}, {GETX, GETS}) {
1277     z_recycleRequest;
1278   }
1279
1280   transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, DW_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR, L, DW_L, DR_L}, {DMA_READ, DMA_WRITE, DMA_WRITE_All_Tokens}) {
1281     y_recycleDmaRequestQueue;
1282   }
1283
1284   transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, DW_L_W, O_DW_W, O_DR_W}, {Data_Owner, Ack_Owner, Tokens, Data_All_Tokens, Ack_All_Tokens}) {
1285     kz_recycleResponse;
1286   }
1287
1288   //
1289   // If we receive a request timeout while waiting for memory, it is likely that
1290   // the request will be satisfied and issuing a presistent request will do us
1291   // no good.  Just wait.
1292   //
1293   transition({O_DW_W, O_DR_W}, Request_Timeout) {
1294     rs_resetScheduleTimeout;
1295   }
1296
1297   transition(NO_W, Lockdown, L_NO_W) {
1298     l_popIncomingPersistentQueue;
1299   }
1300
1301   transition(O_W, Lockdown, L_O_W) {
1302     l_popIncomingPersistentQueue;
1303   }
1304
1305   transition(O_DR_W, Lockdown, DR_L_W) {
1306     l_popIncomingPersistentQueue;
1307   }
1308
1309   transition(O_DW_W, Lockdown, DW_L_W) {
1310     l_popIncomingPersistentQueue;
1311   }
1312
1313   transition({NO_W, O_W, O_DR_W, O_DW_W, O_DW, NO_DR, NO_DW}, {Unlockdown, Own_Lock_or_Unlock, Own_Lock_or_Unlock_Tokens}) {
1314     l_popIncomingPersistentQueue;
1315   }
1316 }