2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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30 machine(DMA, "DMA Controller")
31 : DMASequencer * dma_sequencer;
32 Cycles request_latency := 6;
35 MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response";
36 MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request";
38 state_declaration(State, desc="DMA states", default="DMA_State_READY") {
39 READY, AccessPermission:Invalid, desc="Ready to accept a new request";
40 BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
41 BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
44 enumeration(Event, desc="DMA events") {
45 ReadRequest, desc="A new read request";
46 WriteRequest, desc="A new write request";
47 Data, desc="Data from a DMA memory read";
48 Ack, desc="DMA write to memory completed";
51 structure(DMASequencer, external="yes") {
53 void dataCallback(DataBlock);
56 MessageBuffer mandatoryQueue, ordered="false";
59 State getState(Address addr) {
62 void setState(Address addr, State state) {
66 AccessPermission getAccessPermission(Address addr) {
67 return AccessPermission:NotPresent;
70 void setAccessPermission(Address addr, State state) {
73 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
74 error("DMA Controller does not support getDataBlock function.\n");
77 out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
79 in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
80 if (dmaRequestQueue_in.isReady()) {
81 peek(dmaRequestQueue_in, SequencerMsg) {
82 if (in_msg.Type == SequencerRequestType:LD ) {
83 trigger(Event:ReadRequest, in_msg.LineAddress);
84 } else if (in_msg.Type == SequencerRequestType:ST) {
85 trigger(Event:WriteRequest, in_msg.LineAddress);
87 error("Invalid request type");
93 in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
94 if (dmaResponseQueue_in.isReady()) {
95 peek( dmaResponseQueue_in, DMAResponseMsg) {
96 if (in_msg.Type == DMAResponseType:ACK) {
97 trigger(Event:Ack, in_msg.LineAddress);
98 } else if (in_msg.Type == DMAResponseType:DATA) {
99 trigger(Event:Data, in_msg.LineAddress);
101 error("Invalid response type");
107 action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
108 peek(dmaRequestQueue_in, SequencerMsg) {
109 enqueue(reqToDirectory_out, DMARequestMsg, request_latency) {
110 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
111 out_msg.LineAddress := in_msg.LineAddress;
112 out_msg.Type := DMARequestType:READ;
113 out_msg.Requestor := machineID;
114 out_msg.DataBlk := in_msg.DataBlk;
115 out_msg.Len := in_msg.Len;
116 out_msg.Destination.add(map_Address_to_Directory(address));
117 out_msg.MessageSize := MessageSizeType:Writeback_Control;
122 action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
123 peek(dmaRequestQueue_in, SequencerMsg) {
124 enqueue(reqToDirectory_out, DMARequestMsg, request_latency) {
125 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
126 out_msg.LineAddress := in_msg.LineAddress;
127 out_msg.Type := DMARequestType:WRITE;
128 out_msg.Requestor := machineID;
129 out_msg.DataBlk := in_msg.DataBlk;
130 out_msg.Len := in_msg.Len;
131 out_msg.Destination.add(map_Address_to_Directory(address));
132 out_msg.MessageSize := MessageSizeType:Writeback_Control;
137 action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
138 peek (dmaResponseQueue_in, DMAResponseMsg) {
139 dma_sequencer.ackCallback();
143 action(d_dataCallback, "d", desc="Write data to dma sequencer") {
144 peek (dmaResponseQueue_in, DMAResponseMsg) {
145 dma_sequencer.dataCallback(in_msg.DataBlk);
149 action(p_popRequestQueue, "p", desc="Pop request queue") {
150 dmaRequestQueue_in.dequeue();
153 action(p_popResponseQueue, "\p", desc="Pop request queue") {
154 dmaResponseQueue_in.dequeue();
157 transition(READY, ReadRequest, BUSY_RD) {
162 transition(READY, WriteRequest, BUSY_WR) {
167 transition(BUSY_RD, Data, READY) {
172 transition(BUSY_WR, Ack, READY) {