src/mem/protocol/MOESI_hammer-cache.sm

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * AMD's contributions to the MOESI hammer protocol do not constitute an
  30  * endorsement of its similarity to any AMD products.
  31  *
  32  * Authors: Milo Martin
  33  *          Brad Beckmann
  34  */
  35
  36 machine(L1Cache, "AMD Hammer-like protocol")
  37 : Sequencer * sequencer,
  38   CacheMemory * L1IcacheMemory,
  39   CacheMemory * L1DcacheMemory,
  40   CacheMemory * L2cacheMemory,
  41   int cache_response_latency = 10,
  42   int issue_latency = 2,
  43   int l2_cache_hit_latency = 10,
  44   bool no_mig_atomic = true
  45 {
  46
  47   // NETWORK BUFFERS
  48   MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="false";
  49   MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="false";
  50   MessageBuffer unblockFromCache, network="To", virtual_network="5", ordered="false";
  51
  52   MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="false";
  53   MessageBuffer responseToCache, network="From", virtual_network="4", ordered="false";
  54
  55
  56   // STATES
  57   state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
  58     // Base states
  59     I, AccessPermission:Invalid, desc="Idle";
  60     S, AccessPermission:Read_Only, desc="Shared";
  61     O, AccessPermission:Read_Only, desc="Owned";
  62     M, AccessPermission:Read_Only, desc="Modified (dirty)";
  63     MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
  64
  65     // Transient States
  66     IM, AccessPermission:Busy, "IM", desc="Issued GetX";
  67     SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have a valid copy of the line";
  68     OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
  69     ISM, AccessPermission:Read_Only, "ISM", desc="Issued GetX, received valid data, waiting for all acks";
  70     M_W, AccessPermission:Read_Only, "M^W", desc="Issued GetS, received exclusive data";
  71     MM_W, AccessPermission:Read_Write, "MM^W", desc="Issued GetX, received exclusive data";
  72     IS, AccessPermission:Busy, "IS", desc="Issued GetS";
  73     SS, AccessPermission:Read_Only, "SS", desc="Issued GetS, received data, waiting for all acks";
  74     OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
  75     MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
  76     II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack";
  77     IT, AccessPermission:Busy, "IT", desc="Invalid block transferring to L1";
  78     ST, AccessPermission:Busy, "ST", desc="S block transferring to L1";
  79     OT, AccessPermission:Busy, "OT", desc="O block transferring to L1";
  80     MT, AccessPermission:Busy, "MT", desc="M block transferring to L1";
  81     MMT, AccessPermission:Busy, "MMT", desc="MM block transferring to L1";
  82   }
  83
  84   // EVENTS
  85   enumeration(Event, desc="Cache events") {
  86     Load,            desc="Load request from the processor";
  87     Ifetch,          desc="I-fetch request from the processor";
  88     Store,           desc="Store request from the processor";
  89     L2_Replacement,  desc="L2 Replacement";
  90     L1_to_L2,        desc="L1 to L2 transfer";
  91     Trigger_L2_to_L1D,  desc="Trigger L2 to L1-Data transfer";
  92     Trigger_L2_to_L1I,  desc="Trigger L2 to L1-Instruction transfer";
  93     Complete_L2_to_L1, desc="L2 to L1 transfer completed";
  94
  95     // Requests
  96     Other_GETX,      desc="A GetX from another processor";
  97     Other_GETS,      desc="A GetS from another processor";
  98     Merged_GETS,     desc="A Merged GetS from another processor";
  99     Other_GETS_No_Mig, desc="A GetS from another processor";
 100     NC_DMA_GETS,     desc="special GetS when only DMA exists";
 101     Invalidate,      desc="Invalidate block";
 102
 103     // Responses
 104     Ack,             desc="Received an ack message";
 105     Shared_Ack,      desc="Received an ack message, responder has a shared copy";
 106     Data,            desc="Received a data message";
 107     Shared_Data,     desc="Received a data message, responder has a shared copy";
 108     Exclusive_Data,  desc="Received a data message, responder had an exclusive copy, they gave it to us";
 109
 110     Writeback_Ack,   desc="Writeback O.K. from directory";
 111     Writeback_Nack,  desc="Writeback not O.K. from directory";
 112
 113     // Triggers
 114     All_acks,                  desc="Received all required data and message acks";
 115     All_acks_no_sharers,        desc="Received all acks and no other processor has a shared copy";
 116   }
 117
 118   // TYPES
 119
 120   // STRUCTURE DEFINITIONS
 121
 122   MessageBuffer mandatoryQueue, ordered="false";
 123
 124   // CacheEntry
 125   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 126     State CacheState,        desc="cache state";
 127     bool Dirty,              desc="Is the data dirty (different than memory)?";
 128     DataBlock DataBlk,       desc="data for the block";
 129     bool FromL2, default="false", desc="block just moved from L2";
 130     bool AtomicAccessed, default="false", desc="block just moved from L2";
 131   }
 132
 133   // TBE fields
 134   structure(TBE, desc="...") {
 135     State TBEState,          desc="Transient state";
 136     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 137     bool Dirty,              desc="Is the data dirty (different than memory)?";
 138     int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
 139     bool Sharers,            desc="On a GetS, did we find any other sharers in the system";
 140     bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks";
 141     MachineID LastResponder, desc="last machine to send a response for this request";
 142     MachineID CurOwner,      desc="current owner of the block, used for UnblockS responses";
 143     Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
 144     Time ForwardRequestTime, default="0", desc="time the dir forwarded the request";
 145     Time FirstResponseTime, default="0", desc="the time the first response was received";
 146   }
 147
 148   external_type(TBETable) {
 149     TBE lookup(Address);
 150     void allocate(Address);
 151     void deallocate(Address);
 152     bool isPresent(Address);
 153   }
 154
 155   TBETable TBEs, template_hack="<L1Cache_TBE>";
 156
 157   void set_cache_entry(AbstractCacheEntry b);
 158   void unset_cache_entry();
 159   void set_tbe(TBE b);
 160   void unset_tbe();
 161   void wakeUpAllBuffers();
 162   void wakeUpBuffers(Address a);
 163
 164   Entry getCacheEntry(Address address), return_by_pointer="yes" {
 165     Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
 166     if(is_valid(L2cache_entry)) {
 167       return L2cache_entry;
 168     }
 169
 170     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(address));
 171     if(is_valid(L1Dcache_entry)) {
 172       return L1Dcache_entry;
 173     }
 174
 175     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(address));
 176     return L1Icache_entry;
 177   }
 178
 179   Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
 180     Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
 181     return L2cache_entry;
 182   }
 183
 184   Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
 185     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(address));
 186     return L1Dcache_entry;
 187   }
 188
 189   Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
 190     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(address));
 191     return L1Icache_entry;
 192   }
 193
 194   State getState(TBE tbe, Entry cache_entry, Address addr) {
 195     if(is_valid(tbe)) {
 196       return tbe.TBEState;
 197     } else if (is_valid(cache_entry)) {
 198       return cache_entry.CacheState;
 199     }
 200     return State:I;
 201   }
 202
 203   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 204     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 205     assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 206     assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 207
 208     if (is_valid(tbe)) {
 209       tbe.TBEState := state;
 210     }
 211
 212     if (is_valid(cache_entry)) {
 213       cache_entry.CacheState := state;
 214     }
 215   }
 216
 217   Event mandatory_request_type_to_event(CacheRequestType type) {
 218     if (type == CacheRequestType:LD) {
 219       return Event:Load;
 220     } else if (type == CacheRequestType:IFETCH) {
 221       return Event:Ifetch;
 222     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 223       return Event:Store;
 224     } else {
 225       error("Invalid CacheRequestType");
 226     }
 227   }
 228
 229   GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
 230     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
 231       //
 232       // NOTE direct local hits should not call this
 233       //
 234       return GenericMachineType:L1Cache_wCC;
 235     } else {
 236       return ConvertMachToGenericMach(machineIDToMachineType(sender));
 237     }
 238   }
 239
 240   GenericMachineType testAndClearLocalHit(Entry cache_entry) {
 241     if (is_valid(cache_entry) && cache_entry.FromL2) {
 242       cache_entry.FromL2 := false;
 243       return GenericMachineType:L2Cache;
 244     } else {
 245       return GenericMachineType:L1Cache;
 246     }
 247   }
 248
 249   bool IsAtomicAccessed(Entry cache_entry) {
 250     assert(is_valid(cache_entry));
 251     return cache_entry.AtomicAccessed;
 252   }
 253
 254   MessageBuffer triggerQueue, ordered="false";
 255
 256   // ** OUT_PORTS **
 257
 258   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 259   out_port(responseNetwork_out, ResponseMsg, responseFromCache);
 260   out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
 261   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 262
 263   // ** IN_PORTS **
 264
 265   // Trigger Queue
 266   in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
 267     if (triggerQueue_in.isReady()) {
 268       peek(triggerQueue_in, TriggerMsg) {
 269
 270         Entry cache_entry := getCacheEntry(in_msg.Address);
 271         TBE tbe := TBEs[in_msg.Address];
 272
 273         if (in_msg.Type == TriggerType:L2_to_L1) {
 274           trigger(Event:Complete_L2_to_L1, in_msg.Address, cache_entry, tbe);
 275         } else if (in_msg.Type == TriggerType:ALL_ACKS) {
 276           trigger(Event:All_acks, in_msg.Address, cache_entry, tbe);
 277         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
 278           trigger(Event:All_acks_no_sharers, in_msg.Address, cache_entry, tbe);
 279         } else {
 280           error("Unexpected message");
 281         }
 282       }
 283     }
 284   }
 285
 286   // Nothing from the unblock network
 287
 288   // Response Network
 289   in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
 290     if (responseToCache_in.isReady()) {
 291       peek(responseToCache_in, ResponseMsg, block_on="Address") {
 292
 293         Entry cache_entry := getCacheEntry(in_msg.Address);
 294         TBE tbe := TBEs[in_msg.Address];
 295
 296         if (in_msg.Type == CoherenceResponseType:ACK) {
 297           trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
 298         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
 299           trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe);
 300         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 301           trigger(Event:Data, in_msg.Address, cache_entry, tbe);
 302         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 303           trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe);
 304         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 305           trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe);
 306         } else {
 307           error("Unexpected message");
 308         }
 309       }
 310     }
 311   }
 312
 313   // Forward Network
 314   in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
 315     if (forwardToCache_in.isReady()) {
 316       peek(forwardToCache_in, RequestMsg, block_on="Address") {
 317
 318         Entry cache_entry := getCacheEntry(in_msg.Address);
 319         TBE tbe := TBEs[in_msg.Address];
 320
 321         if (in_msg.Type == CoherenceRequestType:GETX) {
 322           trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe);
 323         } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
 324           trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe);
 325         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 326           if (machineCount(MachineType:L1Cache) > 1) {
 327             if (is_valid(cache_entry)) {
 328               if (IsAtomicAccessed(cache_entry) && no_mig_atomic) {
 329                 trigger(Event:Other_GETS_No_Mig, in_msg.Address, cache_entry, tbe);
 330               } else {
 331                 trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
 332               }
 333             } else {
 334               trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
 335             }
 336           } else {
 337             trigger(Event:NC_DMA_GETS, in_msg.Address, cache_entry, tbe);
 338           }
 339         } else if (in_msg.Type == CoherenceRequestType:INV) {
 340           trigger(Event:Invalidate, in_msg.Address, cache_entry, tbe);
 341         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 342           trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
 343         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 344           trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
 345         } else {
 346           error("Unexpected message");
 347         }
 348       }
 349     }
 350   }
 351
 352   // Nothing from the request network
 353
 354   // Mandatory Queue
 355   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
 356     if (mandatoryQueue_in.isReady()) {
 357       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 358
 359         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 360         TBE tbe := TBEs[in_msg.LineAddress];
 361
 362         if (in_msg.Type == CacheRequestType:IFETCH) {
 363           // ** INSTRUCTION ACCESS ***
 364
 365           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 366           if (is_valid(L1Icache_entry)) {
 367             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 368             trigger(mandatory_request_type_to_event(in_msg.Type),
 369                     in_msg.LineAddress, L1Icache_entry, tbe);
 370           } else {
 371             // Check to see if it is in the OTHER L1
 372             Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 373             if (is_valid(L1Dcache_entry)) {
 374               // The block is in the wrong L1, try to write it to the L2
 375               if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
 376                 trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
 377               } else {
 378                 Address l2_victim_addr := L2cacheMemory.cacheProbe(in_msg.LineAddress);
 379                 trigger(Event:L2_Replacement,
 380                         l2_victim_addr,
 381                         getL2CacheEntry(l2_victim_addr),
 382                         TBEs[l2_victim_addr]);
 383               }
 384             }
 385
 386             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 387               // L1 does't have the line, but we have space for it in the L1
 388
 389               Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
 390               if (is_valid(L2cache_entry)) {
 391                 // L2 has it (maybe not with the right permissions)
 392                 trigger(Event:Trigger_L2_to_L1I, in_msg.LineAddress,
 393                         L2cache_entry, tbe);
 394               } else {
 395                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 396                 trigger(mandatory_request_type_to_event(in_msg.Type),
 397                         in_msg.LineAddress, L1Icache_entry, tbe);
 398               }
 399             } else {
 400               // No room in the L1, so we need to make room
 401               Address l1i_victim_addr := L1IcacheMemory.cacheProbe(in_msg.LineAddress);
 402               if (L2cacheMemory.cacheAvail(l1i_victim_addr)) {
 403                 // The L2 has room, so we move the line from the L1 to the L2
 404                 trigger(Event:L1_to_L2,
 405                         l1i_victim_addr,
 406                         getL1ICacheEntry(l1i_victim_addr),
 407                         TBEs[l1i_victim_addr]);
 408               } else {
 409                 Address l2_victim_addr := L2cacheMemory.cacheProbe(l1i_victim_addr);
 410                 // The L2 does not have room, so we replace a line from the L2
 411                 trigger(Event:L2_Replacement,
 412                         l2_victim_addr,
 413                         getL2CacheEntry(l2_victim_addr),
 414                         TBEs[l2_victim_addr]);
 415               }
 416             }
 417           }
 418         } else {
 419           // *** DATA ACCESS ***
 420
 421           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 422           if (is_valid(L1Dcache_entry)) {
 423             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 424             trigger(mandatory_request_type_to_event(in_msg.Type),
 425                     in_msg.LineAddress, L1Dcache_entry, tbe);
 426           } else {
 427
 428             // Check to see if it is in the OTHER L1
 429             Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 430             if (is_valid(L1Icache_entry)) {
 431               // The block is in the wrong L1, try to write it to the L2
 432               if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
 433                 trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
 434               } else {
 435                 Address l2_victim_addr := L2cacheMemory.cacheProbe(in_msg.LineAddress);
 436                 trigger(Event:L2_Replacement,
 437                         l2_victim_addr,
 438                         getL2CacheEntry(l2_victim_addr),
 439                         TBEs[l2_victim_addr]);
 440               }
 441             }
 442
 443             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 444               // L1 does't have the line, but we have space for it in the L1
 445               Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
 446               if (is_valid(L2cache_entry)) {
 447                 // L2 has it (maybe not with the right permissions)
 448                 trigger(Event:Trigger_L2_to_L1D, in_msg.LineAddress,
 449                         L2cache_entry, tbe);
 450               } else {
 451                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 452                 trigger(mandatory_request_type_to_event(in_msg.Type),
 453                         in_msg.LineAddress, L1Dcache_entry, tbe);
 454               }
 455             } else {
 456               // No room in the L1, so we need to make room
 457               Address l1d_victim_addr := L1DcacheMemory.cacheProbe(in_msg.LineAddress);
 458               if (L2cacheMemory.cacheAvail(l1d_victim_addr)) {
 459                 // The L2 has room, so we move the line from the L1 to the L2
 460                 trigger(Event:L1_to_L2,
 461                         l1d_victim_addr,
 462                         getL1DCacheEntry(l1d_victim_addr),
 463                         TBEs[l1d_victim_addr]);
 464               } else {
 465                 Address l2_victim_addr := L2cacheMemory.cacheProbe(l1d_victim_addr);
 466                 // The L2 does not have room, so we replace a line from the L2
 467                 trigger(Event:L2_Replacement,
 468                         l2_victim_addr,
 469                         getL2CacheEntry(l2_victim_addr),
 470                         TBEs[l2_victim_addr]);
 471               }
 472             }
 473           }
 474         }
 475       }
 476     }
 477   }
 478
 479   // ACTIONS
 480
 481   action(a_issueGETS, "a", desc="Issue GETS") {
 482     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 483       assert(is_valid(tbe));
 484       out_msg.Address := address;
 485       out_msg.Type := CoherenceRequestType:GETS;
 486       out_msg.Requestor := machineID;
 487       out_msg.Destination.add(map_Address_to_Directory(address));
 488       out_msg.MessageSize := MessageSizeType:Request_Control;
 489       out_msg.InitialRequestTime := get_time();
 490       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
 491     }
 492   }
 493
 494   action(b_issueGETX, "b", desc="Issue GETX") {
 495     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 496       assert(is_valid(tbe));
 497       out_msg.Address := address;
 498       out_msg.Type := CoherenceRequestType:GETX;
 499       out_msg.Requestor := machineID;
 500       out_msg.Destination.add(map_Address_to_Directory(address));
 501       out_msg.MessageSize := MessageSizeType:Request_Control;
 502       out_msg.InitialRequestTime := get_time();
 503       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
 504     }
 505   }
 506
 507   action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") {
 508     peek(forwardToCache_in, RequestMsg) {
 509       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 510         assert(is_valid(cache_entry));
 511         out_msg.Address := address;
 512         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 513         out_msg.Sender := machineID;
 514         out_msg.Destination.add(in_msg.Requestor);
 515         out_msg.DataBlk := cache_entry.DataBlk;
 516         out_msg.Dirty := cache_entry.Dirty;
 517         if (in_msg.DirectedProbe) {
 518           out_msg.Acks := machineCount(MachineType:L1Cache);
 519         } else {
 520           out_msg.Acks := 2;
 521         }
 522         out_msg.SilentAcks := in_msg.SilentAcks;
 523         out_msg.MessageSize := MessageSizeType:Response_Data;
 524         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 525         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 526       }
 527     }
 528   }
 529
 530   action(d_issuePUT, "d", desc="Issue PUT") {
 531     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 532       out_msg.Address := address;
 533       out_msg.Type := CoherenceRequestType:PUT;
 534       out_msg.Requestor := machineID;
 535       out_msg.Destination.add(map_Address_to_Directory(address));
 536       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 537     }
 538   }
 539
 540   action(e_sendData, "e", desc="Send data from cache to requestor") {
 541     peek(forwardToCache_in, RequestMsg) {
 542       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 543         assert(is_valid(cache_entry));
 544         out_msg.Address := address;
 545         out_msg.Type := CoherenceResponseType:DATA;
 546         out_msg.Sender := machineID;
 547         out_msg.Destination.add(in_msg.Requestor);
 548         out_msg.DataBlk := cache_entry.DataBlk;
 549         out_msg.Dirty := cache_entry.Dirty;
 550         if (in_msg.DirectedProbe) {
 551           out_msg.Acks := machineCount(MachineType:L1Cache);
 552         } else {
 553           out_msg.Acks := 2;
 554         }
 555         out_msg.SilentAcks := in_msg.SilentAcks;
 556         out_msg.MessageSize := MessageSizeType:Response_Data;
 557         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 558         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 559       }
 560     }
 561   }
 562
 563   action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, keep a shared copy") {
 564     peek(forwardToCache_in, RequestMsg) {
 565       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 566         assert(is_valid(cache_entry));
 567         out_msg.Address := address;
 568         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 569         out_msg.Sender := machineID;
 570         out_msg.Destination.add(in_msg.Requestor);
 571         out_msg.DataBlk := cache_entry.DataBlk;
 572         out_msg.Dirty := cache_entry.Dirty;
 573         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 574         if (in_msg.DirectedProbe) {
 575           out_msg.Acks := machineCount(MachineType:L1Cache);
 576         } else {
 577           out_msg.Acks := 2;
 578         }
 579         out_msg.SilentAcks := in_msg.SilentAcks;
 580         out_msg.MessageSize := MessageSizeType:Response_Data;
 581         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 582         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 583       }
 584     }
 585   }
 586
 587   action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors") {
 588     peek(forwardToCache_in, RequestMsg) {
 589       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 590         assert(is_valid(cache_entry));
 591         out_msg.Address := address;
 592         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 593         out_msg.Sender := machineID;
 594         out_msg.Destination := in_msg.MergedRequestors;
 595         out_msg.DataBlk := cache_entry.DataBlk;
 596         out_msg.Dirty := cache_entry.Dirty;
 597         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 598         out_msg.Acks := machineCount(MachineType:L1Cache);
 599         out_msg.SilentAcks := in_msg.SilentAcks;
 600         out_msg.MessageSize := MessageSizeType:Response_Data;
 601         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 602         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 603       }
 604     }
 605   }
 606
 607   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 608     peek(forwardToCache_in, RequestMsg) {
 609       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 610         out_msg.Address := address;
 611         out_msg.Type := CoherenceResponseType:ACK;
 612         out_msg.Sender := machineID;
 613         out_msg.Destination.add(in_msg.Requestor);
 614         out_msg.Acks := 1;
 615         out_msg.SilentAcks := in_msg.SilentAcks;
 616         assert(in_msg.DirectedProbe == false);
 617         out_msg.MessageSize := MessageSizeType:Response_Control;
 618         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 619         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 620       }
 621     }
 622   }
 623
 624   action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") {
 625     peek(forwardToCache_in, RequestMsg) {
 626       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 627         out_msg.Address := address;
 628         out_msg.Type := CoherenceResponseType:ACK_SHARED;
 629         out_msg.Sender := machineID;
 630         out_msg.Destination.add(in_msg.Requestor);
 631         out_msg.Acks := 1;
 632         out_msg.SilentAcks := in_msg.SilentAcks;
 633         assert(in_msg.DirectedProbe == false);
 634         out_msg.MessageSize := MessageSizeType:Response_Control;
 635         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 636         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 637       }
 638     }
 639   }
 640
 641   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 642     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 643       out_msg.Address := address;
 644       out_msg.Type := CoherenceResponseType:UNBLOCK;
 645       out_msg.Sender := machineID;
 646       out_msg.Destination.add(map_Address_to_Directory(address));
 647       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 648     }
 649   }
 650
 651   action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") {
 652     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 653       out_msg.Address := address;
 654       out_msg.Type := CoherenceResponseType:UNBLOCKM;
 655       out_msg.Sender := machineID;
 656       out_msg.Destination.add(map_Address_to_Directory(address));
 657       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 658     }
 659   }
 660
 661   action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") {
 662     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 663       assert(is_valid(tbe));
 664       out_msg.Address := address;
 665       out_msg.Type := CoherenceResponseType:UNBLOCKS;
 666       out_msg.Sender := machineID;
 667       out_msg.CurOwner := tbe.CurOwner;
 668       out_msg.Destination.add(map_Address_to_Directory(address));
 669       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 670     }
 671   }
 672
 673   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 674     assert(is_valid(cache_entry));
 675     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 676     sequencer.readCallback(address, testAndClearLocalHit(cache_entry),
 677                            cache_entry.DataBlk);
 678   }
 679
 680   action(hx_external_load_hit, "hx", desc="load required external msgs") {
 681     assert(is_valid(cache_entry));
 682     assert(is_valid(tbe));
 683     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 684     peek(responseToCache_in, ResponseMsg) {
 685
 686       sequencer.readCallback(address,
 687                              getNondirectHitMachType(in_msg.Address, in_msg.Sender),
 688                              cache_entry.DataBlk,
 689                              tbe.InitialRequestTime,
 690                              tbe.ForwardRequestTime,
 691                              tbe.FirstResponseTime);
 692     }
 693   }
 694
 695   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 696     assert(is_valid(cache_entry));
 697     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 698     peek(mandatoryQueue_in, CacheMsg) {
 699       sequencer.writeCallback(address, testAndClearLocalHit(cache_entry),
 700                               cache_entry.DataBlk);
 701
 702       cache_entry.Dirty := true;
 703       if (in_msg.Type == CacheRequestType:ATOMIC) {
 704         cache_entry.AtomicAccessed := true;
 705       }
 706     }
 707   }
 708
 709   action(sx_external_store_hit, "sx", desc="store required external msgs.") {
 710     assert(is_valid(cache_entry));
 711     assert(is_valid(tbe));
 712     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 713     peek(responseToCache_in, ResponseMsg) {
 714
 715       sequencer.writeCallback(address,
 716                               getNondirectHitMachType(address, in_msg.Sender),
 717                               cache_entry.DataBlk,
 718                               tbe.InitialRequestTime,
 719                               tbe.ForwardRequestTime,
 720                               tbe.FirstResponseTime);
 721     }
 722     cache_entry.Dirty := true;
 723   }
 724
 725   action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
 726     assert(is_valid(cache_entry));
 727     assert(is_valid(tbe));
 728     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 729
 730     sequencer.writeCallback(address,
 731                             getNondirectHitMachType(address, tbe.LastResponder),
 732                             cache_entry.DataBlk,
 733                             tbe.InitialRequestTime,
 734                             tbe.ForwardRequestTime,
 735                             tbe.FirstResponseTime);
 736
 737     cache_entry.Dirty := true;
 738   }
 739
 740   action(i_allocateTBE, "i", desc="Allocate TBE") {
 741     check_allocate(TBEs);
 742     assert(is_valid(cache_entry));
 743     TBEs.allocate(address);
 744     set_tbe(TBEs[address]);
 745     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
 746     tbe.Dirty := cache_entry.Dirty;
 747     tbe.Sharers := false;
 748   }
 749
 750   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 751     triggerQueue_in.dequeue();
 752   }
 753
 754   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 755     mandatoryQueue_in.dequeue();
 756   }
 757
 758   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 759     forwardToCache_in.dequeue();
 760   }
 761
 762   action(hp_copyFromTBEToL2, "li", desc="Copy data from TBE to L2 cache entry.") {
 763     assert(is_valid(cache_entry));
 764     assert(is_valid(tbe));
 765     cache_entry.Dirty   := tbe.Dirty;
 766     cache_entry.DataBlk := tbe.DataBlk;
 767   }
 768
 769   action(nb_copyFromTBEToL1, "fu", desc="Copy data from TBE to L1 cache entry.") {
 770     assert(is_valid(cache_entry));
 771     assert(is_valid(tbe));
 772     cache_entry.Dirty   := tbe.Dirty;
 773     cache_entry.DataBlk := tbe.DataBlk;
 774     cache_entry.FromL2 := true;
 775   }
 776
 777   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 778     peek(responseToCache_in, ResponseMsg) {
 779       assert(in_msg.Acks > 0);
 780       assert(is_valid(tbe));
 781       DPRINTF(RubySlicc, "Sender = %s\n", in_msg.Sender);
 782       DPRINTF(RubySlicc, "SilentAcks = %d\n", in_msg.SilentAcks);
 783       if (tbe.AppliedSilentAcks == false) {
 784         tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.SilentAcks;
 785         tbe.AppliedSilentAcks := true;
 786       }
 787       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 788       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 789       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 790       APPEND_TRANSITION_COMMENT(tbe.NumPendingMsgs);
 791       APPEND_TRANSITION_COMMENT(in_msg.Sender);
 792       tbe.LastResponder := in_msg.Sender;
 793       if (tbe.InitialRequestTime != zero_time() && in_msg.InitialRequestTime != zero_time()) {
 794         assert(tbe.InitialRequestTime == in_msg.InitialRequestTime);
 795       }
 796       if (in_msg.InitialRequestTime != zero_time()) {
 797         tbe.InitialRequestTime := in_msg.InitialRequestTime;
 798       }
 799       if (tbe.ForwardRequestTime != zero_time() && in_msg.ForwardRequestTime != zero_time()) {
 800         assert(tbe.ForwardRequestTime == in_msg.ForwardRequestTime);
 801       }
 802       if (in_msg.ForwardRequestTime != zero_time()) {
 803         tbe.ForwardRequestTime := in_msg.ForwardRequestTime;
 804       }
 805       if (tbe.FirstResponseTime == zero_time()) {
 806         tbe.FirstResponseTime := get_time();
 807       }
 808     }
 809   }
 810   action(uo_updateCurrentOwner, "uo", desc="When moving SS state, update current owner.") {
 811     peek(responseToCache_in, ResponseMsg) {
 812       assert(is_valid(tbe));
 813       tbe.CurOwner := in_msg.Sender;
 814     }
 815   }
 816
 817   action(n_popResponseQueue, "n", desc="Pop response queue") {
 818     responseToCache_in.dequeue();
 819   }
 820
 821   action(ll_L2toL1Transfer, "ll", desc="") {
 822     enqueue(triggerQueue_out, TriggerMsg, latency=l2_cache_hit_latency) {
 823       out_msg.Address := address;
 824       out_msg.Type := TriggerType:L2_to_L1;
 825     }
 826   }
 827
 828   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 829     assert(is_valid(tbe));
 830     if (tbe.NumPendingMsgs == 0) {
 831       enqueue(triggerQueue_out, TriggerMsg) {
 832         out_msg.Address := address;
 833         if (tbe.Sharers) {
 834           out_msg.Type := TriggerType:ALL_ACKS;
 835         } else {
 836           out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
 837         }
 838       }
 839     }
 840   }
 841
 842   action(p_decrementNumberOfMessagesByOne, "p", desc="Decrement the number of messages for which we're waiting by one") {
 843     assert(is_valid(tbe));
 844     tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
 845   }
 846
 847   action(pp_incrementNumberOfMessagesByOne, "\p", desc="Increment the number of messages for which we're waiting by one") {
 848     assert(is_valid(tbe));
 849     tbe.NumPendingMsgs := tbe.NumPendingMsgs + 1;
 850   }
 851
 852   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 853     peek(forwardToCache_in, RequestMsg) {
 854         assert(in_msg.Requestor != machineID);
 855       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 856         assert(is_valid(tbe));
 857         out_msg.Address := address;
 858         out_msg.Type := CoherenceResponseType:DATA;
 859         out_msg.Sender := machineID;
 860         out_msg.Destination.add(in_msg.Requestor);
 861         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 862         out_msg.DataBlk := tbe.DataBlk;
 863         out_msg.Dirty := tbe.Dirty;
 864         if (in_msg.DirectedProbe) {
 865           out_msg.Acks := machineCount(MachineType:L1Cache);
 866         } else {
 867           out_msg.Acks := 2;
 868         }
 869         out_msg.SilentAcks := in_msg.SilentAcks;
 870         out_msg.MessageSize := MessageSizeType:Response_Data;
 871         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 872         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 873       }
 874     }
 875   }
 876
 877   action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, multiple sharers") {
 878     peek(forwardToCache_in, RequestMsg) {
 879       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 880         assert(is_valid(tbe));
 881         out_msg.Address := address;
 882         out_msg.Type := CoherenceResponseType:DATA;
 883         out_msg.Sender := machineID;
 884         out_msg.Destination := in_msg.MergedRequestors;
 885         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 886         out_msg.DataBlk := tbe.DataBlk;
 887         out_msg.Dirty := tbe.Dirty;
 888         out_msg.Acks := machineCount(MachineType:L1Cache);
 889         out_msg.SilentAcks := in_msg.SilentAcks;
 890         out_msg.MessageSize := MessageSizeType:Response_Data;
 891         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 892         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 893       }
 894     }
 895   }
 896
 897   action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
 898     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 899       assert(is_valid(tbe));
 900       out_msg.Address := address;
 901       out_msg.Sender := machineID;
 902       out_msg.Destination.add(map_Address_to_Directory(address));
 903       out_msg.Dirty := tbe.Dirty;
 904       if (tbe.Dirty) {
 905         out_msg.Type := CoherenceResponseType:WB_DIRTY;
 906         out_msg.DataBlk := tbe.DataBlk;
 907         out_msg.MessageSize := MessageSizeType:Writeback_Data;
 908       } else {
 909         out_msg.Type := CoherenceResponseType:WB_CLEAN;
 910         // NOTE: in a real system this would not send data.  We send
 911         // data here only so we can check it at the memory
 912         out_msg.DataBlk := tbe.DataBlk;
 913         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 914       }
 915     }
 916   }
 917
 918   action(r_setSharerBit, "r", desc="We saw other sharers") {
 919     assert(is_valid(tbe));
 920     tbe.Sharers := true;
 921   }
 922
 923   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 924     TBEs.deallocate(address);
 925     unset_tbe();
 926   }
 927
 928   action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") {
 929     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 930       assert(is_valid(tbe));
 931       out_msg.Address := address;
 932       out_msg.Sender := machineID;
 933       out_msg.Destination.add(map_Address_to_Directory(address));
 934       out_msg.DataBlk := tbe.DataBlk;
 935       out_msg.Dirty := tbe.Dirty;
 936       if (tbe.Dirty) {
 937         out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_DIRTY;
 938         out_msg.DataBlk := tbe.DataBlk;
 939         out_msg.MessageSize := MessageSizeType:Writeback_Data;
 940       } else {
 941         out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_CLEAN;
 942         // NOTE: in a real system this would not send data.  We send
 943         // data here only so we can check it at the memory
 944         out_msg.DataBlk := tbe.DataBlk;
 945         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 946       }
 947     }
 948   }
 949
 950   action(u_writeDataToCache, "u", desc="Write data to cache") {
 951     peek(responseToCache_in, ResponseMsg) {
 952       assert(is_valid(cache_entry));
 953       cache_entry.DataBlk := in_msg.DataBlk;
 954       cache_entry.Dirty := in_msg.Dirty;
 955     }
 956   }
 957
 958   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
 959     peek(responseToCache_in, ResponseMsg) {
 960       assert(is_valid(cache_entry));
 961       DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
 962               cache_entry.DataBlk, in_msg.DataBlk);
 963       assert(cache_entry.DataBlk == in_msg.DataBlk);
 964       cache_entry.DataBlk := in_msg.DataBlk;
 965       cache_entry.Dirty := in_msg.Dirty || cache_entry.Dirty;
 966     }
 967   }
 968
 969   action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 970     if (L1DcacheMemory.isTagPresent(address)) {
 971       L1DcacheMemory.deallocate(address);
 972     } else {
 973       L1IcacheMemory.deallocate(address);
 974     }
 975     unset_cache_entry();
 976   }
 977
 978   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
 979     if (is_invalid(cache_entry)) {
 980       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
 981     }
 982   }
 983
 984   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
 985     if (is_invalid(cache_entry)) {
 986       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
 987     }
 988   }
 989
 990   action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
 991     set_cache_entry(L2cacheMemory.allocate(address, new Entry));
 992   }
 993
 994   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 995     L2cacheMemory.deallocate(address);
 996     unset_cache_entry();
 997   }
 998
 999   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1000     peek(mandatoryQueue_in, CacheMsg) {
1001       if (L1IcacheMemory.isTagPresent(address)) {
1002         L1IcacheMemory.profileMiss(in_msg);
1003       } else if (L1DcacheMemory.isTagPresent(address)) {
1004         L1DcacheMemory.profileMiss(in_msg);
1005       }
1006       if (L2cacheMemory.isTagPresent(address) == false) {
1007         L2cacheMemory.profileMiss(in_msg);
1008       }
1009     }
1010   }
1011
1012   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1013     stall_and_wait(mandatoryQueue_in, address);
1014   }
1015
1016   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1017     wakeUpBuffers(address);
1018   }
1019
1020   action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1021     wakeUpAllBuffers();
1022   }
1023
1024   //*****************************************************
1025   // TRANSITIONS
1026   //*****************************************************
1027
1028   // Transitions for Load/Store/L2_Replacement from transient states
1029   transition({IM, SM, ISM, OM, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) {
1030     zz_stallAndWaitMandatoryQueue;
1031   }
1032
1033   transition({M_W, MM_W}, {L2_Replacement}) {
1034     zz_stallAndWaitMandatoryQueue;
1035   }
1036
1037   transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT}, {Load, Ifetch}) {
1038     zz_stallAndWaitMandatoryQueue;
1039   }
1040
1041   transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT}, L1_to_L2) {
1042     zz_stallAndWaitMandatoryQueue;
1043   }
1044
1045   transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
1046     // stall
1047   }
1048
1049   // Transitions moving data between the L1 and L2 caches
1050   transition({I, S, O, M, MM}, L1_to_L2) {
1051     i_allocateTBE;
1052     gg_deallocateL1CacheBlock;
1053     vv_allocateL2CacheBlock;
1054     hp_copyFromTBEToL2;
1055     s_deallocateTBE;
1056     ka_wakeUpAllDependents;
1057   }
1058
1059   transition(I, Trigger_L2_to_L1D, IT) {
1060     i_allocateTBE;
1061     rr_deallocateL2CacheBlock;
1062     ii_allocateL1DCacheBlock;
1063     nb_copyFromTBEToL1; // Not really needed for state I
1064     s_deallocateTBE;
1065     uu_profileMiss;
1066     zz_stallAndWaitMandatoryQueue;
1067     ll_L2toL1Transfer;
1068   }
1069
1070   transition(S, Trigger_L2_to_L1D, ST) {
1071     i_allocateTBE;
1072     rr_deallocateL2CacheBlock;
1073     ii_allocateL1DCacheBlock;
1074     nb_copyFromTBEToL1;
1075     s_deallocateTBE;
1076     uu_profileMiss;
1077     zz_stallAndWaitMandatoryQueue;
1078     ll_L2toL1Transfer;
1079   }
1080
1081   transition(O, Trigger_L2_to_L1D, OT) {
1082     i_allocateTBE;
1083     rr_deallocateL2CacheBlock;
1084     ii_allocateL1DCacheBlock;
1085     nb_copyFromTBEToL1;
1086     s_deallocateTBE;
1087     uu_profileMiss;
1088     zz_stallAndWaitMandatoryQueue;
1089     ll_L2toL1Transfer;
1090   }
1091
1092   transition(M, Trigger_L2_to_L1D, MT) {
1093     i_allocateTBE;
1094     rr_deallocateL2CacheBlock;
1095     ii_allocateL1DCacheBlock;
1096     nb_copyFromTBEToL1;
1097     s_deallocateTBE;
1098     uu_profileMiss;
1099     zz_stallAndWaitMandatoryQueue;
1100     ll_L2toL1Transfer;
1101   }
1102
1103   transition(MM, Trigger_L2_to_L1D, MMT) {
1104     i_allocateTBE;
1105     rr_deallocateL2CacheBlock;
1106     ii_allocateL1DCacheBlock;
1107     nb_copyFromTBEToL1;
1108     s_deallocateTBE;
1109     uu_profileMiss;
1110     zz_stallAndWaitMandatoryQueue;
1111     ll_L2toL1Transfer;
1112   }
1113
1114   transition(I, Trigger_L2_to_L1I, IT) {
1115     i_allocateTBE;
1116     rr_deallocateL2CacheBlock;
1117     jj_allocateL1ICacheBlock;
1118     nb_copyFromTBEToL1;
1119     s_deallocateTBE;
1120     uu_profileMiss;
1121     zz_stallAndWaitMandatoryQueue;
1122     ll_L2toL1Transfer;
1123   }
1124
1125   transition(S, Trigger_L2_to_L1I, ST) {
1126     i_allocateTBE;
1127     rr_deallocateL2CacheBlock;
1128     jj_allocateL1ICacheBlock;
1129     nb_copyFromTBEToL1;
1130     s_deallocateTBE;
1131     uu_profileMiss;
1132     zz_stallAndWaitMandatoryQueue;
1133     ll_L2toL1Transfer;
1134   }
1135
1136   transition(O, Trigger_L2_to_L1I, OT) {
1137     i_allocateTBE;
1138     rr_deallocateL2CacheBlock;
1139     jj_allocateL1ICacheBlock;
1140     nb_copyFromTBEToL1;
1141     s_deallocateTBE;
1142     uu_profileMiss;
1143     zz_stallAndWaitMandatoryQueue;
1144     ll_L2toL1Transfer;
1145   }
1146
1147   transition(M, Trigger_L2_to_L1I, MT) {
1148     i_allocateTBE;
1149     rr_deallocateL2CacheBlock;
1150     jj_allocateL1ICacheBlock;
1151     nb_copyFromTBEToL1;
1152     s_deallocateTBE;
1153     uu_profileMiss;
1154     zz_stallAndWaitMandatoryQueue;
1155     ll_L2toL1Transfer;
1156   }
1157
1158   transition(MM, Trigger_L2_to_L1I, MMT) {
1159     i_allocateTBE;
1160     rr_deallocateL2CacheBlock;
1161     jj_allocateL1ICacheBlock;
1162     nb_copyFromTBEToL1;
1163     s_deallocateTBE;
1164     uu_profileMiss;
1165     zz_stallAndWaitMandatoryQueue;
1166     ll_L2toL1Transfer;
1167   }
1168
1169   transition(IT, Complete_L2_to_L1, I) {
1170     j_popTriggerQueue;
1171     kd_wakeUpDependents;
1172   }
1173
1174   transition(ST, Complete_L2_to_L1, S) {
1175     j_popTriggerQueue;
1176     kd_wakeUpDependents;
1177   }
1178
1179   transition(OT, Complete_L2_to_L1, O) {
1180     j_popTriggerQueue;
1181     kd_wakeUpDependents;
1182   }
1183
1184   transition(MT, Complete_L2_to_L1, M) {
1185     j_popTriggerQueue;
1186     kd_wakeUpDependents;
1187   }
1188
1189   transition(MMT, Complete_L2_to_L1, MM) {
1190     j_popTriggerQueue;
1191     kd_wakeUpDependents;
1192   }
1193
1194   // Transitions from Idle
1195   transition(I, Load, IS) {
1196     ii_allocateL1DCacheBlock;
1197     i_allocateTBE;
1198     a_issueGETS;
1199     uu_profileMiss;
1200     k_popMandatoryQueue;
1201   }
1202
1203   transition(I, Ifetch, IS) {
1204     jj_allocateL1ICacheBlock;
1205     i_allocateTBE;
1206     a_issueGETS;
1207     uu_profileMiss;
1208     k_popMandatoryQueue;
1209   }
1210
1211   transition(I, Store, IM) {
1212     ii_allocateL1DCacheBlock;
1213     i_allocateTBE;
1214     b_issueGETX;
1215     uu_profileMiss;
1216     k_popMandatoryQueue;
1217   }
1218
1219   transition(I, L2_Replacement) {
1220     rr_deallocateL2CacheBlock;
1221     ka_wakeUpAllDependents;
1222   }
1223
1224   transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1225     f_sendAck;
1226     l_popForwardQueue;
1227   }
1228
1229   // Transitions from Shared
1230   transition({S, SM, ISM}, {Load, Ifetch}) {
1231     h_load_hit;
1232     k_popMandatoryQueue;
1233   }
1234
1235   transition(S, Store, SM) {
1236     i_allocateTBE;
1237     b_issueGETX;
1238     uu_profileMiss;
1239     k_popMandatoryQueue;
1240   }
1241
1242   transition(S, L2_Replacement, I) {
1243     rr_deallocateL2CacheBlock;
1244     ka_wakeUpAllDependents;
1245   }
1246
1247   transition(S, {Other_GETX, Invalidate}, I) {
1248     f_sendAck;
1249     l_popForwardQueue;
1250   }
1251
1252   transition(S, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1253     ff_sendAckShared;
1254     l_popForwardQueue;
1255   }
1256
1257   // Transitions from Owned
1258   transition({O, OM, SS, MM_W, M_W}, {Load, Ifetch}) {
1259     h_load_hit;
1260     k_popMandatoryQueue;
1261   }
1262
1263   transition(O, Store, OM) {
1264     i_allocateTBE;
1265     b_issueGETX;
1266     p_decrementNumberOfMessagesByOne;
1267     uu_profileMiss;
1268     k_popMandatoryQueue;
1269   }
1270
1271   transition(O, L2_Replacement, OI) {
1272     i_allocateTBE;
1273     d_issuePUT;
1274     rr_deallocateL2CacheBlock;
1275     ka_wakeUpAllDependents;
1276   }
1277
1278   transition(O, {Other_GETX, Invalidate}, I) {
1279     e_sendData;
1280     l_popForwardQueue;
1281   }
1282
1283   transition(O, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1284     ee_sendDataShared;
1285     l_popForwardQueue;
1286   }
1287
1288   transition(O, Merged_GETS) {
1289     em_sendDataSharedMultiple;
1290     l_popForwardQueue;
1291   }
1292
1293   // Transitions from Modified
1294   transition(MM, {Load, Ifetch}) {
1295     h_load_hit;
1296     k_popMandatoryQueue;
1297   }
1298
1299   transition(MM, Store) {
1300     hh_store_hit;
1301     k_popMandatoryQueue;
1302   }
1303
1304   transition(MM, L2_Replacement, MI) {
1305     i_allocateTBE;
1306     d_issuePUT;
1307     rr_deallocateL2CacheBlock;
1308     ka_wakeUpAllDependents;
1309   }
1310
1311   transition(MM, {Other_GETX, Invalidate}, I) {
1312     c_sendExclusiveData;
1313     l_popForwardQueue;
1314   }
1315
1316   transition(MM, Other_GETS, I) {
1317     c_sendExclusiveData;
1318     l_popForwardQueue;
1319   }
1320
1321   transition(MM, NC_DMA_GETS) {
1322     c_sendExclusiveData;
1323     l_popForwardQueue;
1324   }
1325
1326   transition(MM, Other_GETS_No_Mig, O) {
1327     ee_sendDataShared;
1328     l_popForwardQueue;
1329   }
1330
1331   transition(MM, Merged_GETS, O) {
1332     em_sendDataSharedMultiple;
1333     l_popForwardQueue;
1334   }
1335
1336   // Transitions from Dirty Exclusive
1337   transition(M, {Load, Ifetch}) {
1338     h_load_hit;
1339     k_popMandatoryQueue;
1340   }
1341
1342   transition(M, Store, MM) {
1343     hh_store_hit;
1344     k_popMandatoryQueue;
1345   }
1346
1347   transition(M, L2_Replacement, MI) {
1348     i_allocateTBE;
1349     d_issuePUT;
1350     rr_deallocateL2CacheBlock;
1351     ka_wakeUpAllDependents;
1352   }
1353
1354   transition(M, {Other_GETX, Invalidate}, I) {
1355     c_sendExclusiveData;
1356     l_popForwardQueue;
1357   }
1358
1359   transition(M, {Other_GETS, Other_GETS_No_Mig}, O) {
1360     ee_sendDataShared;
1361     l_popForwardQueue;
1362   }
1363
1364   transition(M, NC_DMA_GETS) {
1365     ee_sendDataShared;
1366     l_popForwardQueue;
1367   }
1368
1369   transition(M, Merged_GETS, O) {
1370     em_sendDataSharedMultiple;
1371     l_popForwardQueue;
1372   }
1373
1374   // Transitions from IM
1375
1376   transition(IM, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1377     f_sendAck;
1378     l_popForwardQueue;
1379   }
1380
1381   transition(IM, Ack) {
1382     m_decrementNumberOfMessages;
1383     o_checkForCompletion;
1384     n_popResponseQueue;
1385   }
1386
1387   transition(IM, Data, ISM) {
1388     u_writeDataToCache;
1389     m_decrementNumberOfMessages;
1390     o_checkForCompletion;
1391     n_popResponseQueue;
1392   }
1393
1394   transition(IM, Exclusive_Data, MM_W) {
1395     u_writeDataToCache;
1396     m_decrementNumberOfMessages;
1397     o_checkForCompletion;
1398     sx_external_store_hit;
1399     n_popResponseQueue;
1400     kd_wakeUpDependents;
1401   }
1402
1403   // Transitions from SM
1404   transition(SM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1405     ff_sendAckShared;
1406     l_popForwardQueue;
1407   }
1408
1409   transition(SM, {Other_GETX, Invalidate}, IM) {
1410     f_sendAck;
1411     l_popForwardQueue;
1412   }
1413
1414   transition(SM, Ack) {
1415     m_decrementNumberOfMessages;
1416     o_checkForCompletion;
1417     n_popResponseQueue;
1418   }
1419
1420   transition(SM, {Data, Exclusive_Data}, ISM) {
1421     v_writeDataToCacheVerify;
1422     m_decrementNumberOfMessages;
1423     o_checkForCompletion;
1424     n_popResponseQueue;
1425   }
1426
1427   // Transitions from ISM
1428   transition(ISM, Ack) {
1429     m_decrementNumberOfMessages;
1430     o_checkForCompletion;
1431     n_popResponseQueue;
1432   }
1433
1434   transition(ISM, All_acks_no_sharers, MM) {
1435     sxt_trig_ext_store_hit;
1436     gm_sendUnblockM;
1437     s_deallocateTBE;
1438     j_popTriggerQueue;
1439     kd_wakeUpDependents;
1440   }
1441
1442   // Transitions from OM
1443
1444   transition(OM, {Other_GETX, Invalidate}, IM) {
1445     e_sendData;
1446     pp_incrementNumberOfMessagesByOne;
1447     l_popForwardQueue;
1448   }
1449
1450   transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1451     ee_sendDataShared;
1452     l_popForwardQueue;
1453   }
1454
1455   transition(OM, Merged_GETS) {
1456     em_sendDataSharedMultiple;
1457     l_popForwardQueue;
1458   }
1459
1460   transition(OM, Ack) {
1461     m_decrementNumberOfMessages;
1462     o_checkForCompletion;
1463     n_popResponseQueue;
1464   }
1465
1466   transition(OM, {All_acks, All_acks_no_sharers}, MM) {
1467     sxt_trig_ext_store_hit;
1468     gm_sendUnblockM;
1469     s_deallocateTBE;
1470     j_popTriggerQueue;
1471     kd_wakeUpDependents;
1472   }
1473
1474   // Transitions from IS
1475
1476   transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1477     f_sendAck;
1478     l_popForwardQueue;
1479   }
1480
1481   transition(IS, Ack) {
1482     m_decrementNumberOfMessages;
1483     o_checkForCompletion;
1484     n_popResponseQueue;
1485   }
1486
1487   transition(IS, Shared_Ack) {
1488     m_decrementNumberOfMessages;
1489     r_setSharerBit;
1490     o_checkForCompletion;
1491     n_popResponseQueue;
1492   }
1493
1494   transition(IS, Data, SS) {
1495     u_writeDataToCache;
1496     m_decrementNumberOfMessages;
1497     o_checkForCompletion;
1498     hx_external_load_hit;
1499     uo_updateCurrentOwner;
1500     n_popResponseQueue;
1501     kd_wakeUpDependents;
1502   }
1503
1504   transition(IS, Exclusive_Data, M_W) {
1505     u_writeDataToCache;
1506     m_decrementNumberOfMessages;
1507     o_checkForCompletion;
1508     hx_external_load_hit;
1509     n_popResponseQueue;
1510     kd_wakeUpDependents;
1511   }
1512
1513   transition(IS, Shared_Data, SS) {
1514     u_writeDataToCache;
1515     r_setSharerBit;
1516     m_decrementNumberOfMessages;
1517     o_checkForCompletion;
1518     hx_external_load_hit;
1519     uo_updateCurrentOwner;
1520     n_popResponseQueue;
1521     kd_wakeUpDependents;
1522   }
1523
1524   // Transitions from SS
1525
1526   transition(SS, Ack) {
1527     m_decrementNumberOfMessages;
1528     o_checkForCompletion;
1529     n_popResponseQueue;
1530   }
1531
1532   transition(SS, Shared_Ack) {
1533     m_decrementNumberOfMessages;
1534     r_setSharerBit;
1535     o_checkForCompletion;
1536     n_popResponseQueue;
1537   }
1538
1539   transition(SS, All_acks, S) {
1540     gs_sendUnblockS;
1541     s_deallocateTBE;
1542     j_popTriggerQueue;
1543     kd_wakeUpDependents;
1544   }
1545
1546   transition(SS, All_acks_no_sharers, S) {
1547     // Note: The directory might still be the owner, so that is why we go to S
1548     gs_sendUnblockS;
1549     s_deallocateTBE;
1550     j_popTriggerQueue;
1551     kd_wakeUpDependents;
1552   }
1553
1554   // Transitions from MM_W
1555
1556   transition(MM_W, Store) {
1557     hh_store_hit;
1558     k_popMandatoryQueue;
1559   }
1560
1561   transition(MM_W, Ack) {
1562     m_decrementNumberOfMessages;
1563     o_checkForCompletion;
1564     n_popResponseQueue;
1565   }
1566
1567   transition(MM_W, All_acks_no_sharers, MM) {
1568     gm_sendUnblockM;
1569     s_deallocateTBE;
1570     j_popTriggerQueue;
1571     kd_wakeUpDependents;
1572   }
1573
1574   // Transitions from M_W
1575
1576   transition(M_W, Store, MM_W) {
1577     hh_store_hit;
1578     k_popMandatoryQueue;
1579   }
1580
1581   transition(M_W, Ack) {
1582     m_decrementNumberOfMessages;
1583     o_checkForCompletion;
1584     n_popResponseQueue;
1585   }
1586
1587   transition(M_W, All_acks_no_sharers, M) {
1588     gm_sendUnblockM;
1589     s_deallocateTBE;
1590     j_popTriggerQueue;
1591     kd_wakeUpDependents;
1592   }
1593
1594   // Transitions from OI/MI
1595
1596   transition({OI, MI}, {Other_GETX, Invalidate}, II) {
1597     q_sendDataFromTBEToCache;
1598     l_popForwardQueue;
1599   }
1600
1601   transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
1602     q_sendDataFromTBEToCache;
1603     l_popForwardQueue;
1604   }
1605
1606   transition({OI, MI}, Merged_GETS, OI) {
1607     qm_sendDataFromTBEToCache;
1608     l_popForwardQueue;
1609   }
1610
1611   transition(MI, Writeback_Ack, I) {
1612     t_sendExclusiveDataFromTBEToMemory;
1613     s_deallocateTBE;
1614     l_popForwardQueue;
1615     kd_wakeUpDependents;
1616   }
1617
1618   transition(OI, Writeback_Ack, I) {
1619     qq_sendDataFromTBEToMemory;
1620     s_deallocateTBE;
1621     l_popForwardQueue;
1622     kd_wakeUpDependents;
1623   }
1624
1625   // Transitions from II
1626   transition(II, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
1627     f_sendAck;
1628     l_popForwardQueue;
1629   }
1630
1631   transition(II, Writeback_Ack, I) {
1632     g_sendUnblock;
1633     s_deallocateTBE;
1634     l_popForwardQueue;
1635     kd_wakeUpDependents;
1636   }
1637
1638   transition(II, Writeback_Nack, I) {
1639     s_deallocateTBE;
1640     l_popForwardQueue;
1641     kd_wakeUpDependents;
1642   }
1643 }