src/mem/protocol/MOESI_hammer-cache.sm

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * AMD's contributions to the MOESI hammer protocol do not constitute an
  30  * endorsement of its similarity to any AMD products.
  31  *
  32  * Authors: Milo Martin
  33  *          Brad Beckmann
  34  */
  35
  36 machine(L1Cache, "AMD Hammer-like protocol")
  37 : Sequencer * sequencer,
  38   CacheMemory * L1IcacheMemory,
  39   CacheMemory * L1DcacheMemory,
  40   CacheMemory * L2cacheMemory,
  41   int cache_response_latency = 10,
  42   int issue_latency = 2,
  43   int l2_cache_hit_latency = 10,
  44   bool no_mig_atomic = true
  45 {
  46
  47   // NETWORK BUFFERS
  48   MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="false";
  49   MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="false";
  50   MessageBuffer unblockFromCache, network="To", virtual_network="5", ordered="false";
  51
  52   MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="false";
  53   MessageBuffer responseToCache, network="From", virtual_network="4", ordered="false";
  54
  55
  56   // STATES
  57   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  58     // Base states
  59     I, desc="Idle";
  60     S, desc="Shared";
  61     O, desc="Owned";
  62     M, desc="Modified (dirty)";
  63     MM, desc="Modified (dirty and locally modified)";
  64
  65     // Transient States
  66     IM, "IM", desc="Issued GetX";
  67     SM, "SM", desc="Issued GetX, we still have an old copy of the line";
  68     OM, "OM", desc="Issued GetX, received data";
  69     ISM, "ISM", desc="Issued GetX, received data, waiting for all acks";
  70     M_W, "M^W", desc="Issued GetS, received exclusive data";
  71     MM_W, "MM^W", desc="Issued GetX, received exclusive data";
  72     IS, "IS", desc="Issued GetS";
  73     SS, "SS", desc="Issued GetS, received data, waiting for all acks";
  74     OI, "OI", desc="Issued PutO, waiting for ack";
  75     MI, "MI", desc="Issued PutX, waiting for ack";
  76     II, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack";
  77     IT, "IT", desc="Invalid block transferring to L1";
  78     ST, "ST", desc="S block transferring to L1";
  79     OT, "OT", desc="O block transferring to L1";
  80     MT, "MT", desc="M block transferring to L1";
  81     MMT, "MMT", desc="MM block transferring to L1";
  82   }
  83
  84   // EVENTS
  85   enumeration(Event, desc="Cache events") {
  86     Load,            desc="Load request from the processor";
  87     Ifetch,          desc="I-fetch request from the processor";
  88     Store,           desc="Store request from the processor";
  89     L2_Replacement,  desc="L2 Replacement";
  90     L1_to_L2,        desc="L1 to L2 transfer";
  91     Trigger_L2_to_L1D,  desc="Trigger L2 to L1-Data transfer";
  92     Trigger_L2_to_L1I,  desc="Trigger L2 to L1-Instruction transfer";
  93     Complete_L2_to_L1, desc="L2 to L1 transfer completed";
  94
  95     // Requests
  96     Other_GETX,      desc="A GetX from another processor";
  97     Other_GETS,      desc="A GetS from another processor";
  98     Merged_GETS,     desc="A Merged GetS from another processor";
  99     Other_GETS_No_Mig, desc="A GetS from another processor";
 100     NC_DMA_GETS,     desc="special GetS when only DMA exists";
 101     Invalidate,      desc="Invalidate block";
 102
 103     // Responses
 104     Ack,             desc="Received an ack message";
 105     Shared_Ack,      desc="Received an ack message, responder has a shared copy";
 106     Data,            desc="Received a data message";
 107     Shared_Data,     desc="Received a data message, responder has a shared copy";
 108     Exclusive_Data,  desc="Received a data message, responder had an exclusive copy, they gave it to us";
 109
 110     Writeback_Ack,   desc="Writeback O.K. from directory";
 111     Writeback_Nack,  desc="Writeback not O.K. from directory";
 112
 113     // Triggers
 114     All_acks,                  desc="Received all required data and message acks";
 115     All_acks_no_sharers,        desc="Received all acks and no other processor has a shared copy";
 116   }
 117
 118   // TYPES
 119
 120   // STRUCTURE DEFINITIONS
 121
 122   MessageBuffer mandatoryQueue, ordered="false";
 123
 124   // CacheEntry
 125   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 126     State CacheState,        desc="cache state";
 127     bool Dirty,              desc="Is the data dirty (different than memory)?";
 128     DataBlock DataBlk,       desc="data for the block";
 129     bool FromL2, default="false", desc="block just moved from L2";
 130     bool AtomicAccessed, default="false", desc="block just moved from L2";
 131   }
 132
 133   // TBE fields
 134   structure(TBE, desc="...") {
 135     State TBEState,          desc="Transient state";
 136     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 137     bool Dirty,              desc="Is the data dirty (different than memory)?";
 138     int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
 139     bool Sharers,            desc="On a GetS, did we find any other sharers in the system";
 140     bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks";
 141     MachineID LastResponder, desc="last machine to send a response for this request";
 142     MachineID CurOwner,      desc="current owner of the block, used for UnblockS responses";
 143     Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
 144     Time ForwardRequestTime, default="0", desc="time the dir forwarded the request";
 145     Time FirstResponseTime, default="0", desc="the time the first response was received";
 146   }
 147
 148   external_type(TBETable) {
 149     TBE lookup(Address);
 150     void allocate(Address);
 151     void deallocate(Address);
 152     bool isPresent(Address);
 153   }
 154
 155   TBETable TBEs, template_hack="<L1Cache_TBE>";
 156
 157   void set_cache_entry(AbstractCacheEntry b);
 158   void unset_cache_entry();
 159   void set_tbe(TBE b);
 160   void unset_tbe();
 161
 162   Entry getCacheEntry(Address address), return_by_pointer="yes" {
 163     Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
 164     if(is_valid(L2cache_entry)) {
 165       return L2cache_entry;
 166     }
 167
 168     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(address));
 169     if(is_valid(L1Dcache_entry)) {
 170       return L1Dcache_entry;
 171     }
 172
 173     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(address));
 174     return L1Icache_entry;
 175   }
 176
 177   Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
 178     Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
 179     return L2cache_entry;
 180   }
 181
 182   Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
 183     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(address));
 184     return L1Dcache_entry;
 185   }
 186
 187   Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
 188     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(address));
 189     return L1Icache_entry;
 190   }
 191
 192   State getState(TBE tbe, Entry cache_entry, Address addr) {
 193     if(is_valid(tbe)) {
 194       return tbe.TBEState;
 195     } else if (is_valid(cache_entry)) {
 196       return cache_entry.CacheState;
 197     }
 198     return State:I;
 199   }
 200
 201   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 202     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 203     assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 204     assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 205
 206     if (is_valid(tbe)) {
 207       tbe.TBEState := state;
 208     }
 209
 210     if (is_valid(cache_entry)) {
 211       cache_entry.CacheState := state;
 212
 213       // Set permission
 214       if ((state == State:MM) ||
 215           (state == State:MM_W)) {
 216         cache_entry.changePermission(AccessPermission:Read_Write);
 217       } else if (state == State:S ||
 218                  state == State:O ||
 219                  state == State:M ||
 220                  state == State:M_W ||
 221                  state == State:SM ||
 222                  state == State:ISM ||
 223                  state == State:OM ||
 224                  state == State:SS) {
 225         cache_entry.changePermission(AccessPermission:Read_Only);
 226       } else {
 227         cache_entry.changePermission(AccessPermission:Invalid);
 228       }
 229     }
 230   }
 231
 232   Event mandatory_request_type_to_event(CacheRequestType type) {
 233     if (type == CacheRequestType:LD) {
 234       return Event:Load;
 235     } else if (type == CacheRequestType:IFETCH) {
 236       return Event:Ifetch;
 237     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 238       return Event:Store;
 239     } else {
 240       error("Invalid CacheRequestType");
 241     }
 242   }
 243
 244   GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
 245     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
 246       //
 247       // NOTE direct local hits should not call this
 248       //
 249       return GenericMachineType:L1Cache_wCC;
 250     } else {
 251       return ConvertMachToGenericMach(machineIDToMachineType(sender));
 252     }
 253   }
 254
 255   GenericMachineType testAndClearLocalHit(Entry cache_entry) {
 256     if (is_valid(cache_entry) && cache_entry.FromL2) {
 257       cache_entry.FromL2 := false;
 258       return GenericMachineType:L2Cache;
 259     } else {
 260       return GenericMachineType:L1Cache;
 261     }
 262   }
 263
 264   bool IsAtomicAccessed(Entry cache_entry) {
 265     assert(is_valid(cache_entry));
 266     return cache_entry.AtomicAccessed;
 267   }
 268
 269   MessageBuffer triggerQueue, ordered="false";
 270
 271   // ** OUT_PORTS **
 272
 273   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 274   out_port(responseNetwork_out, ResponseMsg, responseFromCache);
 275   out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
 276   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 277
 278   // ** IN_PORTS **
 279
 280   // Trigger Queue
 281   in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
 282     if (triggerQueue_in.isReady()) {
 283       peek(triggerQueue_in, TriggerMsg) {
 284
 285         Entry cache_entry := getCacheEntry(in_msg.Address);
 286         TBE tbe := TBEs[in_msg.Address];
 287
 288         if (in_msg.Type == TriggerType:L2_to_L1) {
 289           trigger(Event:Complete_L2_to_L1, in_msg.Address, cache_entry, tbe);
 290         } else if (in_msg.Type == TriggerType:ALL_ACKS) {
 291           trigger(Event:All_acks, in_msg.Address, cache_entry, tbe);
 292         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
 293           trigger(Event:All_acks_no_sharers, in_msg.Address, cache_entry, tbe);
 294         } else {
 295           error("Unexpected message");
 296         }
 297       }
 298     }
 299   }
 300
 301   // Nothing from the unblock network
 302
 303   // Response Network
 304   in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
 305     if (responseToCache_in.isReady()) {
 306       peek(responseToCache_in, ResponseMsg, block_on="Address") {
 307
 308         Entry cache_entry := getCacheEntry(in_msg.Address);
 309         TBE tbe := TBEs[in_msg.Address];
 310
 311         if (in_msg.Type == CoherenceResponseType:ACK) {
 312           trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
 313         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
 314           trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe);
 315         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 316           trigger(Event:Data, in_msg.Address, cache_entry, tbe);
 317         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 318           trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe);
 319         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 320           trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe);
 321         } else {
 322           error("Unexpected message");
 323         }
 324       }
 325     }
 326   }
 327
 328   // Forward Network
 329   in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
 330     if (forwardToCache_in.isReady()) {
 331       peek(forwardToCache_in, RequestMsg, block_on="Address") {
 332
 333         Entry cache_entry := getCacheEntry(in_msg.Address);
 334         TBE tbe := TBEs[in_msg.Address];
 335
 336         if (in_msg.Type == CoherenceRequestType:GETX) {
 337           trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe);
 338         } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
 339           trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe);
 340         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 341           if (machineCount(MachineType:L1Cache) > 1) {
 342             if (is_valid(cache_entry)) {
 343               if (IsAtomicAccessed(cache_entry) && no_mig_atomic) {
 344                 trigger(Event:Other_GETS_No_Mig, in_msg.Address, cache_entry, tbe);
 345               } else {
 346                 trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
 347               }
 348             } else {
 349               trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
 350             }
 351           } else {
 352             trigger(Event:NC_DMA_GETS, in_msg.Address, cache_entry, tbe);
 353           }
 354         } else if (in_msg.Type == CoherenceRequestType:INV) {
 355           trigger(Event:Invalidate, in_msg.Address, cache_entry, tbe);
 356         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 357           trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
 358         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 359           trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
 360         } else {
 361           error("Unexpected message");
 362         }
 363       }
 364     }
 365   }
 366
 367   // Nothing from the request network
 368
 369   // Mandatory Queue
 370   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
 371     if (mandatoryQueue_in.isReady()) {
 372       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 373
 374         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 375         TBE tbe := TBEs[in_msg.LineAddress];
 376
 377         if (in_msg.Type == CacheRequestType:IFETCH) {
 378           // ** INSTRUCTION ACCESS ***
 379
 380           // Check to see if it is in the OTHER L1
 381           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 382           if (is_valid(L1Dcache_entry)) {
 383             // The block is in the wrong L1, try to write it to the L2
 384             if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
 385               trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
 386             } else {
 387               trigger(Event:L2_Replacement,
 388                       L2cacheMemory.cacheProbe(in_msg.LineAddress),
 389                       getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
 390                       TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
 391             }
 392           }
 393
 394           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 395           if (is_valid(L1Icache_entry)) {
 396             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 397             trigger(mandatory_request_type_to_event(in_msg.Type),
 398                     in_msg.LineAddress, L1Icache_entry, tbe);
 399           } else {
 400             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 401               // L1 does't have the line, but we have space for it in the L1
 402
 403               Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
 404               if (is_valid(L2cache_entry)) {
 405                 // L2 has it (maybe not with the right permissions)
 406                 trigger(Event:Trigger_L2_to_L1I, in_msg.LineAddress,
 407                         L2cache_entry, tbe);
 408               } else {
 409                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 410                 trigger(mandatory_request_type_to_event(in_msg.Type),
 411                         in_msg.LineAddress, L1Icache_entry, tbe);
 412               }
 413             } else {
 414               // No room in the L1, so we need to make room
 415               if (L2cacheMemory.cacheAvail(L1IcacheMemory.cacheProbe(in_msg.LineAddress))) {
 416                 // The L2 has room, so we move the line from the L1 to the L2
 417                 trigger(Event:L1_to_L2,
 418                         L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 419                         getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 420                         TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 421               } else {
 422                 // The L2 does not have room, so we replace a line from the L2
 423                 trigger(Event:L2_Replacement,
 424                         L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 425                         getL2CacheEntry(L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress))),
 426                         TBEs[L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress))]);
 427               }
 428             }
 429           }
 430         } else {
 431           // *** DATA ACCESS ***
 432
 433           // Check to see if it is in the OTHER L1
 434           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 435           if (is_valid(L1Icache_entry)) {
 436             // The block is in the wrong L1, try to write it to the L2
 437             if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
 438               trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
 439             } else {
 440               trigger(Event:L2_Replacement,
 441                       L2cacheMemory.cacheProbe(in_msg.LineAddress),
 442                       getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
 443                       TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
 444             }
 445           }
 446
 447           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 448           if (is_valid(L1Dcache_entry)) {
 449             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 450             trigger(mandatory_request_type_to_event(in_msg.Type),
 451                     in_msg.LineAddress, L1Dcache_entry, tbe);
 452           } else {
 453             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 454               // L1 does't have the line, but we have space for it in the L1
 455               Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
 456               if (is_valid(L2cache_entry)) {
 457                 // L2 has it (maybe not with the right permissions)
 458                 trigger(Event:Trigger_L2_to_L1D, in_msg.LineAddress,
 459                         L2cache_entry, tbe);
 460               } else {
 461                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 462                 trigger(mandatory_request_type_to_event(in_msg.Type),
 463                         in_msg.LineAddress, L1Dcache_entry, tbe);
 464               }
 465             } else {
 466               // No room in the L1, so we need to make room
 467               if (L2cacheMemory.cacheAvail(L1DcacheMemory.cacheProbe(in_msg.LineAddress))) {
 468                 // The L2 has room, so we move the line from the L1 to the L2
 469                 trigger(Event:L1_to_L2,
 470                         L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 471                         getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 472                         TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 473               } else {
 474                 // The L2 does not have room, so we replace a line from the L2
 475                 trigger(Event:L2_Replacement,
 476                         L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 477                         getL2CacheEntry(L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress))),
 478                         TBEs[L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress))]);
 479               }
 480             }
 481           }
 482         }
 483       }
 484     }
 485   }
 486
 487   // ACTIONS
 488
 489   action(a_issueGETS, "a", desc="Issue GETS") {
 490     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 491       assert(is_valid(tbe));
 492       out_msg.Address := address;
 493       out_msg.Type := CoherenceRequestType:GETS;
 494       out_msg.Requestor := machineID;
 495       out_msg.Destination.add(map_Address_to_Directory(address));
 496       out_msg.MessageSize := MessageSizeType:Request_Control;
 497       out_msg.InitialRequestTime := get_time();
 498       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
 499     }
 500   }
 501
 502   action(b_issueGETX, "b", desc="Issue GETX") {
 503     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 504       assert(is_valid(tbe));
 505       out_msg.Address := address;
 506       out_msg.Type := CoherenceRequestType:GETX;
 507       out_msg.Requestor := machineID;
 508       out_msg.Destination.add(map_Address_to_Directory(address));
 509       out_msg.MessageSize := MessageSizeType:Request_Control;
 510       out_msg.InitialRequestTime := get_time();
 511       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
 512     }
 513   }
 514
 515   action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") {
 516     peek(forwardToCache_in, RequestMsg) {
 517       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 518         assert(is_valid(cache_entry));
 519         out_msg.Address := address;
 520         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 521         out_msg.Sender := machineID;
 522         out_msg.Destination.add(in_msg.Requestor);
 523         out_msg.DataBlk := cache_entry.DataBlk;
 524         out_msg.Dirty := cache_entry.Dirty;
 525         if (in_msg.DirectedProbe) {
 526           out_msg.Acks := machineCount(MachineType:L1Cache);
 527         } else {
 528           out_msg.Acks := 2;
 529         }
 530         out_msg.SilentAcks := in_msg.SilentAcks;
 531         out_msg.MessageSize := MessageSizeType:Response_Data;
 532         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 533         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 534       }
 535     }
 536   }
 537
 538   action(d_issuePUT, "d", desc="Issue PUT") {
 539     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 540       out_msg.Address := address;
 541       out_msg.Type := CoherenceRequestType:PUT;
 542       out_msg.Requestor := machineID;
 543       out_msg.Destination.add(map_Address_to_Directory(address));
 544       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 545     }
 546   }
 547
 548   action(e_sendData, "e", desc="Send data from cache to requestor") {
 549     peek(forwardToCache_in, RequestMsg) {
 550       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 551         assert(is_valid(cache_entry));
 552         out_msg.Address := address;
 553         out_msg.Type := CoherenceResponseType:DATA;
 554         out_msg.Sender := machineID;
 555         out_msg.Destination.add(in_msg.Requestor);
 556         out_msg.DataBlk := cache_entry.DataBlk;
 557         out_msg.Dirty := cache_entry.Dirty;
 558         if (in_msg.DirectedProbe) {
 559           out_msg.Acks := machineCount(MachineType:L1Cache);
 560         } else {
 561           out_msg.Acks := 2;
 562         }
 563         out_msg.SilentAcks := in_msg.SilentAcks;
 564         out_msg.MessageSize := MessageSizeType:Response_Data;
 565         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 566         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 567       }
 568     }
 569   }
 570
 571   action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, keep a shared copy") {
 572     peek(forwardToCache_in, RequestMsg) {
 573       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 574         assert(is_valid(cache_entry));
 575         out_msg.Address := address;
 576         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 577         out_msg.Sender := machineID;
 578         out_msg.Destination.add(in_msg.Requestor);
 579         out_msg.DataBlk := cache_entry.DataBlk;
 580         out_msg.Dirty := cache_entry.Dirty;
 581         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 582         if (in_msg.DirectedProbe) {
 583           out_msg.Acks := machineCount(MachineType:L1Cache);
 584         } else {
 585           out_msg.Acks := 2;
 586         }
 587         out_msg.SilentAcks := in_msg.SilentAcks;
 588         out_msg.MessageSize := MessageSizeType:Response_Data;
 589         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 590         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 591       }
 592     }
 593   }
 594
 595   action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors") {
 596     peek(forwardToCache_in, RequestMsg) {
 597       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 598         assert(is_valid(cache_entry));
 599         out_msg.Address := address;
 600         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 601         out_msg.Sender := machineID;
 602         out_msg.Destination := in_msg.MergedRequestors;
 603         out_msg.DataBlk := cache_entry.DataBlk;
 604         out_msg.Dirty := cache_entry.Dirty;
 605         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 606         out_msg.Acks := machineCount(MachineType:L1Cache);
 607         out_msg.SilentAcks := in_msg.SilentAcks;
 608         out_msg.MessageSize := MessageSizeType:Response_Data;
 609         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 610         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 611       }
 612     }
 613   }
 614
 615   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 616     peek(forwardToCache_in, RequestMsg) {
 617       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 618         out_msg.Address := address;
 619         out_msg.Type := CoherenceResponseType:ACK;
 620         out_msg.Sender := machineID;
 621         out_msg.Destination.add(in_msg.Requestor);
 622         out_msg.Acks := 1;
 623         out_msg.SilentAcks := in_msg.SilentAcks;
 624         assert(in_msg.DirectedProbe == false);
 625         out_msg.MessageSize := MessageSizeType:Response_Control;
 626         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 627         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 628       }
 629     }
 630   }
 631
 632   action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") {
 633     peek(forwardToCache_in, RequestMsg) {
 634       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 635         out_msg.Address := address;
 636         out_msg.Type := CoherenceResponseType:ACK_SHARED;
 637         out_msg.Sender := machineID;
 638         out_msg.Destination.add(in_msg.Requestor);
 639         out_msg.Acks := 1;
 640         out_msg.SilentAcks := in_msg.SilentAcks;
 641         assert(in_msg.DirectedProbe == false);
 642         out_msg.MessageSize := MessageSizeType:Response_Control;
 643         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 644         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 645       }
 646     }
 647   }
 648
 649   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 650     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 651       out_msg.Address := address;
 652       out_msg.Type := CoherenceResponseType:UNBLOCK;
 653       out_msg.Sender := machineID;
 654       out_msg.Destination.add(map_Address_to_Directory(address));
 655       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 656     }
 657   }
 658
 659   action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") {
 660     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 661       out_msg.Address := address;
 662       out_msg.Type := CoherenceResponseType:UNBLOCKM;
 663       out_msg.Sender := machineID;
 664       out_msg.Destination.add(map_Address_to_Directory(address));
 665       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 666     }
 667   }
 668
 669   action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") {
 670     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 671       assert(is_valid(tbe));
 672       out_msg.Address := address;
 673       out_msg.Type := CoherenceResponseType:UNBLOCKS;
 674       out_msg.Sender := machineID;
 675       out_msg.CurOwner := tbe.CurOwner;
 676       out_msg.Destination.add(map_Address_to_Directory(address));
 677       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 678     }
 679   }
 680
 681   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 682     assert(is_valid(cache_entry));
 683     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 684     sequencer.readCallback(address, testAndClearLocalHit(cache_entry),
 685                            cache_entry.DataBlk);
 686   }
 687
 688   action(hx_external_load_hit, "hx", desc="load required external msgs") {
 689     assert(is_valid(cache_entry));
 690     assert(is_valid(tbe));
 691     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 692     peek(responseToCache_in, ResponseMsg) {
 693
 694       sequencer.readCallback(address,
 695                              getNondirectHitMachType(in_msg.Address, in_msg.Sender),
 696                              cache_entry.DataBlk,
 697                              tbe.InitialRequestTime,
 698                              tbe.ForwardRequestTime,
 699                              tbe.FirstResponseTime);
 700     }
 701   }
 702
 703   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 704     assert(is_valid(cache_entry));
 705     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 706     peek(mandatoryQueue_in, CacheMsg) {
 707       sequencer.writeCallback(address, testAndClearLocalHit(cache_entry),
 708                               cache_entry.DataBlk);
 709
 710       cache_entry.Dirty := true;
 711       if (in_msg.Type == CacheRequestType:ATOMIC) {
 712         cache_entry.AtomicAccessed := true;
 713       }
 714     }
 715   }
 716
 717   action(sx_external_store_hit, "sx", desc="store required external msgs.") {
 718     assert(is_valid(cache_entry));
 719     assert(is_valid(tbe));
 720     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 721     peek(responseToCache_in, ResponseMsg) {
 722
 723       sequencer.writeCallback(address,
 724                               getNondirectHitMachType(address, in_msg.Sender),
 725                               cache_entry.DataBlk,
 726                               tbe.InitialRequestTime,
 727                               tbe.ForwardRequestTime,
 728                               tbe.FirstResponseTime);
 729     }
 730     cache_entry.Dirty := true;
 731   }
 732
 733   action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
 734     assert(is_valid(cache_entry));
 735     assert(is_valid(tbe));
 736     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 737
 738     sequencer.writeCallback(address,
 739                             getNondirectHitMachType(address, tbe.LastResponder),
 740                             cache_entry.DataBlk,
 741                             tbe.InitialRequestTime,
 742                             tbe.ForwardRequestTime,
 743                             tbe.FirstResponseTime);
 744
 745     cache_entry.Dirty := true;
 746   }
 747
 748   action(i_allocateTBE, "i", desc="Allocate TBE") {
 749     check_allocate(TBEs);
 750     assert(is_valid(cache_entry));
 751     TBEs.allocate(address);
 752     set_tbe(TBEs[address]);
 753     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
 754     tbe.Dirty := cache_entry.Dirty;
 755     tbe.Sharers := false;
 756   }
 757
 758   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 759     triggerQueue_in.dequeue();
 760   }
 761
 762   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 763     mandatoryQueue_in.dequeue();
 764   }
 765
 766   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 767     forwardToCache_in.dequeue();
 768   }
 769
 770   action(hp_copyFromTBEToL2, "li", desc="Copy data from TBE to L2 cache entry.") {
 771     assert(is_valid(cache_entry));
 772     assert(is_valid(tbe));
 773     cache_entry.Dirty   := tbe.Dirty;
 774     cache_entry.DataBlk := tbe.DataBlk;
 775   }
 776
 777   action(nb_copyFromTBEToL1, "fu", desc="Copy data from TBE to L1 cache entry.") {
 778     assert(is_valid(cache_entry));
 779     assert(is_valid(tbe));
 780     cache_entry.Dirty   := tbe.Dirty;
 781     cache_entry.DataBlk := tbe.DataBlk;
 782     cache_entry.FromL2 := true;
 783   }
 784
 785   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 786     peek(responseToCache_in, ResponseMsg) {
 787       assert(in_msg.Acks > 0);
 788       assert(is_valid(tbe));
 789       DPRINTF(RubySlicc, "Sender = %s\n", in_msg.Sender);
 790       DPRINTF(RubySlicc, "SilentAcks = %d\n", in_msg.SilentAcks);
 791       if (tbe.AppliedSilentAcks == false) {
 792         tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.SilentAcks;
 793         tbe.AppliedSilentAcks := true;
 794       }
 795       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 796       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 797       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 798       APPEND_TRANSITION_COMMENT(tbe.NumPendingMsgs);
 799       APPEND_TRANSITION_COMMENT(in_msg.Sender);
 800       tbe.LastResponder := in_msg.Sender;
 801       if (tbe.InitialRequestTime != zero_time() && in_msg.InitialRequestTime != zero_time()) {
 802         assert(tbe.InitialRequestTime == in_msg.InitialRequestTime);
 803       }
 804       if (in_msg.InitialRequestTime != zero_time()) {
 805         tbe.InitialRequestTime := in_msg.InitialRequestTime;
 806       }
 807       if (tbe.ForwardRequestTime != zero_time() && in_msg.ForwardRequestTime != zero_time()) {
 808         assert(tbe.ForwardRequestTime == in_msg.ForwardRequestTime);
 809       }
 810       if (in_msg.ForwardRequestTime != zero_time()) {
 811         tbe.ForwardRequestTime := in_msg.ForwardRequestTime;
 812       }
 813       if (tbe.FirstResponseTime == zero_time()) {
 814         tbe.FirstResponseTime := get_time();
 815       }
 816     }
 817   }
 818   action(uo_updateCurrentOwner, "uo", desc="When moving SS state, update current owner.") {
 819     peek(responseToCache_in, ResponseMsg) {
 820       assert(is_valid(tbe));
 821       tbe.CurOwner := in_msg.Sender;
 822     }
 823   }
 824
 825   action(n_popResponseQueue, "n", desc="Pop response queue") {
 826     responseToCache_in.dequeue();
 827   }
 828
 829   action(ll_L2toL1Transfer, "ll", desc="") {
 830     enqueue(triggerQueue_out, TriggerMsg, latency=l2_cache_hit_latency) {
 831       out_msg.Address := address;
 832       out_msg.Type := TriggerType:L2_to_L1;
 833     }
 834   }
 835
 836   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 837     assert(is_valid(tbe));
 838     if (tbe.NumPendingMsgs == 0) {
 839       enqueue(triggerQueue_out, TriggerMsg) {
 840         out_msg.Address := address;
 841         if (tbe.Sharers) {
 842           out_msg.Type := TriggerType:ALL_ACKS;
 843         } else {
 844           out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
 845         }
 846       }
 847     }
 848   }
 849
 850   action(p_decrementNumberOfMessagesByOne, "p", desc="Decrement the number of messages for which we're waiting by one") {
 851     assert(is_valid(tbe));
 852     tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
 853   }
 854
 855   action(pp_incrementNumberOfMessagesByOne, "\p", desc="Increment the number of messages for which we're waiting by one") {
 856     assert(is_valid(tbe));
 857     tbe.NumPendingMsgs := tbe.NumPendingMsgs + 1;
 858   }
 859
 860   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 861     peek(forwardToCache_in, RequestMsg) {
 862         assert(in_msg.Requestor != machineID);
 863       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 864         assert(is_valid(tbe));
 865         out_msg.Address := address;
 866         out_msg.Type := CoherenceResponseType:DATA;
 867         out_msg.Sender := machineID;
 868         out_msg.Destination.add(in_msg.Requestor);
 869         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 870         out_msg.DataBlk := tbe.DataBlk;
 871         out_msg.Dirty := tbe.Dirty;
 872         if (in_msg.DirectedProbe) {
 873           out_msg.Acks := machineCount(MachineType:L1Cache);
 874         } else {
 875           out_msg.Acks := 2;
 876         }
 877         out_msg.SilentAcks := in_msg.SilentAcks;
 878         out_msg.MessageSize := MessageSizeType:Response_Data;
 879         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 880         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 881       }
 882     }
 883   }
 884
 885   action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, multiple sharers") {
 886     peek(forwardToCache_in, RequestMsg) {
 887       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 888         assert(is_valid(tbe));
 889         out_msg.Address := address;
 890         out_msg.Type := CoherenceResponseType:DATA;
 891         out_msg.Sender := machineID;
 892         out_msg.Destination := in_msg.MergedRequestors;
 893         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 894         out_msg.DataBlk := tbe.DataBlk;
 895         out_msg.Dirty := tbe.Dirty;
 896         out_msg.Acks := machineCount(MachineType:L1Cache);
 897         out_msg.SilentAcks := in_msg.SilentAcks;
 898         out_msg.MessageSize := MessageSizeType:Response_Data;
 899         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 900         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 901       }
 902     }
 903   }
 904
 905   action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
 906     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 907       assert(is_valid(tbe));
 908       out_msg.Address := address;
 909       out_msg.Sender := machineID;
 910       out_msg.Destination.add(map_Address_to_Directory(address));
 911       out_msg.Dirty := tbe.Dirty;
 912       if (tbe.Dirty) {
 913         out_msg.Type := CoherenceResponseType:WB_DIRTY;
 914         out_msg.DataBlk := tbe.DataBlk;
 915         out_msg.MessageSize := MessageSizeType:Writeback_Data;
 916       } else {
 917         out_msg.Type := CoherenceResponseType:WB_CLEAN;
 918         // NOTE: in a real system this would not send data.  We send
 919         // data here only so we can check it at the memory
 920         out_msg.DataBlk := tbe.DataBlk;
 921         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 922       }
 923     }
 924   }
 925
 926   action(r_setSharerBit, "r", desc="We saw other sharers") {
 927     assert(is_valid(tbe));
 928     tbe.Sharers := true;
 929   }
 930
 931   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 932     TBEs.deallocate(address);
 933     unset_tbe();
 934   }
 935
 936   action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") {
 937     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
 938       assert(is_valid(tbe));
 939       out_msg.Address := address;
 940       out_msg.Sender := machineID;
 941       out_msg.Destination.add(map_Address_to_Directory(address));
 942       out_msg.DataBlk := tbe.DataBlk;
 943       out_msg.Dirty := tbe.Dirty;
 944       if (tbe.Dirty) {
 945         out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_DIRTY;
 946         out_msg.DataBlk := tbe.DataBlk;
 947         out_msg.MessageSize := MessageSizeType:Writeback_Data;
 948       } else {
 949         out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_CLEAN;
 950         // NOTE: in a real system this would not send data.  We send
 951         // data here only so we can check it at the memory
 952         out_msg.DataBlk := tbe.DataBlk;
 953         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 954       }
 955     }
 956   }
 957
 958   action(u_writeDataToCache, "u", desc="Write data to cache") {
 959     peek(responseToCache_in, ResponseMsg) {
 960       assert(is_valid(cache_entry));
 961       cache_entry.DataBlk := in_msg.DataBlk;
 962       cache_entry.Dirty := in_msg.Dirty;
 963     }
 964   }
 965
 966   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
 967     peek(responseToCache_in, ResponseMsg) {
 968       assert(is_valid(cache_entry));
 969       DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
 970               cache_entry.DataBlk, in_msg.DataBlk);
 971       assert(cache_entry.DataBlk == in_msg.DataBlk);
 972       cache_entry.DataBlk := in_msg.DataBlk;
 973       cache_entry.Dirty := in_msg.Dirty || cache_entry.Dirty;
 974     }
 975   }
 976
 977   action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 978     if (L1DcacheMemory.isTagPresent(address)) {
 979       L1DcacheMemory.deallocate(address);
 980     } else {
 981       L1IcacheMemory.deallocate(address);
 982     }
 983     unset_cache_entry();
 984   }
 985
 986   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
 987     if (is_invalid(cache_entry)) {
 988       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
 989     }
 990   }
 991
 992   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
 993     if (is_invalid(cache_entry)) {
 994       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
 995     }
 996   }
 997
 998   action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
 999     set_cache_entry(L2cacheMemory.allocate(address, new Entry));
1000   }
1001
1002   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
1003     L2cacheMemory.deallocate(address);
1004     unset_cache_entry();
1005   }
1006
1007   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
1008     peek(mandatoryQueue_in, CacheMsg) {
1009       if (L1IcacheMemory.isTagPresent(address)) {
1010         L1IcacheMemory.profileMiss(in_msg);
1011       } else if (L1DcacheMemory.isTagPresent(address)) {
1012         L1DcacheMemory.profileMiss(in_msg);
1013       }
1014       if (L2cacheMemory.isTagPresent(address) == false) {
1015         L2cacheMemory.profileMiss(in_msg);
1016       }
1017     }
1018   }
1019
1020   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1021     stall_and_wait(mandatoryQueue_in, address);
1022   }
1023
1024   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1025     wake_up_dependents(address);
1026   }
1027
1028   action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1029     wake_up_all_dependents();
1030   }
1031
1032   //*****************************************************
1033   // TRANSITIONS
1034   //*****************************************************
1035
1036   // Transitions for Load/Store/L2_Replacement from transient states
1037   transition({IM, SM, ISM, OM, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) {
1038     zz_stallAndWaitMandatoryQueue;
1039   }
1040
1041   transition({M_W, MM_W}, {L2_Replacement}) {
1042     zz_stallAndWaitMandatoryQueue;
1043   }
1044
1045   transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT}, {Load, Ifetch}) {
1046     zz_stallAndWaitMandatoryQueue;
1047   }
1048
1049   transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT}, L1_to_L2) {
1050     zz_stallAndWaitMandatoryQueue;
1051   }
1052
1053   transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
1054     // stall
1055   }
1056
1057   // Transitions moving data between the L1 and L2 caches
1058   transition({I, S, O, M, MM}, L1_to_L2) {
1059     i_allocateTBE;
1060     gg_deallocateL1CacheBlock;
1061     vv_allocateL2CacheBlock;
1062     hp_copyFromTBEToL2;
1063     s_deallocateTBE;
1064     ka_wakeUpAllDependents;
1065   }
1066
1067   transition(I, Trigger_L2_to_L1D, IT) {
1068     i_allocateTBE;
1069     rr_deallocateL2CacheBlock;
1070     ii_allocateL1DCacheBlock;
1071     nb_copyFromTBEToL1; // Not really needed for state I
1072     s_deallocateTBE;
1073     uu_profileMiss;
1074     zz_stallAndWaitMandatoryQueue;
1075     ll_L2toL1Transfer;
1076   }
1077
1078   transition(S, Trigger_L2_to_L1D, ST) {
1079     i_allocateTBE;
1080     rr_deallocateL2CacheBlock;
1081     ii_allocateL1DCacheBlock;
1082     nb_copyFromTBEToL1;
1083     s_deallocateTBE;
1084     uu_profileMiss;
1085     zz_stallAndWaitMandatoryQueue;
1086     ll_L2toL1Transfer;
1087   }
1088
1089   transition(O, Trigger_L2_to_L1D, OT) {
1090     i_allocateTBE;
1091     rr_deallocateL2CacheBlock;
1092     ii_allocateL1DCacheBlock;
1093     nb_copyFromTBEToL1;
1094     s_deallocateTBE;
1095     uu_profileMiss;
1096     zz_stallAndWaitMandatoryQueue;
1097     ll_L2toL1Transfer;
1098   }
1099
1100   transition(M, Trigger_L2_to_L1D, MT) {
1101     i_allocateTBE;
1102     rr_deallocateL2CacheBlock;
1103     ii_allocateL1DCacheBlock;
1104     nb_copyFromTBEToL1;
1105     s_deallocateTBE;
1106     uu_profileMiss;
1107     zz_stallAndWaitMandatoryQueue;
1108     ll_L2toL1Transfer;
1109   }
1110
1111   transition(MM, Trigger_L2_to_L1D, MMT) {
1112     i_allocateTBE;
1113     rr_deallocateL2CacheBlock;
1114     ii_allocateL1DCacheBlock;
1115     nb_copyFromTBEToL1;
1116     s_deallocateTBE;
1117     uu_profileMiss;
1118     zz_stallAndWaitMandatoryQueue;
1119     ll_L2toL1Transfer;
1120   }
1121
1122   transition(I, Trigger_L2_to_L1I, IT) {
1123     i_allocateTBE;
1124     rr_deallocateL2CacheBlock;
1125     jj_allocateL1ICacheBlock;
1126     nb_copyFromTBEToL1;
1127     s_deallocateTBE;
1128     uu_profileMiss;
1129     zz_stallAndWaitMandatoryQueue;
1130     ll_L2toL1Transfer;
1131   }
1132
1133   transition(S, Trigger_L2_to_L1I, ST) {
1134     i_allocateTBE;
1135     rr_deallocateL2CacheBlock;
1136     jj_allocateL1ICacheBlock;
1137     nb_copyFromTBEToL1;
1138     s_deallocateTBE;
1139     uu_profileMiss;
1140     zz_stallAndWaitMandatoryQueue;
1141     ll_L2toL1Transfer;
1142   }
1143
1144   transition(O, Trigger_L2_to_L1I, OT) {
1145     i_allocateTBE;
1146     rr_deallocateL2CacheBlock;
1147     jj_allocateL1ICacheBlock;
1148     nb_copyFromTBEToL1;
1149     s_deallocateTBE;
1150     uu_profileMiss;
1151     zz_stallAndWaitMandatoryQueue;
1152     ll_L2toL1Transfer;
1153   }
1154
1155   transition(M, Trigger_L2_to_L1I, MT) {
1156     i_allocateTBE;
1157     rr_deallocateL2CacheBlock;
1158     jj_allocateL1ICacheBlock;
1159     nb_copyFromTBEToL1;
1160     s_deallocateTBE;
1161     uu_profileMiss;
1162     zz_stallAndWaitMandatoryQueue;
1163     ll_L2toL1Transfer;
1164   }
1165
1166   transition(MM, Trigger_L2_to_L1I, MMT) {
1167     i_allocateTBE;
1168     rr_deallocateL2CacheBlock;
1169     jj_allocateL1ICacheBlock;
1170     nb_copyFromTBEToL1;
1171     s_deallocateTBE;
1172     uu_profileMiss;
1173     zz_stallAndWaitMandatoryQueue;
1174     ll_L2toL1Transfer;
1175   }
1176
1177   transition(IT, Complete_L2_to_L1, I) {
1178     j_popTriggerQueue;
1179     kd_wakeUpDependents;
1180   }
1181
1182   transition(ST, Complete_L2_to_L1, S) {
1183     j_popTriggerQueue;
1184     kd_wakeUpDependents;
1185   }
1186
1187   transition(OT, Complete_L2_to_L1, O) {
1188     j_popTriggerQueue;
1189     kd_wakeUpDependents;
1190   }
1191
1192   transition(MT, Complete_L2_to_L1, M) {
1193     j_popTriggerQueue;
1194     kd_wakeUpDependents;
1195   }
1196
1197   transition(MMT, Complete_L2_to_L1, MM) {
1198     j_popTriggerQueue;
1199     kd_wakeUpDependents;
1200   }
1201
1202   // Transitions from Idle
1203   transition(I, Load, IS) {
1204     ii_allocateL1DCacheBlock;
1205     i_allocateTBE;
1206     a_issueGETS;
1207     uu_profileMiss;
1208     k_popMandatoryQueue;
1209   }
1210
1211   transition(I, Ifetch, IS) {
1212     jj_allocateL1ICacheBlock;
1213     i_allocateTBE;
1214     a_issueGETS;
1215     uu_profileMiss;
1216     k_popMandatoryQueue;
1217   }
1218
1219   transition(I, Store, IM) {
1220     ii_allocateL1DCacheBlock;
1221     i_allocateTBE;
1222     b_issueGETX;
1223     uu_profileMiss;
1224     k_popMandatoryQueue;
1225   }
1226
1227   transition(I, L2_Replacement) {
1228     rr_deallocateL2CacheBlock;
1229     ka_wakeUpAllDependents;
1230   }
1231
1232   transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1233     f_sendAck;
1234     l_popForwardQueue;
1235   }
1236
1237   // Transitions from Shared
1238   transition({S, SM, ISM}, {Load, Ifetch}) {
1239     h_load_hit;
1240     k_popMandatoryQueue;
1241   }
1242
1243   transition(S, Store, SM) {
1244     i_allocateTBE;
1245     b_issueGETX;
1246     uu_profileMiss;
1247     k_popMandatoryQueue;
1248   }
1249
1250   transition(S, L2_Replacement, I) {
1251     rr_deallocateL2CacheBlock;
1252     ka_wakeUpAllDependents;
1253   }
1254
1255   transition(S, {Other_GETX, Invalidate}, I) {
1256     f_sendAck;
1257     l_popForwardQueue;
1258   }
1259
1260   transition(S, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1261     ff_sendAckShared;
1262     l_popForwardQueue;
1263   }
1264
1265   // Transitions from Owned
1266   transition({O, OM, SS, MM_W, M_W}, {Load, Ifetch}) {
1267     h_load_hit;
1268     k_popMandatoryQueue;
1269   }
1270
1271   transition(O, Store, OM) {
1272     i_allocateTBE;
1273     b_issueGETX;
1274     p_decrementNumberOfMessagesByOne;
1275     uu_profileMiss;
1276     k_popMandatoryQueue;
1277   }
1278
1279   transition(O, L2_Replacement, OI) {
1280     i_allocateTBE;
1281     d_issuePUT;
1282     rr_deallocateL2CacheBlock;
1283     ka_wakeUpAllDependents;
1284   }
1285
1286   transition(O, {Other_GETX, Invalidate}, I) {
1287     e_sendData;
1288     l_popForwardQueue;
1289   }
1290
1291   transition(O, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1292     ee_sendDataShared;
1293     l_popForwardQueue;
1294   }
1295
1296   transition(O, Merged_GETS) {
1297     em_sendDataSharedMultiple;
1298     l_popForwardQueue;
1299   }
1300
1301   // Transitions from Modified
1302   transition(MM, {Load, Ifetch}) {
1303     h_load_hit;
1304     k_popMandatoryQueue;
1305   }
1306
1307   transition(MM, Store) {
1308     hh_store_hit;
1309     k_popMandatoryQueue;
1310   }
1311
1312   transition(MM, L2_Replacement, MI) {
1313     i_allocateTBE;
1314     d_issuePUT;
1315     rr_deallocateL2CacheBlock;
1316     ka_wakeUpAllDependents;
1317   }
1318
1319   transition(MM, {Other_GETX, Invalidate}, I) {
1320     c_sendExclusiveData;
1321     l_popForwardQueue;
1322   }
1323
1324   transition(MM, Other_GETS, I) {
1325     c_sendExclusiveData;
1326     l_popForwardQueue;
1327   }
1328
1329   transition(MM, NC_DMA_GETS) {
1330     c_sendExclusiveData;
1331     l_popForwardQueue;
1332   }
1333
1334   transition(MM, Other_GETS_No_Mig, O) {
1335     ee_sendDataShared;
1336     l_popForwardQueue;
1337   }
1338
1339   transition(MM, Merged_GETS, O) {
1340     em_sendDataSharedMultiple;
1341     l_popForwardQueue;
1342   }
1343
1344   // Transitions from Dirty Exclusive
1345   transition(M, {Load, Ifetch}) {
1346     h_load_hit;
1347     k_popMandatoryQueue;
1348   }
1349
1350   transition(M, Store, MM) {
1351     hh_store_hit;
1352     k_popMandatoryQueue;
1353   }
1354
1355   transition(M, L2_Replacement, MI) {
1356     i_allocateTBE;
1357     d_issuePUT;
1358     rr_deallocateL2CacheBlock;
1359     ka_wakeUpAllDependents;
1360   }
1361
1362   transition(M, {Other_GETX, Invalidate}, I) {
1363     c_sendExclusiveData;
1364     l_popForwardQueue;
1365   }
1366
1367   transition(M, {Other_GETS, Other_GETS_No_Mig}, O) {
1368     ee_sendDataShared;
1369     l_popForwardQueue;
1370   }
1371
1372   transition(M, NC_DMA_GETS) {
1373     ee_sendDataShared;
1374     l_popForwardQueue;
1375   }
1376
1377   transition(M, Merged_GETS, O) {
1378     em_sendDataSharedMultiple;
1379     l_popForwardQueue;
1380   }
1381
1382   // Transitions from IM
1383
1384   transition(IM, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1385     f_sendAck;
1386     l_popForwardQueue;
1387   }
1388
1389   transition(IM, Ack) {
1390     m_decrementNumberOfMessages;
1391     o_checkForCompletion;
1392     n_popResponseQueue;
1393   }
1394
1395   transition(IM, Data, ISM) {
1396     u_writeDataToCache;
1397     m_decrementNumberOfMessages;
1398     o_checkForCompletion;
1399     n_popResponseQueue;
1400   }
1401
1402   transition(IM, Exclusive_Data, MM_W) {
1403     u_writeDataToCache;
1404     m_decrementNumberOfMessages;
1405     o_checkForCompletion;
1406     sx_external_store_hit;
1407     n_popResponseQueue;
1408     kd_wakeUpDependents;
1409   }
1410
1411   // Transitions from SM
1412   transition(SM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1413     ff_sendAckShared;
1414     l_popForwardQueue;
1415   }
1416
1417   transition(SM, {Other_GETX, Invalidate}, IM) {
1418     f_sendAck;
1419     l_popForwardQueue;
1420   }
1421
1422   transition(SM, Ack) {
1423     m_decrementNumberOfMessages;
1424     o_checkForCompletion;
1425     n_popResponseQueue;
1426   }
1427
1428   transition(SM, {Data, Exclusive_Data}, ISM) {
1429     v_writeDataToCacheVerify;
1430     m_decrementNumberOfMessages;
1431     o_checkForCompletion;
1432     n_popResponseQueue;
1433   }
1434
1435   // Transitions from ISM
1436   transition(ISM, Ack) {
1437     m_decrementNumberOfMessages;
1438     o_checkForCompletion;
1439     n_popResponseQueue;
1440   }
1441
1442   transition(ISM, All_acks_no_sharers, MM) {
1443     sxt_trig_ext_store_hit;
1444     gm_sendUnblockM;
1445     s_deallocateTBE;
1446     j_popTriggerQueue;
1447     kd_wakeUpDependents;
1448   }
1449
1450   // Transitions from OM
1451
1452   transition(OM, {Other_GETX, Invalidate}, IM) {
1453     e_sendData;
1454     pp_incrementNumberOfMessagesByOne;
1455     l_popForwardQueue;
1456   }
1457
1458   transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1459     ee_sendDataShared;
1460     l_popForwardQueue;
1461   }
1462
1463   transition(OM, Merged_GETS) {
1464     em_sendDataSharedMultiple;
1465     l_popForwardQueue;
1466   }
1467
1468   transition(OM, Ack) {
1469     m_decrementNumberOfMessages;
1470     o_checkForCompletion;
1471     n_popResponseQueue;
1472   }
1473
1474   transition(OM, {All_acks, All_acks_no_sharers}, MM) {
1475     sxt_trig_ext_store_hit;
1476     gm_sendUnblockM;
1477     s_deallocateTBE;
1478     j_popTriggerQueue;
1479     kd_wakeUpDependents;
1480   }
1481
1482   // Transitions from IS
1483
1484   transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1485     f_sendAck;
1486     l_popForwardQueue;
1487   }
1488
1489   transition(IS, Ack) {
1490     m_decrementNumberOfMessages;
1491     o_checkForCompletion;
1492     n_popResponseQueue;
1493   }
1494
1495   transition(IS, Shared_Ack) {
1496     m_decrementNumberOfMessages;
1497     r_setSharerBit;
1498     o_checkForCompletion;
1499     n_popResponseQueue;
1500   }
1501
1502   transition(IS, Data, SS) {
1503     u_writeDataToCache;
1504     m_decrementNumberOfMessages;
1505     o_checkForCompletion;
1506     hx_external_load_hit;
1507     uo_updateCurrentOwner;
1508     n_popResponseQueue;
1509     kd_wakeUpDependents;
1510   }
1511
1512   transition(IS, Exclusive_Data, M_W) {
1513     u_writeDataToCache;
1514     m_decrementNumberOfMessages;
1515     o_checkForCompletion;
1516     hx_external_load_hit;
1517     n_popResponseQueue;
1518     kd_wakeUpDependents;
1519   }
1520
1521   transition(IS, Shared_Data, SS) {
1522     u_writeDataToCache;
1523     r_setSharerBit;
1524     m_decrementNumberOfMessages;
1525     o_checkForCompletion;
1526     hx_external_load_hit;
1527     uo_updateCurrentOwner;
1528     n_popResponseQueue;
1529     kd_wakeUpDependents;
1530   }
1531
1532   // Transitions from SS
1533
1534   transition(SS, Ack) {
1535     m_decrementNumberOfMessages;
1536     o_checkForCompletion;
1537     n_popResponseQueue;
1538   }
1539
1540   transition(SS, Shared_Ack) {
1541     m_decrementNumberOfMessages;
1542     r_setSharerBit;
1543     o_checkForCompletion;
1544     n_popResponseQueue;
1545   }
1546
1547   transition(SS, All_acks, S) {
1548     gs_sendUnblockS;
1549     s_deallocateTBE;
1550     j_popTriggerQueue;
1551   }
1552
1553   transition(SS, All_acks_no_sharers, S) {
1554     // Note: The directory might still be the owner, so that is why we go to S
1555     gs_sendUnblockS;
1556     s_deallocateTBE;
1557     j_popTriggerQueue;
1558   }
1559
1560   // Transitions from MM_W
1561
1562   transition(MM_W, Store) {
1563     hh_store_hit;
1564     k_popMandatoryQueue;
1565   }
1566
1567   transition(MM_W, Ack) {
1568     m_decrementNumberOfMessages;
1569     o_checkForCompletion;
1570     n_popResponseQueue;
1571   }
1572
1573   transition(MM_W, All_acks_no_sharers, MM) {
1574     gm_sendUnblockM;
1575     s_deallocateTBE;
1576     j_popTriggerQueue;
1577     kd_wakeUpDependents;
1578   }
1579
1580   // Transitions from M_W
1581
1582   transition(M_W, Store, MM_W) {
1583     hh_store_hit;
1584     k_popMandatoryQueue;
1585   }
1586
1587   transition(M_W, Ack) {
1588     m_decrementNumberOfMessages;
1589     o_checkForCompletion;
1590     n_popResponseQueue;
1591   }
1592
1593   transition(M_W, All_acks_no_sharers, M) {
1594     gm_sendUnblockM;
1595     s_deallocateTBE;
1596     j_popTriggerQueue;
1597     kd_wakeUpDependents;
1598   }
1599
1600   // Transitions from OI/MI
1601
1602   transition({OI, MI}, {Other_GETX, Invalidate}, II) {
1603     q_sendDataFromTBEToCache;
1604     l_popForwardQueue;
1605   }
1606
1607   transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
1608     q_sendDataFromTBEToCache;
1609     l_popForwardQueue;
1610   }
1611
1612   transition({OI, MI}, Merged_GETS, OI) {
1613     qm_sendDataFromTBEToCache;
1614     l_popForwardQueue;
1615   }
1616
1617   transition(MI, Writeback_Ack, I) {
1618     t_sendExclusiveDataFromTBEToMemory;
1619     s_deallocateTBE;
1620     l_popForwardQueue;
1621     kd_wakeUpDependents;
1622   }
1623
1624   transition(OI, Writeback_Ack, I) {
1625     qq_sendDataFromTBEToMemory;
1626     s_deallocateTBE;
1627     l_popForwardQueue;
1628     kd_wakeUpDependents;
1629   }
1630
1631   // Transitions from II
1632   transition(II, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
1633     f_sendAck;
1634     l_popForwardQueue;
1635   }
1636
1637   transition(II, Writeback_Ack, I) {
1638     g_sendUnblock;
1639     s_deallocateTBE;
1640     l_popForwardQueue;
1641     kd_wakeUpDependents;
1642   }
1643
1644   transition(II, Writeback_Nack, I) {
1645     s_deallocateTBE;
1646     l_popForwardQueue;
1647     kd_wakeUpDependents;
1648   }
1649 }