2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * AMD's contributions to the MOESI hammer protocol do not constitute an
30 * endorsement of its similarity to any AMD products.
32 * Authors: Milo Martin
36 machine(MachineType:L1Cache, "AMD Hammer-like protocol")
37 : Sequencer * sequencer;
38 CacheMemory * L1Icache;
39 CacheMemory * L1Dcache;
40 CacheMemory * L2cache;
41 Cycles cache_response_latency := 10;
42 Cycles issue_latency := 2;
43 Cycles l2_cache_hit_latency := 10;
44 bool no_mig_atomic := "True";
48 MessageBuffer * requestFromCache, network="To", virtual_network="2",
50 MessageBuffer * responseFromCache, network="To", virtual_network="4",
52 MessageBuffer * unblockFromCache, network="To", virtual_network="5",
55 MessageBuffer * forwardToCache, network="From", virtual_network="3",
57 MessageBuffer * responseToCache, network="From", virtual_network="4",
60 MessageBuffer * mandatoryQueue;
62 MessageBuffer * triggerQueue;
65 state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
67 I, AccessPermission:Invalid, desc="Idle";
68 S, AccessPermission:Read_Only, desc="Shared";
69 O, AccessPermission:Read_Only, desc="Owned";
70 M, AccessPermission:Read_Only, desc="Modified (dirty)";
71 MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
73 // Base states, locked and ready to service the mandatory queue
74 IR, AccessPermission:Invalid, desc="Idle";
75 SR, AccessPermission:Read_Only, desc="Shared";
76 OR, AccessPermission:Read_Only, desc="Owned";
77 MR, AccessPermission:Read_Only, desc="Modified (dirty)";
78 MMR, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
81 IM, AccessPermission:Busy, "IM", desc="Issued GetX";
82 SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have a valid copy of the line";
83 OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
84 ISM, AccessPermission:Read_Only, "ISM", desc="Issued GetX, received valid data, waiting for all acks";
85 M_W, AccessPermission:Read_Only, "M^W", desc="Issued GetS, received exclusive data";
86 MM_W, AccessPermission:Read_Write, "MM^W", desc="Issued GetX, received exclusive data";
87 IS, AccessPermission:Busy, "IS", desc="Issued GetS";
88 SS, AccessPermission:Read_Only, "SS", desc="Issued GetS, received data, waiting for all acks";
89 OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
90 MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
91 II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack";
92 ST, AccessPermission:Busy, "ST", desc="S block transferring to L1";
93 OT, AccessPermission:Busy, "OT", desc="O block transferring to L1";
94 MT, AccessPermission:Busy, "MT", desc="M block transferring to L1";
95 MMT, AccessPermission:Busy, "MMT", desc="MM block transferring to L0";
97 //Transition States Related to Flushing
98 MI_F, AccessPermission:Busy, "MI_F", desc="Issued PutX due to a Flush, waiting for ack";
99 MM_F, AccessPermission:Busy, "MM_F", desc="Issued GETF due to a Flush, waiting for ack";
100 IM_F, AccessPermission:Busy, "IM_F", desc="Issued GetX due to a Flush";
101 ISM_F, AccessPermission:Read_Only, "ISM_F", desc="Issued GetX, received data, waiting for all acks";
102 SM_F, AccessPermission:Read_Only, "SM_F", desc="Issued GetX, we still have an old copy of the line";
103 OM_F, AccessPermission:Read_Only, "OM_F", desc="Issued GetX, received data";
104 MM_WF, AccessPermission:Busy, "MM_WF", desc="Issued GetX, received exclusive data";
108 enumeration(Event, desc="Cache events") {
109 Load, desc="Load request from the processor";
110 Ifetch, desc="I-fetch request from the processor";
111 Store, desc="Store request from the processor";
112 L2_Replacement, desc="L2 Replacement";
113 L1_to_L2, desc="L1 to L2 transfer";
114 Trigger_L2_to_L1D, desc="Trigger L2 to L1-Data transfer";
115 Trigger_L2_to_L1I, desc="Trigger L2 to L1-Instruction transfer";
116 Complete_L2_to_L1, desc="L2 to L1 transfer completed";
119 Other_GETX, desc="A GetX from another processor";
120 Other_GETS, desc="A GetS from another processor";
121 Merged_GETS, desc="A Merged GetS from another processor";
122 Other_GETS_No_Mig, desc="A GetS from another processor";
123 NC_DMA_GETS, desc="special GetS when only DMA exists";
124 Invalidate, desc="Invalidate block";
127 Ack, desc="Received an ack message";
128 Shared_Ack, desc="Received an ack message, responder has a shared copy";
129 Data, desc="Received a data message";
130 Shared_Data, desc="Received a data message, responder has a shared copy";
131 Exclusive_Data, desc="Received a data message, responder had an exclusive copy, they gave it to us";
133 Writeback_Ack, desc="Writeback O.K. from directory";
134 Writeback_Nack, desc="Writeback not O.K. from directory";
137 All_acks, desc="Received all required data and message acks";
138 All_acks_no_sharers, desc="Received all acks and no other processor has a shared copy";
141 Flush_line, desc="flush the cache line from all caches";
142 Block_Ack, desc="the directory is blocked and ready for the flush";
145 // STRUCTURE DEFINITIONS
147 structure(Entry, desc="...", interface="AbstractCacheEntry") {
148 State CacheState, desc="cache state";
149 bool Dirty, desc="Is the data dirty (different than memory)?";
150 DataBlock DataBlk, desc="data for the block";
151 bool FromL2, default="false", desc="block just moved from L2";
152 bool AtomicAccessed, default="false", desc="block just moved from L2";
156 structure(TBE, desc="...") {
157 State TBEState, desc="Transient state";
158 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
159 bool Dirty, desc="Is the data dirty (different than memory)?";
160 int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for";
161 bool Sharers, desc="On a GetS, did we find any other sharers in the system";
162 bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks";
163 MachineID LastResponder, desc="last machine to send a response for this request";
164 MachineID CurOwner, desc="current owner of the block, used for UnblockS responses";
166 Cycles InitialRequestTime, default="Cycles(0)",
167 desc="time the initial requests was sent from the L1Cache";
168 Cycles ForwardRequestTime, default="Cycles(0)",
169 desc="time the dir forwarded the request";
170 Cycles FirstResponseTime, default="Cycles(0)",
171 desc="the time the first response was received";
174 structure(TBETable, external="yes") {
177 void deallocate(Addr);
178 bool isPresent(Addr);
181 TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
184 void set_cache_entry(AbstractCacheEntry b);
185 void unset_cache_entry();
188 void wakeUpAllBuffers();
189 void wakeUpBuffers(Addr a);
191 MachineID mapAddressToMachine(Addr addr, MachineType mtype);
193 Entry getCacheEntry(Addr address), return_by_pointer="yes" {
194 Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
195 if(is_valid(L2cache_entry)) {
196 return L2cache_entry;
199 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address));
200 if(is_valid(L1Dcache_entry)) {
201 return L1Dcache_entry;
204 Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address));
205 return L1Icache_entry;
208 void functionalRead(Addr addr, Packet *pkt) {
209 Entry cache_entry := getCacheEntry(addr);
210 if(is_valid(cache_entry)) {
211 testAndRead(addr, cache_entry.DataBlk, pkt);
213 TBE tbe := TBEs[addr];
215 testAndRead(addr, tbe.DataBlk, pkt);
217 error("Missing data block");
222 int functionalWrite(Addr addr, Packet *pkt) {
223 int num_functional_writes := 0;
225 Entry cache_entry := getCacheEntry(addr);
226 if(is_valid(cache_entry)) {
227 num_functional_writes := num_functional_writes +
228 testAndWrite(addr, cache_entry.DataBlk, pkt);
229 return num_functional_writes;
232 TBE tbe := TBEs[addr];
233 num_functional_writes := num_functional_writes +
234 testAndWrite(addr, tbe.DataBlk, pkt);
235 return num_functional_writes;
238 Entry getL2CacheEntry(Addr address), return_by_pointer="yes" {
239 Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
240 return L2cache_entry;
243 Entry getL1DCacheEntry(Addr address), return_by_pointer="yes" {
244 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address));
245 return L1Dcache_entry;
248 Entry getL1ICacheEntry(Addr address), return_by_pointer="yes" {
249 Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address));
250 return L1Icache_entry;
253 State getState(TBE tbe, Entry cache_entry, Addr addr) {
256 } else if (is_valid(cache_entry)) {
257 return cache_entry.CacheState;
262 void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
263 assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
264 assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
265 assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
268 tbe.TBEState := state;
271 if (is_valid(cache_entry)) {
272 cache_entry.CacheState := state;
276 AccessPermission getAccessPermission(Addr addr) {
277 TBE tbe := TBEs[addr];
279 return L1Cache_State_to_permission(tbe.TBEState);
282 Entry cache_entry := getCacheEntry(addr);
283 if(is_valid(cache_entry)) {
284 return L1Cache_State_to_permission(cache_entry.CacheState);
287 return AccessPermission:NotPresent;
290 void setAccessPermission(Entry cache_entry, Addr addr, State state) {
291 if (is_valid(cache_entry)) {
292 cache_entry.changePermission(L1Cache_State_to_permission(state));
296 Event mandatory_request_type_to_event(RubyRequestType type) {
297 if (type == RubyRequestType:LD) {
299 } else if (type == RubyRequestType:IFETCH) {
301 } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
303 } else if ((type == RubyRequestType:FLUSH)) {
304 return Event:Flush_line;
306 error("Invalid RubyRequestType");
310 MachineType testAndClearLocalHit(Entry cache_entry) {
311 if (is_valid(cache_entry) && cache_entry.FromL2) {
312 cache_entry.FromL2 := false;
313 return MachineType:L2Cache;
315 return MachineType:L1Cache;
318 bool IsAtomicAccessed(Entry cache_entry) {
319 assert(is_valid(cache_entry));
320 return cache_entry.AtomicAccessed;
324 out_port(requestNetwork_out, RequestMsg, requestFromCache);
325 out_port(responseNetwork_out, ResponseMsg, responseFromCache);
326 out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
327 out_port(triggerQueue_out, TriggerMsg, triggerQueue);
332 in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
333 if (triggerQueue_in.isReady(clockEdge())) {
334 peek(triggerQueue_in, TriggerMsg) {
336 Entry cache_entry := getCacheEntry(in_msg.addr);
337 TBE tbe := TBEs[in_msg.addr];
339 if (in_msg.Type == TriggerType:L2_to_L1) {
340 trigger(Event:Complete_L2_to_L1, in_msg.addr, cache_entry, tbe);
341 } else if (in_msg.Type == TriggerType:ALL_ACKS) {
342 trigger(Event:All_acks, in_msg.addr, cache_entry, tbe);
343 } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
344 trigger(Event:All_acks_no_sharers, in_msg.addr, cache_entry, tbe);
346 error("Unexpected message");
352 // Nothing from the unblock network
355 in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
356 if (responseToCache_in.isReady(clockEdge())) {
357 peek(responseToCache_in, ResponseMsg, block_on="addr") {
359 Entry cache_entry := getCacheEntry(in_msg.addr);
360 TBE tbe := TBEs[in_msg.addr];
362 if (in_msg.Type == CoherenceResponseType:ACK) {
363 trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
364 } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
365 trigger(Event:Shared_Ack, in_msg.addr, cache_entry, tbe);
366 } else if (in_msg.Type == CoherenceResponseType:DATA) {
367 trigger(Event:Data, in_msg.addr, cache_entry, tbe);
368 } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
369 trigger(Event:Shared_Data, in_msg.addr, cache_entry, tbe);
370 } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
371 trigger(Event:Exclusive_Data, in_msg.addr, cache_entry, tbe);
373 error("Unexpected message");
380 in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
381 if (forwardToCache_in.isReady(clockEdge())) {
382 peek(forwardToCache_in, RequestMsg, block_on="addr") {
384 Entry cache_entry := getCacheEntry(in_msg.addr);
385 TBE tbe := TBEs[in_msg.addr];
387 if ((in_msg.Type == CoherenceRequestType:GETX) ||
388 (in_msg.Type == CoherenceRequestType:GETF)) {
389 trigger(Event:Other_GETX, in_msg.addr, cache_entry, tbe);
390 } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
391 trigger(Event:Merged_GETS, in_msg.addr, cache_entry, tbe);
392 } else if (in_msg.Type == CoherenceRequestType:GETS) {
393 if (machineCount(MachineType:L1Cache) > 1) {
394 if (is_valid(cache_entry)) {
395 if (IsAtomicAccessed(cache_entry) && no_mig_atomic) {
396 trigger(Event:Other_GETS_No_Mig, in_msg.addr, cache_entry, tbe);
398 trigger(Event:Other_GETS, in_msg.addr, cache_entry, tbe);
401 trigger(Event:Other_GETS, in_msg.addr, cache_entry, tbe);
404 trigger(Event:NC_DMA_GETS, in_msg.addr, cache_entry, tbe);
406 } else if (in_msg.Type == CoherenceRequestType:INV) {
407 trigger(Event:Invalidate, in_msg.addr, cache_entry, tbe);
408 } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
409 trigger(Event:Writeback_Ack, in_msg.addr, cache_entry, tbe);
410 } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
411 trigger(Event:Writeback_Nack, in_msg.addr, cache_entry, tbe);
412 } else if (in_msg.Type == CoherenceRequestType:BLOCK_ACK) {
413 trigger(Event:Block_Ack, in_msg.addr, cache_entry, tbe);
415 error("Unexpected message");
421 // Nothing from the request network
424 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
425 if (mandatoryQueue_in.isReady(clockEdge())) {
426 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
428 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
429 TBE tbe := TBEs[in_msg.LineAddress];
431 if (in_msg.Type == RubyRequestType:IFETCH) {
432 // ** INSTRUCTION ACCESS ***
434 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
435 if (is_valid(L1Icache_entry)) {
436 // The tag matches for the L1, so the L1 fetches the line.
437 // We know it can't be in the L2 due to exclusion
438 trigger(mandatory_request_type_to_event(in_msg.Type),
439 in_msg.LineAddress, L1Icache_entry, tbe);
441 // Check to see if it is in the OTHER L1
442 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
443 if (is_valid(L1Dcache_entry)) {
444 // The block is in the wrong L1, try to write it to the L2
445 if (L2cache.cacheAvail(in_msg.LineAddress)) {
446 trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
448 Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
449 trigger(Event:L2_Replacement,
451 getL2CacheEntry(l2_victim_addr),
452 TBEs[l2_victim_addr]);
456 if (L1Icache.cacheAvail(in_msg.LineAddress)) {
457 // L1 does't have the line, but we have space for it in the L1
459 Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
460 if (is_valid(L2cache_entry)) {
461 // L2 has it (maybe not with the right permissions)
462 trigger(Event:Trigger_L2_to_L1I, in_msg.LineAddress,
465 // We have room, the L2 doesn't have it, so the L1 fetches the line
466 trigger(mandatory_request_type_to_event(in_msg.Type),
467 in_msg.LineAddress, L1Icache_entry, tbe);
470 // No room in the L1, so we need to make room
471 Addr l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress);
472 if (L2cache.cacheAvail(l1i_victim_addr)) {
473 // The L2 has room, so we move the line from the L1 to the L2
474 trigger(Event:L1_to_L2,
476 getL1ICacheEntry(l1i_victim_addr),
477 TBEs[l1i_victim_addr]);
479 Addr l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
480 // The L2 does not have room, so we replace a line from the L2
481 trigger(Event:L2_Replacement,
483 getL2CacheEntry(l2_victim_addr),
484 TBEs[l2_victim_addr]);
489 // *** DATA ACCESS ***
491 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
492 if (is_valid(L1Dcache_entry)) {
493 // The tag matches for the L1, so the L1 fetches the line.
494 // We know it can't be in the L2 due to exclusion
495 trigger(mandatory_request_type_to_event(in_msg.Type),
496 in_msg.LineAddress, L1Dcache_entry, tbe);
499 // Check to see if it is in the OTHER L1
500 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
501 if (is_valid(L1Icache_entry)) {
502 // The block is in the wrong L1, try to write it to the L2
503 if (L2cache.cacheAvail(in_msg.LineAddress)) {
504 trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
506 Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
507 trigger(Event:L2_Replacement,
509 getL2CacheEntry(l2_victim_addr),
510 TBEs[l2_victim_addr]);
514 if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
515 // L1 does't have the line, but we have space for it in the L1
516 Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
517 if (is_valid(L2cache_entry)) {
518 // L2 has it (maybe not with the right permissions)
519 trigger(Event:Trigger_L2_to_L1D, in_msg.LineAddress,
522 // We have room, the L2 doesn't have it, so the L1 fetches the line
523 trigger(mandatory_request_type_to_event(in_msg.Type),
524 in_msg.LineAddress, L1Dcache_entry, tbe);
527 // No room in the L1, so we need to make room
528 Addr l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress);
529 if (L2cache.cacheAvail(l1d_victim_addr)) {
530 // The L2 has room, so we move the line from the L1 to the L2
531 trigger(Event:L1_to_L2,
533 getL1DCacheEntry(l1d_victim_addr),
534 TBEs[l1d_victim_addr]);
536 Addr l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
537 // The L2 does not have room, so we replace a line from the L2
538 trigger(Event:L2_Replacement,
540 getL2CacheEntry(l2_victim_addr),
541 TBEs[l2_victim_addr]);
552 action(a_issueGETS, "a", desc="Issue GETS") {
553 enqueue(requestNetwork_out, RequestMsg, issue_latency) {
554 assert(is_valid(tbe));
555 out_msg.addr := address;
556 out_msg.Type := CoherenceRequestType:GETS;
557 out_msg.Requestor := machineID;
558 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
559 out_msg.MessageSize := MessageSizeType:Request_Control;
560 out_msg.InitialRequestTime := curCycle();
562 // One from each other cache (n-1) plus the memory (+1)
563 tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
567 action(b_issueGETX, "b", desc="Issue GETX") {
568 enqueue(requestNetwork_out, RequestMsg, issue_latency) {
569 assert(is_valid(tbe));
570 out_msg.addr := address;
571 out_msg.Type := CoherenceRequestType:GETX;
572 out_msg.Requestor := machineID;
573 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
574 out_msg.MessageSize := MessageSizeType:Request_Control;
575 out_msg.InitialRequestTime := curCycle();
577 // One from each other cache (n-1) plus the memory (+1)
578 tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
582 action(b_issueGETXIfMoreThanOne, "bo", desc="Issue GETX") {
583 if (machineCount(MachineType:L1Cache) > 1) {
584 enqueue(requestNetwork_out, RequestMsg, issue_latency) {
585 assert(is_valid(tbe));
586 out_msg.addr := address;
587 out_msg.Type := CoherenceRequestType:GETX;
588 out_msg.Requestor := machineID;
589 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
590 out_msg.MessageSize := MessageSizeType:Request_Control;
591 out_msg.InitialRequestTime := curCycle();
595 // One from each other cache (n-1) plus the memory (+1)
596 tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
599 action(bf_issueGETF, "bf", desc="Issue GETF") {
600 enqueue(requestNetwork_out, RequestMsg, issue_latency) {
601 assert(is_valid(tbe));
602 out_msg.addr := address;
603 out_msg.Type := CoherenceRequestType:GETF;
604 out_msg.Requestor := machineID;
605 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
606 out_msg.MessageSize := MessageSizeType:Request_Control;
607 out_msg.InitialRequestTime := curCycle();
609 // One from each other cache (n-1) plus the memory (+1)
610 tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
614 action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") {
615 peek(forwardToCache_in, RequestMsg) {
616 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
617 assert(is_valid(cache_entry));
618 out_msg.addr := address;
619 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
620 out_msg.Sender := machineID;
621 out_msg.Destination.add(in_msg.Requestor);
622 out_msg.DataBlk := cache_entry.DataBlk;
623 out_msg.Dirty := cache_entry.Dirty;
624 if (in_msg.DirectedProbe) {
625 out_msg.Acks := machineCount(MachineType:L1Cache);
629 out_msg.SilentAcks := in_msg.SilentAcks;
630 out_msg.MessageSize := MessageSizeType:Response_Data;
631 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
632 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
637 action(ct_sendExclusiveDataFromTBE, "ct", desc="Send exclusive data from tbe to requestor") {
638 peek(forwardToCache_in, RequestMsg) {
639 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
640 assert(is_valid(tbe));
641 out_msg.addr := address;
642 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
643 out_msg.Sender := machineID;
644 out_msg.Destination.add(in_msg.Requestor);
645 out_msg.DataBlk := tbe.DataBlk;
646 out_msg.Dirty := tbe.Dirty;
647 if (in_msg.DirectedProbe) {
648 out_msg.Acks := machineCount(MachineType:L1Cache);
652 out_msg.SilentAcks := in_msg.SilentAcks;
653 out_msg.MessageSize := MessageSizeType:Response_Data;
654 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
655 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
660 action(d_issuePUT, "d", desc="Issue PUT") {
661 enqueue(requestNetwork_out, RequestMsg, issue_latency) {
662 out_msg.addr := address;
663 out_msg.Type := CoherenceRequestType:PUT;
664 out_msg.Requestor := machineID;
665 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
666 out_msg.MessageSize := MessageSizeType:Writeback_Control;
670 action(df_issuePUTF, "df", desc="Issue PUTF") {
671 enqueue(requestNetwork_out, RequestMsg, issue_latency) {
672 out_msg.addr := address;
673 out_msg.Type := CoherenceRequestType:PUTF;
674 out_msg.Requestor := machineID;
675 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
676 out_msg.MessageSize := MessageSizeType:Writeback_Control;
680 action(e_sendData, "e", desc="Send data from cache to requestor") {
681 peek(forwardToCache_in, RequestMsg) {
682 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
683 assert(is_valid(cache_entry));
684 out_msg.addr := address;
685 out_msg.Type := CoherenceResponseType:DATA;
686 out_msg.Sender := machineID;
687 out_msg.Destination.add(in_msg.Requestor);
688 out_msg.DataBlk := cache_entry.DataBlk;
689 out_msg.Dirty := cache_entry.Dirty;
690 if (in_msg.DirectedProbe) {
691 out_msg.Acks := machineCount(MachineType:L1Cache);
695 out_msg.SilentAcks := in_msg.SilentAcks;
696 out_msg.MessageSize := MessageSizeType:Response_Data;
697 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
698 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
703 action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, remaining the owner") {
704 peek(forwardToCache_in, RequestMsg) {
705 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
706 assert(is_valid(cache_entry));
707 out_msg.addr := address;
708 out_msg.Type := CoherenceResponseType:DATA_SHARED;
709 out_msg.Sender := machineID;
710 out_msg.Destination.add(in_msg.Requestor);
711 out_msg.DataBlk := cache_entry.DataBlk;
712 out_msg.Dirty := cache_entry.Dirty;
713 DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
714 if (in_msg.DirectedProbe) {
715 out_msg.Acks := machineCount(MachineType:L1Cache);
719 out_msg.SilentAcks := in_msg.SilentAcks;
720 out_msg.MessageSize := MessageSizeType:Response_Data;
721 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
722 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
727 action(et_sendDataSharedFromTBE, "\et", desc="Send data from TBE to requestor, keep a shared copy") {
728 peek(forwardToCache_in, RequestMsg) {
729 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
730 assert(is_valid(tbe));
731 out_msg.addr := address;
732 out_msg.Type := CoherenceResponseType:DATA_SHARED;
733 out_msg.Sender := machineID;
734 out_msg.Destination.add(in_msg.Requestor);
735 out_msg.DataBlk := tbe.DataBlk;
736 out_msg.Dirty := tbe.Dirty;
737 DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
738 if (in_msg.DirectedProbe) {
739 out_msg.Acks := machineCount(MachineType:L1Cache);
743 out_msg.SilentAcks := in_msg.SilentAcks;
744 out_msg.MessageSize := MessageSizeType:Response_Data;
745 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
746 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
751 action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors, still the owner") {
752 peek(forwardToCache_in, RequestMsg) {
753 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
754 assert(is_valid(cache_entry));
755 out_msg.addr := address;
756 out_msg.Type := CoherenceResponseType:DATA_SHARED;
757 out_msg.Sender := machineID;
758 out_msg.Destination := in_msg.MergedRequestors;
759 out_msg.DataBlk := cache_entry.DataBlk;
760 out_msg.Dirty := cache_entry.Dirty;
761 DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
762 out_msg.Acks := machineCount(MachineType:L1Cache);
763 out_msg.SilentAcks := in_msg.SilentAcks;
764 out_msg.MessageSize := MessageSizeType:Response_Data;
765 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
766 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
771 action(emt_sendDataSharedMultipleFromTBE, "emt", desc="Send data from tbe to all requestors") {
772 peek(forwardToCache_in, RequestMsg) {
773 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
774 assert(is_valid(tbe));
775 out_msg.addr := address;
776 out_msg.Type := CoherenceResponseType:DATA_SHARED;
777 out_msg.Sender := machineID;
778 out_msg.Destination := in_msg.MergedRequestors;
779 out_msg.DataBlk := tbe.DataBlk;
780 out_msg.Dirty := tbe.Dirty;
781 DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
782 out_msg.Acks := machineCount(MachineType:L1Cache);
783 out_msg.SilentAcks := in_msg.SilentAcks;
784 out_msg.MessageSize := MessageSizeType:Response_Data;
785 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
786 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
791 action(f_sendAck, "f", desc="Send ack from cache to requestor") {
792 peek(forwardToCache_in, RequestMsg) {
793 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
794 out_msg.addr := address;
795 out_msg.Type := CoherenceResponseType:ACK;
796 out_msg.Sender := machineID;
797 out_msg.Destination.add(in_msg.Requestor);
799 out_msg.SilentAcks := in_msg.SilentAcks;
800 assert(in_msg.DirectedProbe == false);
801 out_msg.MessageSize := MessageSizeType:Response_Control;
802 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
803 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
808 action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") {
809 peek(forwardToCache_in, RequestMsg) {
810 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
811 out_msg.addr := address;
812 out_msg.Type := CoherenceResponseType:ACK_SHARED;
813 out_msg.Sender := machineID;
814 out_msg.Destination.add(in_msg.Requestor);
816 out_msg.SilentAcks := in_msg.SilentAcks;
817 assert(in_msg.DirectedProbe == false);
818 out_msg.MessageSize := MessageSizeType:Response_Control;
819 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
820 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
825 action(g_sendUnblock, "g", desc="Send unblock to memory") {
826 enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
827 out_msg.addr := address;
828 out_msg.Type := CoherenceResponseType:UNBLOCK;
829 out_msg.Sender := machineID;
830 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
831 out_msg.MessageSize := MessageSizeType:Unblock_Control;
835 action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") {
836 enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
837 out_msg.addr := address;
838 out_msg.Type := CoherenceResponseType:UNBLOCKM;
839 out_msg.Sender := machineID;
840 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
841 out_msg.MessageSize := MessageSizeType:Unblock_Control;
845 action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") {
846 enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
847 assert(is_valid(tbe));
848 out_msg.addr := address;
849 out_msg.Type := CoherenceResponseType:UNBLOCKS;
850 out_msg.Sender := machineID;
851 out_msg.CurOwner := tbe.CurOwner;
852 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
853 out_msg.MessageSize := MessageSizeType:Unblock_Control;
857 action(h_load_hit, "hd", desc="Notify sequencer the load completed.") {
858 assert(is_valid(cache_entry));
859 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
860 L1Dcache.setMRU(cache_entry);
861 sequencer.readCallback(address, cache_entry.DataBlk, false,
862 testAndClearLocalHit(cache_entry));
865 action(h_ifetch_hit, "hi", desc="Notify sequencer the ifetch completed.") {
866 assert(is_valid(cache_entry));
867 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
868 L1Icache.setMRU(cache_entry);
869 sequencer.readCallback(address, cache_entry.DataBlk, false,
870 testAndClearLocalHit(cache_entry));
873 action(hx_external_load_hit, "hx", desc="load required external msgs") {
874 assert(is_valid(cache_entry));
875 assert(is_valid(tbe));
876 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
877 peek(responseToCache_in, ResponseMsg) {
878 L1Icache.setMRU(address);
879 L1Dcache.setMRU(address);
880 sequencer.readCallback(address, cache_entry.DataBlk, true,
881 machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
882 tbe.ForwardRequestTime, tbe.FirstResponseTime);
886 action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
887 assert(is_valid(cache_entry));
888 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
889 peek(mandatoryQueue_in, RubyRequest) {
890 L1Dcache.setMRU(cache_entry);
891 sequencer.writeCallback(address, cache_entry.DataBlk, false,
892 testAndClearLocalHit(cache_entry));
894 cache_entry.Dirty := true;
895 if (in_msg.Type == RubyRequestType:ATOMIC) {
896 cache_entry.AtomicAccessed := true;
901 action(hh_flush_hit, "\hf", desc="Notify sequencer that flush completed.") {
902 assert(is_valid(tbe));
903 DPRINTF(RubySlicc, "%s\n", tbe.DataBlk);
904 sequencer.writeCallback(address, tbe.DataBlk, false, MachineType:L1Cache);
907 action(sx_external_store_hit, "sx", desc="store required external msgs.") {
908 assert(is_valid(cache_entry));
909 assert(is_valid(tbe));
910 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
911 peek(responseToCache_in, ResponseMsg) {
912 L1Icache.setMRU(address);
913 L1Dcache.setMRU(address);
914 sequencer.writeCallback(address, cache_entry.DataBlk, true,
915 machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
916 tbe.ForwardRequestTime, tbe.FirstResponseTime);
918 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
919 cache_entry.Dirty := true;
922 action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
923 assert(is_valid(cache_entry));
924 assert(is_valid(tbe));
925 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
926 L1Icache.setMRU(address);
927 L1Dcache.setMRU(address);
928 sequencer.writeCallback(address, cache_entry.DataBlk, true,
929 machineIDToMachineType(tbe.LastResponder), tbe.InitialRequestTime,
930 tbe.ForwardRequestTime, tbe.FirstResponseTime);
932 cache_entry.Dirty := true;
935 action(i_allocateTBE, "i", desc="Allocate TBE") {
936 check_allocate(TBEs);
937 assert(is_valid(cache_entry));
938 TBEs.allocate(address);
939 set_tbe(TBEs[address]);
940 tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
941 tbe.Dirty := cache_entry.Dirty;
942 tbe.Sharers := false;
945 action(it_allocateTBE, "it", desc="Allocate TBE") {
946 check_allocate(TBEs);
947 TBEs.allocate(address);
948 set_tbe(TBEs[address]);
950 tbe.Sharers := false;
953 action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
954 triggerQueue_in.dequeue(clockEdge());
957 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
958 mandatoryQueue_in.dequeue(clockEdge());
961 action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
962 forwardToCache_in.dequeue(clockEdge());
965 action(hp_copyFromTBEToL2, "li", desc="Copy data from TBE to L2 cache entry.") {
966 assert(is_valid(cache_entry));
967 assert(is_valid(tbe));
968 cache_entry.Dirty := tbe.Dirty;
969 cache_entry.DataBlk := tbe.DataBlk;
972 action(nb_copyFromTBEToL1, "fu", desc="Copy data from TBE to L1 cache entry.") {
973 assert(is_valid(cache_entry));
974 assert(is_valid(tbe));
975 cache_entry.Dirty := tbe.Dirty;
976 cache_entry.DataBlk := tbe.DataBlk;
977 cache_entry.FromL2 := true;
980 action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
981 peek(responseToCache_in, ResponseMsg) {
982 assert(in_msg.Acks >= 0);
983 assert(is_valid(tbe));
984 DPRINTF(RubySlicc, "Sender = %s\n", in_msg.Sender);
985 DPRINTF(RubySlicc, "SilentAcks = %d\n", in_msg.SilentAcks);
986 if (tbe.AppliedSilentAcks == false) {
987 tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.SilentAcks;
988 tbe.AppliedSilentAcks := true;
990 DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
991 tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
992 DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
993 APPEND_TRANSITION_COMMENT(tbe.NumPendingMsgs);
994 APPEND_TRANSITION_COMMENT(in_msg.Sender);
995 tbe.LastResponder := in_msg.Sender;
996 if (tbe.InitialRequestTime != zero_time() && in_msg.InitialRequestTime != zero_time()) {
997 assert(tbe.InitialRequestTime == in_msg.InitialRequestTime);
999 if (in_msg.InitialRequestTime != zero_time()) {
1000 tbe.InitialRequestTime := in_msg.InitialRequestTime;
1002 if (tbe.ForwardRequestTime != zero_time() && in_msg.ForwardRequestTime != zero_time()) {
1003 assert(tbe.ForwardRequestTime == in_msg.ForwardRequestTime);
1005 if (in_msg.ForwardRequestTime != zero_time()) {
1006 tbe.ForwardRequestTime := in_msg.ForwardRequestTime;
1008 if (tbe.FirstResponseTime == zero_time()) {
1009 tbe.FirstResponseTime := curCycle();
1013 action(uo_updateCurrentOwner, "uo", desc="When moving SS state, update current owner.") {
1014 peek(responseToCache_in, ResponseMsg) {
1015 assert(is_valid(tbe));
1016 tbe.CurOwner := in_msg.Sender;
1020 action(n_popResponseQueue, "n", desc="Pop response queue") {
1021 responseToCache_in.dequeue(clockEdge());
1024 action(ll_L2toL1Transfer, "ll", desc="") {
1025 enqueue(triggerQueue_out, TriggerMsg, l2_cache_hit_latency) {
1026 out_msg.addr := address;
1027 out_msg.Type := TriggerType:L2_to_L1;
1031 action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
1032 assert(is_valid(tbe));
1033 if (tbe.NumPendingMsgs == 0) {
1034 enqueue(triggerQueue_out, TriggerMsg) {
1035 out_msg.addr := address;
1037 out_msg.Type := TriggerType:ALL_ACKS;
1039 out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
1045 action(p_decrementNumberOfMessagesByOne, "p", desc="Decrement the number of messages for which we're waiting by one") {
1046 assert(is_valid(tbe));
1047 tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
1050 action(pp_incrementNumberOfMessagesByOne, "\p", desc="Increment the number of messages for which we're waiting by one") {
1051 assert(is_valid(tbe));
1052 tbe.NumPendingMsgs := tbe.NumPendingMsgs + 1;
1055 action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
1056 peek(forwardToCache_in, RequestMsg) {
1057 assert(in_msg.Requestor != machineID);
1058 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
1059 assert(is_valid(tbe));
1060 out_msg.addr := address;
1061 out_msg.Type := CoherenceResponseType:DATA;
1062 out_msg.Sender := machineID;
1063 out_msg.Destination.add(in_msg.Requestor);
1064 DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
1065 out_msg.DataBlk := tbe.DataBlk;
1066 out_msg.Dirty := tbe.Dirty;
1067 if (in_msg.DirectedProbe) {
1068 out_msg.Acks := machineCount(MachineType:L1Cache);
1072 out_msg.SilentAcks := in_msg.SilentAcks;
1073 out_msg.MessageSize := MessageSizeType:Response_Data;
1074 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
1075 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
1080 action(sq_sendSharedDataFromTBEToCache, "sq", desc="Send shared data from TBE to cache, still the owner") {
1081 peek(forwardToCache_in, RequestMsg) {
1082 assert(in_msg.Requestor != machineID);
1083 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
1084 assert(is_valid(tbe));
1085 out_msg.addr := address;
1086 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1087 out_msg.Sender := machineID;
1088 out_msg.Destination.add(in_msg.Requestor);
1089 DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
1090 out_msg.DataBlk := tbe.DataBlk;
1091 out_msg.Dirty := tbe.Dirty;
1092 if (in_msg.DirectedProbe) {
1093 out_msg.Acks := machineCount(MachineType:L1Cache);
1097 out_msg.SilentAcks := in_msg.SilentAcks;
1098 out_msg.MessageSize := MessageSizeType:Response_Data;
1099 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
1100 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
1105 action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, multiple sharers, still the owner") {
1106 peek(forwardToCache_in, RequestMsg) {
1107 enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
1108 assert(is_valid(tbe));
1109 out_msg.addr := address;
1110 out_msg.Type := CoherenceResponseType:DATA_SHARED;
1111 out_msg.Sender := machineID;
1112 out_msg.Destination := in_msg.MergedRequestors;
1113 DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
1114 out_msg.DataBlk := tbe.DataBlk;
1115 out_msg.Dirty := tbe.Dirty;
1116 out_msg.Acks := machineCount(MachineType:L1Cache);
1117 out_msg.SilentAcks := in_msg.SilentAcks;
1118 out_msg.MessageSize := MessageSizeType:Response_Data;
1119 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
1120 out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
1125 action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
1126 enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
1127 assert(is_valid(tbe));
1128 out_msg.addr := address;
1129 out_msg.Sender := machineID;
1130 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1131 out_msg.Dirty := tbe.Dirty;
1133 out_msg.Type := CoherenceResponseType:WB_DIRTY;
1134 out_msg.DataBlk := tbe.DataBlk;
1135 out_msg.MessageSize := MessageSizeType:Writeback_Data;
1137 out_msg.Type := CoherenceResponseType:WB_CLEAN;
1138 // NOTE: in a real system this would not send data. We send
1139 // data here only so we can check it at the memory
1140 out_msg.DataBlk := tbe.DataBlk;
1141 out_msg.MessageSize := MessageSizeType:Writeback_Control;
1146 action(r_setSharerBit, "r", desc="We saw other sharers") {
1147 assert(is_valid(tbe));
1148 tbe.Sharers := true;
1151 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1152 TBEs.deallocate(address);
1156 action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") {
1157 enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
1158 assert(is_valid(tbe));
1159 out_msg.addr := address;
1160 out_msg.Sender := machineID;
1161 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1162 out_msg.DataBlk := tbe.DataBlk;
1163 out_msg.Dirty := tbe.Dirty;
1165 out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_DIRTY;
1166 out_msg.DataBlk := tbe.DataBlk;
1167 out_msg.MessageSize := MessageSizeType:Writeback_Data;
1169 out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_CLEAN;
1170 // NOTE: in a real system this would not send data. We send
1171 // data here only so we can check it at the memory
1172 out_msg.DataBlk := tbe.DataBlk;
1173 out_msg.MessageSize := MessageSizeType:Writeback_Control;
1178 action(u_writeDataToCache, "u", desc="Write data to cache") {
1179 peek(responseToCache_in, ResponseMsg) {
1180 assert(is_valid(cache_entry));
1181 cache_entry.DataBlk := in_msg.DataBlk;
1182 cache_entry.Dirty := in_msg.Dirty;
1186 action(uf_writeDataToCacheTBE, "uf", desc="Write data to TBE") {
1187 peek(responseToCache_in, ResponseMsg) {
1188 assert(is_valid(tbe));
1189 tbe.DataBlk := in_msg.DataBlk;
1190 tbe.Dirty := in_msg.Dirty;
1194 action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
1195 peek(responseToCache_in, ResponseMsg) {
1196 assert(is_valid(cache_entry));
1197 DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
1198 cache_entry.DataBlk, in_msg.DataBlk);
1199 assert(cache_entry.DataBlk == in_msg.DataBlk);
1200 cache_entry.DataBlk := in_msg.DataBlk;
1201 cache_entry.Dirty := in_msg.Dirty || cache_entry.Dirty;
1205 action(vt_writeDataToTBEVerify, "vt", desc="Write data to TBE, assert it was same as before") {
1206 peek(responseToCache_in, ResponseMsg) {
1207 assert(is_valid(tbe));
1208 DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
1209 tbe.DataBlk, in_msg.DataBlk);
1210 assert(tbe.DataBlk == in_msg.DataBlk);
1211 tbe.DataBlk := in_msg.DataBlk;
1212 tbe.Dirty := in_msg.Dirty || tbe.Dirty;
1216 action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1217 if (L1Dcache.isTagPresent(address)) {
1218 L1Dcache.deallocate(address);
1220 L1Icache.deallocate(address);
1222 unset_cache_entry();
1225 action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1226 if (is_invalid(cache_entry)) {
1227 set_cache_entry(L1Dcache.allocate(address, new Entry));
1231 action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
1232 if (is_invalid(cache_entry)) {
1233 set_cache_entry(L1Icache.allocate(address, new Entry));
1237 action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
1238 set_cache_entry(L2cache.allocate(address, new Entry));
1241 action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
1242 L2cache.deallocate(address);
1243 unset_cache_entry();
1246 action(gr_deallocateCacheBlock, "\gr", desc="Deallocate an L1 or L2 cache block.") {
1247 if (L1Dcache.isTagPresent(address)) {
1248 L1Dcache.deallocate(address);
1250 else if (L1Icache.isTagPresent(address)){
1251 L1Icache.deallocate(address);
1254 assert(L2cache.isTagPresent(address));
1255 L2cache.deallocate(address);
1257 unset_cache_entry();
1260 action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
1261 if (send_evictions) {
1262 DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
1263 sequencer.evictionCallback(address);
1267 action(uu_profileL1DataMiss, "\udm", desc="Profile the demand miss") {
1268 ++L1Dcache.demand_misses;
1271 action(uu_profileL1DataHit, "\udh", desc="Profile the demand hits") {
1272 ++L1Dcache.demand_hits;
1275 action(uu_profileL1InstMiss, "\uim", desc="Profile the demand miss") {
1276 ++L1Icache.demand_misses;
1279 action(uu_profileL1InstHit, "\uih", desc="Profile the demand hits") {
1280 ++L1Icache.demand_hits;
1283 action(uu_profileL2Miss, "\um", desc="Profile the demand miss") {
1284 ++L2cache.demand_misses;
1287 action(uu_profileL2Hit, "\uh", desc="Profile the demand hits ") {
1288 ++L2cache.demand_hits;
1291 action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1292 stall_and_wait(mandatoryQueue_in, address);
1295 action(z_stall, "z", desc="stall") {
1296 // do nothing and the special z_stall action will return a protocol stall
1297 // so that the next port is checked
1300 action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1301 wakeUpBuffers(address);
1304 action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1308 //*****************************************************
1310 //*****************************************************
1312 // Transitions for Load/Store/L2_Replacement from transient states
1313 transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II, ST, OT, MT, MMT}, {Store, L2_Replacement}) {
1314 zz_stallAndWaitMandatoryQueue;
1317 transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II}, {Flush_line}) {
1318 zz_stallAndWaitMandatoryQueue;
1321 transition({M_W, MM_W}, {L2_Replacement, Flush_line}) {
1322 zz_stallAndWaitMandatoryQueue;
1325 transition({IM, IS, OI, MI, II, ST, OT, MT, MMT, MI_F, MM_F, OM_F, IM_F, ISM_F, SM_F, MM_WF}, {Load, Ifetch}) {
1326 zz_stallAndWaitMandatoryQueue;
1329 transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F, IR, SR, OR, MR, MMR}, L1_to_L2) {
1330 zz_stallAndWaitMandatoryQueue;
1333 transition({MI_F, MM_F}, {Store}) {
1334 zz_stallAndWaitMandatoryQueue;
1337 transition({MM_F, MI_F}, {Flush_line}) {
1338 zz_stallAndWaitMandatoryQueue;
1341 transition({ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) {
1345 transition({IR, SR, OR, MR, MMR}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
1349 // Transitions moving data between the L1 and L2 caches
1350 transition({S, O, M, MM}, L1_to_L2) {
1352 gg_deallocateL1CacheBlock;
1353 vv_allocateL2CacheBlock;
1358 transition(S, Trigger_L2_to_L1D, ST) {
1360 rr_deallocateL2CacheBlock;
1361 ii_allocateL1DCacheBlock;
1364 zz_stallAndWaitMandatoryQueue;
1368 transition(O, Trigger_L2_to_L1D, OT) {
1370 rr_deallocateL2CacheBlock;
1371 ii_allocateL1DCacheBlock;
1374 zz_stallAndWaitMandatoryQueue;
1378 transition(M, Trigger_L2_to_L1D, MT) {
1380 rr_deallocateL2CacheBlock;
1381 ii_allocateL1DCacheBlock;
1384 zz_stallAndWaitMandatoryQueue;
1388 transition(MM, Trigger_L2_to_L1D, MMT) {
1390 rr_deallocateL2CacheBlock;
1391 ii_allocateL1DCacheBlock;
1394 zz_stallAndWaitMandatoryQueue;
1398 transition(S, Trigger_L2_to_L1I, ST) {
1400 rr_deallocateL2CacheBlock;
1401 jj_allocateL1ICacheBlock;
1404 zz_stallAndWaitMandatoryQueue;
1408 transition(O, Trigger_L2_to_L1I, OT) {
1410 rr_deallocateL2CacheBlock;
1411 jj_allocateL1ICacheBlock;
1414 zz_stallAndWaitMandatoryQueue;
1418 transition(M, Trigger_L2_to_L1I, MT) {
1420 rr_deallocateL2CacheBlock;
1421 jj_allocateL1ICacheBlock;
1424 zz_stallAndWaitMandatoryQueue;
1428 transition(MM, Trigger_L2_to_L1I, MMT) {
1430 rr_deallocateL2CacheBlock;
1431 jj_allocateL1ICacheBlock;
1434 zz_stallAndWaitMandatoryQueue;
1438 transition(ST, Complete_L2_to_L1, SR) {
1440 kd_wakeUpDependents;
1443 transition(OT, Complete_L2_to_L1, OR) {
1445 kd_wakeUpDependents;
1448 transition(MT, Complete_L2_to_L1, MR) {
1450 kd_wakeUpDependents;
1453 transition(MMT, Complete_L2_to_L1, MMR) {
1455 kd_wakeUpDependents;
1458 // Transitions from Idle
1459 transition({I,IR}, Load, IS) {
1460 ii_allocateL1DCacheBlock;
1463 uu_profileL1DataMiss;
1465 k_popMandatoryQueue;
1468 transition({I,IR}, Ifetch, IS) {
1469 jj_allocateL1ICacheBlock;
1472 uu_profileL1InstMiss;
1474 k_popMandatoryQueue;
1477 transition({I,IR}, Store, IM) {
1478 ii_allocateL1DCacheBlock;
1481 uu_profileL1DataMiss;
1483 k_popMandatoryQueue;
1486 transition({I, IR}, Flush_line, IM_F) {
1489 k_popMandatoryQueue;
1492 transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1497 // Transitions from Shared
1498 transition({S, SM, ISM}, Load) {
1500 uu_profileL1DataHit;
1501 k_popMandatoryQueue;
1504 transition({S, SM, ISM}, Ifetch) {
1506 uu_profileL1InstHit;
1507 k_popMandatoryQueue;
1510 transition(SR, Load, S) {
1512 uu_profileL1DataMiss;
1514 k_popMandatoryQueue;
1515 ka_wakeUpAllDependents;
1518 transition(SR, Ifetch, S) {
1520 uu_profileL1InstMiss;
1522 k_popMandatoryQueue;
1523 ka_wakeUpAllDependents;
1526 transition({S,SR}, Store, SM) {
1529 uu_profileL1DataMiss;
1531 k_popMandatoryQueue;
1534 transition({S, SR}, Flush_line, SM_F) {
1537 forward_eviction_to_cpu;
1538 gg_deallocateL1CacheBlock;
1539 k_popMandatoryQueue;
1542 transition(S, L2_Replacement, I) {
1543 forward_eviction_to_cpu;
1544 rr_deallocateL2CacheBlock;
1545 ka_wakeUpAllDependents;
1548 transition(S, {Other_GETX, Invalidate}, I) {
1550 forward_eviction_to_cpu;
1551 gr_deallocateCacheBlock;
1555 transition(S, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1560 // Transitions from Owned
1561 transition({O, OM, SS, MM_W, M_W}, {Load}) {
1563 uu_profileL1DataHit;
1564 k_popMandatoryQueue;
1567 transition({O, OM, SS, MM_W, M_W}, {Ifetch}) {
1569 uu_profileL1InstHit;
1570 k_popMandatoryQueue;
1573 transition(OR, Load, O) {
1575 uu_profileL1DataMiss;
1577 k_popMandatoryQueue;
1578 ka_wakeUpAllDependents;
1581 transition(OR, Ifetch, O) {
1583 uu_profileL1InstMiss;
1585 k_popMandatoryQueue;
1586 ka_wakeUpAllDependents;
1589 transition({O,OR}, Store, OM) {
1592 p_decrementNumberOfMessagesByOne;
1593 uu_profileL1DataMiss;
1595 k_popMandatoryQueue;
1598 transition({O, OR}, Flush_line, OM_F) {
1601 p_decrementNumberOfMessagesByOne;
1602 forward_eviction_to_cpu;
1603 gg_deallocateL1CacheBlock;
1604 k_popMandatoryQueue;
1607 transition(O, L2_Replacement, OI) {
1610 forward_eviction_to_cpu;
1611 rr_deallocateL2CacheBlock;
1612 ka_wakeUpAllDependents;
1615 transition(O, {Other_GETX, Invalidate}, I) {
1617 forward_eviction_to_cpu;
1618 gr_deallocateCacheBlock;
1622 transition(O, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1627 transition(O, Merged_GETS) {
1628 em_sendDataSharedMultiple;
1632 // Transitions from Modified
1633 transition({MM, M}, {Ifetch}) {
1635 uu_profileL1InstHit;
1636 k_popMandatoryQueue;
1639 transition({MM, M}, {Load}) {
1641 uu_profileL1DataHit;
1642 k_popMandatoryQueue;
1645 transition(MM, Store) {
1647 uu_profileL1DataHit;
1648 k_popMandatoryQueue;
1651 transition(MMR, Load, MM) {
1653 uu_profileL1DataMiss;
1655 k_popMandatoryQueue;
1656 ka_wakeUpAllDependents;
1659 transition(MMR, Ifetch, MM) {
1661 uu_profileL1InstMiss;
1663 k_popMandatoryQueue;
1664 ka_wakeUpAllDependents;
1667 transition(MMR, Store, MM) {
1669 uu_profileL1DataMiss;
1671 k_popMandatoryQueue;
1672 ka_wakeUpAllDependents;
1675 transition({MM, M, MMR, MR}, Flush_line, MM_F) {
1678 p_decrementNumberOfMessagesByOne;
1679 forward_eviction_to_cpu;
1680 gg_deallocateL1CacheBlock;
1681 k_popMandatoryQueue;
1684 transition(MM_F, Block_Ack, MI_F) {
1687 kd_wakeUpDependents;
1690 transition(MM, L2_Replacement, MI) {
1693 forward_eviction_to_cpu;
1694 rr_deallocateL2CacheBlock;
1695 ka_wakeUpAllDependents;
1698 transition(MM, {Other_GETX, Invalidate}, I) {
1699 c_sendExclusiveData;
1700 forward_eviction_to_cpu;
1701 gr_deallocateCacheBlock;
1705 transition(MM, Other_GETS, I) {
1706 c_sendExclusiveData;
1707 forward_eviction_to_cpu;
1708 gr_deallocateCacheBlock;
1712 transition(MM, NC_DMA_GETS, O) {
1717 transition(MM, Other_GETS_No_Mig, O) {
1722 transition(MM, Merged_GETS, O) {
1723 em_sendDataSharedMultiple;
1727 // Transitions from Dirty Exclusive
1728 transition(M, Store, MM) {
1730 uu_profileL1DataHit;
1731 k_popMandatoryQueue;
1734 transition(MR, Load, M) {
1736 uu_profileL1DataMiss;
1738 k_popMandatoryQueue;
1739 ka_wakeUpAllDependents;
1742 transition(MR, Ifetch, M) {
1744 uu_profileL1InstMiss;
1746 k_popMandatoryQueue;
1747 ka_wakeUpAllDependents;
1750 transition(MR, Store, MM) {
1752 uu_profileL1DataMiss;
1754 k_popMandatoryQueue;
1755 ka_wakeUpAllDependents;
1758 transition(M, L2_Replacement, MI) {
1761 forward_eviction_to_cpu;
1762 rr_deallocateL2CacheBlock;
1763 ka_wakeUpAllDependents;
1766 transition(M, {Other_GETX, Invalidate}, I) {
1767 c_sendExclusiveData;
1768 forward_eviction_to_cpu;
1769 gr_deallocateCacheBlock;
1773 transition(M, {Other_GETS, Other_GETS_No_Mig}, O) {
1778 transition(M, NC_DMA_GETS, O) {
1783 transition(M, Merged_GETS, O) {
1784 em_sendDataSharedMultiple;
1788 // Transitions from IM
1790 transition({IM, IM_F}, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1795 transition({IM, IM_F, MM_F}, Ack) {
1796 m_decrementNumberOfMessages;
1797 o_checkForCompletion;
1801 transition(IM, Data, ISM) {
1803 m_decrementNumberOfMessages;
1804 o_checkForCompletion;
1808 transition(IM_F, Data, ISM_F) {
1809 uf_writeDataToCacheTBE;
1810 m_decrementNumberOfMessages;
1811 o_checkForCompletion;
1815 transition(IM, Exclusive_Data, MM_W) {
1817 m_decrementNumberOfMessages;
1818 o_checkForCompletion;
1819 sx_external_store_hit;
1821 kd_wakeUpDependents;
1824 transition(IM_F, Exclusive_Data, MM_WF) {
1825 uf_writeDataToCacheTBE;
1826 m_decrementNumberOfMessages;
1827 o_checkForCompletion;
1831 // Transitions from SM
1832 transition({SM, SM_F}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1837 transition(SM, {Other_GETX, Invalidate}, IM) {
1839 forward_eviction_to_cpu;
1843 transition(SM_F, {Other_GETX, Invalidate}, IM_F) {
1845 forward_eviction_to_cpu;
1849 transition({SM, SM_F}, Ack) {
1850 m_decrementNumberOfMessages;
1851 o_checkForCompletion;
1855 transition(SM, {Data, Exclusive_Data}, ISM) {
1856 v_writeDataToCacheVerify;
1857 m_decrementNumberOfMessages;
1858 o_checkForCompletion;
1862 transition(SM_F, {Data, Exclusive_Data}, ISM_F) {
1863 vt_writeDataToTBEVerify;
1864 m_decrementNumberOfMessages;
1865 o_checkForCompletion;
1869 // Transitions from ISM
1870 transition({ISM, ISM_F}, Ack) {
1871 m_decrementNumberOfMessages;
1872 o_checkForCompletion;
1876 transition(ISM, All_acks_no_sharers, MM) {
1877 sxt_trig_ext_store_hit;
1881 kd_wakeUpDependents;
1884 transition(ISM_F, All_acks_no_sharers, MI_F) {
1887 kd_wakeUpDependents;
1890 // Transitions from OM
1892 transition(OM, {Other_GETX, Invalidate}, IM) {
1894 pp_incrementNumberOfMessagesByOne;
1895 forward_eviction_to_cpu;
1899 transition(OM_F, {Other_GETX, Invalidate}, IM_F) {
1900 q_sendDataFromTBEToCache;
1901 pp_incrementNumberOfMessagesByOne;
1902 forward_eviction_to_cpu;
1906 transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1911 transition(OM, Merged_GETS) {
1912 em_sendDataSharedMultiple;
1916 transition(OM_F, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1917 et_sendDataSharedFromTBE;
1921 transition(OM_F, Merged_GETS) {
1922 emt_sendDataSharedMultipleFromTBE;
1926 transition({OM, OM_F}, Ack) {
1927 m_decrementNumberOfMessages;
1928 o_checkForCompletion;
1932 transition(OM, {All_acks, All_acks_no_sharers}, MM) {
1933 sxt_trig_ext_store_hit;
1937 kd_wakeUpDependents;
1940 transition({MM_F, OM_F}, {All_acks, All_acks_no_sharers}, MI_F) {
1943 kd_wakeUpDependents;
1945 // Transitions from IS
1947 transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1952 transition(IS, Ack) {
1953 m_decrementNumberOfMessages;
1954 o_checkForCompletion;
1958 transition(IS, Shared_Ack) {
1959 m_decrementNumberOfMessages;
1961 o_checkForCompletion;
1965 transition(IS, Data, SS) {
1967 m_decrementNumberOfMessages;
1968 o_checkForCompletion;
1969 hx_external_load_hit;
1970 uo_updateCurrentOwner;
1972 kd_wakeUpDependents;
1975 transition(IS, Exclusive_Data, M_W) {
1977 m_decrementNumberOfMessages;
1978 o_checkForCompletion;
1979 hx_external_load_hit;
1981 kd_wakeUpDependents;
1984 transition(IS, Shared_Data, SS) {
1987 m_decrementNumberOfMessages;
1988 o_checkForCompletion;
1989 hx_external_load_hit;
1990 uo_updateCurrentOwner;
1992 kd_wakeUpDependents;
1995 // Transitions from SS
1997 transition(SS, Ack) {
1998 m_decrementNumberOfMessages;
1999 o_checkForCompletion;
2003 transition(SS, Shared_Ack) {
2004 m_decrementNumberOfMessages;
2006 o_checkForCompletion;
2010 transition(SS, All_acks, S) {
2014 kd_wakeUpDependents;
2017 transition(SS, All_acks_no_sharers, S) {
2018 // Note: The directory might still be the owner, so that is why we go to S
2022 kd_wakeUpDependents;
2025 // Transitions from MM_W
2027 transition(MM_W, Store) {
2029 uu_profileL1DataHit;
2030 k_popMandatoryQueue;
2033 transition({MM_W, MM_WF}, Ack) {
2034 m_decrementNumberOfMessages;
2035 o_checkForCompletion;
2039 transition(MM_W, All_acks_no_sharers, MM) {
2043 kd_wakeUpDependents;
2046 transition(MM_WF, All_acks_no_sharers, MI_F) {
2049 kd_wakeUpDependents;
2051 // Transitions from M_W
2053 transition(M_W, Store, MM_W) {
2055 uu_profileL1DataHit;
2056 k_popMandatoryQueue;
2059 transition(M_W, Ack) {
2060 m_decrementNumberOfMessages;
2061 o_checkForCompletion;
2065 transition(M_W, All_acks_no_sharers, M) {
2069 kd_wakeUpDependents;
2072 // Transitions from OI/MI
2074 transition({OI, MI}, {Other_GETX, Invalidate}, II) {
2075 q_sendDataFromTBEToCache;
2079 transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
2080 sq_sendSharedDataFromTBEToCache;
2084 transition({OI, MI}, Merged_GETS, OI) {
2085 qm_sendDataFromTBEToCache;
2089 transition(MI, Writeback_Ack, I) {
2090 t_sendExclusiveDataFromTBEToMemory;
2093 kd_wakeUpDependents;
2096 transition(MI_F, Writeback_Ack, I) {
2098 t_sendExclusiveDataFromTBEToMemory;
2101 kd_wakeUpDependents;
2104 transition(OI, Writeback_Ack, I) {
2105 qq_sendDataFromTBEToMemory;
2108 kd_wakeUpDependents;
2111 // Transitions from II
2112 transition(II, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
2117 transition(II, Writeback_Ack, I) {
2121 kd_wakeUpDependents;
2124 transition(II, Writeback_Nack, I) {
2127 kd_wakeUpDependents;
2130 transition(MM_F, {Other_GETX, Invalidate}, IM_F) {
2131 ct_sendExclusiveDataFromTBE;
2132 pp_incrementNumberOfMessagesByOne;
2136 transition(MM_F, Other_GETS, IM_F) {
2137 ct_sendExclusiveDataFromTBE;
2138 pp_incrementNumberOfMessagesByOne;
2142 transition(MM_F, NC_DMA_GETS, OM_F) {
2143 sq_sendSharedDataFromTBEToCache;
2147 transition(MM_F, Other_GETS_No_Mig, OM_F) {
2148 et_sendDataSharedFromTBE;
2152 transition(MM_F, Merged_GETS, OM_F) {
2153 emt_sendDataSharedMultipleFromTBE;