src/mem/protocol/MOESI_hammer-cache.sm

   1 /*
   2  * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * AMD's contributions to the MOESI hammer protocol do not constitute an
  30  * endorsement of its similarity to any AMD products.
  31  *
  32  * Authors: Milo Martin
  33  *          Brad Beckmann
  34  */
  35
  36 machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
  37 : Sequencer * sequencer;
  38   CacheMemory * L1Icache;
  39   CacheMemory * L1Dcache;
  40   CacheMemory * L2cache;
  41   Cycles cache_response_latency := 10;
  42   Cycles issue_latency := 2;
  43   Cycles l2_cache_hit_latency := 10;
  44   bool no_mig_atomic := "True";
  45   bool send_evictions;
  46 {
  47
  48   // NETWORK BUFFERS
  49   MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="false", vnet_type="request";
  50   MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="false", vnet_type="response";
  51   MessageBuffer unblockFromCache, network="To", virtual_network="5", ordered="false", vnet_type="unblock";
  52
  53   MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="false", vnet_type="forward";
  54   MessageBuffer responseToCache, network="From", virtual_network="4", ordered="false", vnet_type="response";
  55
  56
  57   // STATES
  58   state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
  59     // Base states
  60     I, AccessPermission:Invalid, desc="Idle";
  61     S, AccessPermission:Read_Only, desc="Shared";
  62     O, AccessPermission:Read_Only, desc="Owned";
  63     M, AccessPermission:Read_Only, desc="Modified (dirty)";
  64     MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
  65
  66     // Base states, locked and ready to service the mandatory queue
  67     IR, AccessPermission:Invalid, desc="Idle";
  68     SR, AccessPermission:Read_Only, desc="Shared";
  69     OR, AccessPermission:Read_Only, desc="Owned";
  70     MR, AccessPermission:Read_Only, desc="Modified (dirty)";
  71     MMR, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
  72
  73     // Transient States
  74     IM, AccessPermission:Busy, "IM", desc="Issued GetX";
  75     SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have a valid copy of the line";
  76     OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
  77     ISM, AccessPermission:Read_Only, "ISM", desc="Issued GetX, received valid data, waiting for all acks";
  78     M_W, AccessPermission:Read_Only, "M^W", desc="Issued GetS, received exclusive data";
  79     MM_W, AccessPermission:Read_Write, "MM^W", desc="Issued GetX, received exclusive data";
  80     IS, AccessPermission:Busy, "IS", desc="Issued GetS";
  81     SS, AccessPermission:Read_Only, "SS", desc="Issued GetS, received data, waiting for all acks";
  82     OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
  83     MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
  84     II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack";
  85     IT, AccessPermission:Busy, "IT", desc="Invalid block transferring to L1";
  86     ST, AccessPermission:Busy, "ST", desc="S block transferring to L1";
  87     OT, AccessPermission:Busy, "OT", desc="O block transferring to L1";
  88     MT, AccessPermission:Busy, "MT", desc="M block transferring to L1";
  89     MMT, AccessPermission:Busy, "MMT", desc="MM block transferring to L0";
  90
  91     //Transition States Related to Flushing
  92     MI_F, AccessPermission:Busy, "MI_F", desc="Issued PutX due to a Flush, waiting for ack";
  93     MM_F, AccessPermission:Busy, "MM_F", desc="Issued GETF due to a Flush, waiting for ack";
  94     IM_F, AccessPermission:Busy, "IM_F", desc="Issued GetX due to a Flush";
  95     ISM_F, AccessPermission:Read_Only, "ISM_F", desc="Issued GetX, received data, waiting for all acks";
  96     SM_F, AccessPermission:Read_Only, "SM_F", desc="Issued GetX, we still have an old copy of the line";
  97     OM_F, AccessPermission:Read_Only, "OM_F", desc="Issued GetX, received data";
  98     MM_WF, AccessPermission:Busy, "MM_WF", desc="Issued GetX, received exclusive data";
  99   }
 100
 101   // EVENTS
 102   enumeration(Event, desc="Cache events") {
 103     Load,            desc="Load request from the processor";
 104     Ifetch,          desc="I-fetch request from the processor";
 105     Store,           desc="Store request from the processor";
 106     L2_Replacement,  desc="L2 Replacement";
 107     L1_to_L2,        desc="L1 to L2 transfer";
 108     Trigger_L2_to_L1D,  desc="Trigger L2 to L1-Data transfer";
 109     Trigger_L2_to_L1I,  desc="Trigger L2 to L1-Instruction transfer";
 110     Complete_L2_to_L1, desc="L2 to L1 transfer completed";
 111
 112     // Requests
 113     Other_GETX,      desc="A GetX from another processor";
 114     Other_GETS,      desc="A GetS from another processor";
 115     Merged_GETS,     desc="A Merged GetS from another processor";
 116     Other_GETS_No_Mig, desc="A GetS from another processor";
 117     NC_DMA_GETS,     desc="special GetS when only DMA exists";
 118     Invalidate,      desc="Invalidate block";
 119
 120     // Responses
 121     Ack,             desc="Received an ack message";
 122     Shared_Ack,      desc="Received an ack message, responder has a shared copy";
 123     Data,            desc="Received a data message";
 124     Shared_Data,     desc="Received a data message, responder has a shared copy";
 125     Exclusive_Data,  desc="Received a data message, responder had an exclusive copy, they gave it to us";
 126
 127     Writeback_Ack,   desc="Writeback O.K. from directory";
 128     Writeback_Nack,  desc="Writeback not O.K. from directory";
 129
 130     // Triggers
 131     All_acks,                  desc="Received all required data and message acks";
 132     All_acks_no_sharers,        desc="Received all acks and no other processor has a shared copy";
 133
 134     // For Flush
 135     Flush_line,                  desc="flush the cache line from all caches";
 136     Block_Ack,                   desc="the directory is blocked and ready for the flush";
 137   }
 138
 139   // TYPES
 140
 141   // STRUCTURE DEFINITIONS
 142
 143   MessageBuffer mandatoryQueue, ordered="false";
 144
 145   // CacheEntry
 146   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 147     State CacheState,        desc="cache state";
 148     bool Dirty,              desc="Is the data dirty (different than memory)?";
 149     DataBlock DataBlk,       desc="data for the block";
 150     bool FromL2, default="false", desc="block just moved from L2";
 151     bool AtomicAccessed, default="false", desc="block just moved from L2";
 152   }
 153
 154   // TBE fields
 155   structure(TBE, desc="...") {
 156     State TBEState,          desc="Transient state";
 157     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 158     bool Dirty,              desc="Is the data dirty (different than memory)?";
 159     int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
 160     bool Sharers,            desc="On a GetS, did we find any other sharers in the system";
 161     bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks";
 162     MachineID LastResponder, desc="last machine to send a response for this request";
 163     MachineID CurOwner,      desc="current owner of the block, used for UnblockS responses";
 164
 165     Cycles InitialRequestTime, default="Cycles(0)",
 166             desc="time the initial requests was sent from the L1Cache";
 167     Cycles ForwardRequestTime, default="Cycles(0)",
 168             desc="time the dir forwarded the request";
 169     Cycles FirstResponseTime, default="Cycles(0)",
 170             desc="the time the first response was received";
 171   }
 172
 173   structure(TBETable, external="yes") {
 174     TBE lookup(Address);
 175     void allocate(Address);
 176     void deallocate(Address);
 177     bool isPresent(Address);
 178   }
 179
 180   TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 181
 182   void set_cache_entry(AbstractCacheEntry b);
 183   void unset_cache_entry();
 184   void set_tbe(TBE b);
 185   void unset_tbe();
 186   void wakeUpAllBuffers();
 187   void wakeUpBuffers(Address a);
 188   Cycles curCycle();
 189
 190   Entry getCacheEntry(Address address), return_by_pointer="yes" {
 191     Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
 192     if(is_valid(L2cache_entry)) {
 193       return L2cache_entry;
 194     }
 195
 196     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address));
 197     if(is_valid(L1Dcache_entry)) {
 198       return L1Dcache_entry;
 199     }
 200
 201     Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address));
 202     return L1Icache_entry;
 203   }
 204
 205   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 206     Entry cache_entry := getCacheEntry(addr);
 207     if(is_valid(cache_entry)) {
 208         return cache_entry.DataBlk;
 209     }
 210
 211     TBE tbe := TBEs[addr];
 212     if(is_valid(tbe)) {
 213       return tbe.DataBlk;
 214     }
 215
 216     error("Missing data block");
 217   }
 218
 219   Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
 220     Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
 221     return L2cache_entry;
 222   }
 223
 224   Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
 225     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address));
 226     return L1Dcache_entry;
 227   }
 228
 229   Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
 230     Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address));
 231     return L1Icache_entry;
 232   }
 233
 234   State getState(TBE tbe, Entry cache_entry, Address addr) {
 235     if(is_valid(tbe)) {
 236       return tbe.TBEState;
 237     } else if (is_valid(cache_entry)) {
 238       return cache_entry.CacheState;
 239     }
 240     return State:I;
 241   }
 242
 243   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 244     assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
 245     assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
 246     assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
 247
 248     if (is_valid(tbe)) {
 249       tbe.TBEState := state;
 250     }
 251
 252     if (is_valid(cache_entry)) {
 253       cache_entry.CacheState := state;
 254     }
 255   }
 256
 257   AccessPermission getAccessPermission(Address addr) {
 258     TBE tbe := TBEs[addr];
 259     if(is_valid(tbe)) {
 260       return L1Cache_State_to_permission(tbe.TBEState);
 261     }
 262
 263     Entry cache_entry := getCacheEntry(addr);
 264     if(is_valid(cache_entry)) {
 265       return L1Cache_State_to_permission(cache_entry.CacheState);
 266     }
 267
 268     return AccessPermission:NotPresent;
 269   }
 270
 271   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 272     if (is_valid(cache_entry)) {
 273       cache_entry.changePermission(L1Cache_State_to_permission(state));
 274     }
 275   }
 276
 277   Event mandatory_request_type_to_event(RubyRequestType type) {
 278     if (type == RubyRequestType:LD) {
 279       return Event:Load;
 280     } else if (type == RubyRequestType:IFETCH) {
 281       return Event:Ifetch;
 282     } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
 283       return Event:Store;
 284     } else if ((type == RubyRequestType:FLUSH)) {
 285       return Event:Flush_line;
 286     } else {
 287       error("Invalid RubyRequestType");
 288     }
 289   }
 290
 291   MachineType testAndClearLocalHit(Entry cache_entry) {
 292     if (is_valid(cache_entry) && cache_entry.FromL2) {
 293       cache_entry.FromL2 := false;
 294       return MachineType:L2Cache;
 295     }
 296     return MachineType:L1Cache;
 297   }
 298
 299   bool IsAtomicAccessed(Entry cache_entry) {
 300     assert(is_valid(cache_entry));
 301     return cache_entry.AtomicAccessed;
 302   }
 303
 304   MessageBuffer triggerQueue, ordered="false";
 305
 306   // ** OUT_PORTS **
 307
 308   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 309   out_port(responseNetwork_out, ResponseMsg, responseFromCache);
 310   out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
 311   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 312
 313   // ** IN_PORTS **
 314
 315   // Trigger Queue
 316   in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
 317     if (triggerQueue_in.isReady()) {
 318       peek(triggerQueue_in, TriggerMsg) {
 319
 320         Entry cache_entry := getCacheEntry(in_msg.Addr);
 321         TBE tbe := TBEs[in_msg.Addr];
 322
 323         if (in_msg.Type == TriggerType:L2_to_L1) {
 324           trigger(Event:Complete_L2_to_L1, in_msg.Addr, cache_entry, tbe);
 325         } else if (in_msg.Type == TriggerType:ALL_ACKS) {
 326           trigger(Event:All_acks, in_msg.Addr, cache_entry, tbe);
 327         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
 328           trigger(Event:All_acks_no_sharers, in_msg.Addr, cache_entry, tbe);
 329         } else {
 330           error("Unexpected message");
 331         }
 332       }
 333     }
 334   }
 335
 336   // Nothing from the unblock network
 337
 338   // Response Network
 339   in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
 340     if (responseToCache_in.isReady()) {
 341       peek(responseToCache_in, ResponseMsg, block_on="Addr") {
 342
 343         Entry cache_entry := getCacheEntry(in_msg.Addr);
 344         TBE tbe := TBEs[in_msg.Addr];
 345
 346         if (in_msg.Type == CoherenceResponseType:ACK) {
 347           trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
 348         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
 349           trigger(Event:Shared_Ack, in_msg.Addr, cache_entry, tbe);
 350         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 351           trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
 352         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 353           trigger(Event:Shared_Data, in_msg.Addr, cache_entry, tbe);
 354         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 355           trigger(Event:Exclusive_Data, in_msg.Addr, cache_entry, tbe);
 356         } else {
 357           error("Unexpected message");
 358         }
 359       }
 360     }
 361   }
 362
 363   // Forward Network
 364   in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
 365     if (forwardToCache_in.isReady()) {
 366       peek(forwardToCache_in, RequestMsg, block_on="Addr") {
 367
 368         Entry cache_entry := getCacheEntry(in_msg.Addr);
 369         TBE tbe := TBEs[in_msg.Addr];
 370
 371         if ((in_msg.Type == CoherenceRequestType:GETX) ||
 372             (in_msg.Type == CoherenceRequestType:GETF)) {
 373           trigger(Event:Other_GETX, in_msg.Addr, cache_entry, tbe);
 374         } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
 375           trigger(Event:Merged_GETS, in_msg.Addr, cache_entry, tbe);
 376         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 377           if (machineCount(MachineType:L1Cache) > 1) {
 378             if (is_valid(cache_entry)) {
 379               if (IsAtomicAccessed(cache_entry) && no_mig_atomic) {
 380                 trigger(Event:Other_GETS_No_Mig, in_msg.Addr, cache_entry, tbe);
 381               } else {
 382                 trigger(Event:Other_GETS, in_msg.Addr, cache_entry, tbe);
 383               }
 384             } else {
 385               trigger(Event:Other_GETS, in_msg.Addr, cache_entry, tbe);
 386             }
 387           } else {
 388             trigger(Event:NC_DMA_GETS, in_msg.Addr, cache_entry, tbe);
 389           }
 390         } else if (in_msg.Type == CoherenceRequestType:INV) {
 391           trigger(Event:Invalidate, in_msg.Addr, cache_entry, tbe);
 392         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 393           trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
 394         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 395           trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
 396         } else if (in_msg.Type == CoherenceRequestType:BLOCK_ACK) {
 397           trigger(Event:Block_Ack, in_msg.Addr, cache_entry, tbe);
 398         } else {
 399           error("Unexpected message");
 400         }
 401       }
 402     }
 403   }
 404
 405   // Nothing from the request network
 406
 407   // Mandatory Queue
 408   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
 409     if (mandatoryQueue_in.isReady()) {
 410       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 411
 412         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 413         TBE tbe := TBEs[in_msg.LineAddress];
 414
 415         if (in_msg.Type == RubyRequestType:IFETCH) {
 416           // ** INSTRUCTION ACCESS ***
 417
 418           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 419           if (is_valid(L1Icache_entry)) {
 420             // The tag matches for the L1, so the L1 fetches the line.
 421             // We know it can't be in the L2 due to exclusion
 422             trigger(mandatory_request_type_to_event(in_msg.Type),
 423                     in_msg.LineAddress, L1Icache_entry, tbe);
 424           } else {
 425             // Check to see if it is in the OTHER L1
 426             Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 427             if (is_valid(L1Dcache_entry)) {
 428               // The block is in the wrong L1, try to write it to the L2
 429               if (L2cache.cacheAvail(in_msg.LineAddress)) {
 430                 trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
 431               } else {
 432                 Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
 433                 trigger(Event:L2_Replacement,
 434                         l2_victim_addr,
 435                         getL2CacheEntry(l2_victim_addr),
 436                         TBEs[l2_victim_addr]);
 437               }
 438             }
 439
 440             if (L1Icache.cacheAvail(in_msg.LineAddress)) {
 441               // L1 does't have the line, but we have space for it in the L1
 442
 443               Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
 444               if (is_valid(L2cache_entry)) {
 445                 // L2 has it (maybe not with the right permissions)
 446                 trigger(Event:Trigger_L2_to_L1I, in_msg.LineAddress,
 447                         L2cache_entry, tbe);
 448               } else {
 449                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 450                 trigger(mandatory_request_type_to_event(in_msg.Type),
 451                         in_msg.LineAddress, L1Icache_entry, tbe);
 452               }
 453             } else {
 454               // No room in the L1, so we need to make room
 455               Address l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress);
 456               if (L2cache.cacheAvail(l1i_victim_addr)) {
 457                 // The L2 has room, so we move the line from the L1 to the L2
 458                 trigger(Event:L1_to_L2,
 459                         l1i_victim_addr,
 460                         getL1ICacheEntry(l1i_victim_addr),
 461                         TBEs[l1i_victim_addr]);
 462               } else {
 463                 Address l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
 464                 // The L2 does not have room, so we replace a line from the L2
 465                 trigger(Event:L2_Replacement,
 466                         l2_victim_addr,
 467                         getL2CacheEntry(l2_victim_addr),
 468                         TBEs[l2_victim_addr]);
 469               }
 470             }
 471           }
 472         } else {
 473           // *** DATA ACCESS ***
 474
 475           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 476           if (is_valid(L1Dcache_entry)) {
 477             // The tag matches for the L1, so the L1 fetches the line.
 478             // We know it can't be in the L2 due to exclusion
 479             trigger(mandatory_request_type_to_event(in_msg.Type),
 480                     in_msg.LineAddress, L1Dcache_entry, tbe);
 481           } else {
 482
 483             // Check to see if it is in the OTHER L1
 484             Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 485             if (is_valid(L1Icache_entry)) {
 486               // The block is in the wrong L1, try to write it to the L2
 487               if (L2cache.cacheAvail(in_msg.LineAddress)) {
 488                 trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
 489               } else {
 490                 Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
 491                 trigger(Event:L2_Replacement,
 492                         l2_victim_addr,
 493                         getL2CacheEntry(l2_victim_addr),
 494                         TBEs[l2_victim_addr]);
 495               }
 496             }
 497
 498             if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
 499               // L1 does't have the line, but we have space for it in the L1
 500               Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
 501               if (is_valid(L2cache_entry)) {
 502                 // L2 has it (maybe not with the right permissions)
 503                 trigger(Event:Trigger_L2_to_L1D, in_msg.LineAddress,
 504                         L2cache_entry, tbe);
 505               } else {
 506                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 507                 trigger(mandatory_request_type_to_event(in_msg.Type),
 508                         in_msg.LineAddress, L1Dcache_entry, tbe);
 509               }
 510             } else {
 511               // No room in the L1, so we need to make room
 512               Address l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress);
 513               if (L2cache.cacheAvail(l1d_victim_addr)) {
 514                 // The L2 has room, so we move the line from the L1 to the L2
 515                 trigger(Event:L1_to_L2,
 516                         l1d_victim_addr,
 517                         getL1DCacheEntry(l1d_victim_addr),
 518                         TBEs[l1d_victim_addr]);
 519               } else {
 520                 Address l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
 521                 // The L2 does not have room, so we replace a line from the L2
 522                 trigger(Event:L2_Replacement,
 523                         l2_victim_addr,
 524                         getL2CacheEntry(l2_victim_addr),
 525                         TBEs[l2_victim_addr]);
 526               }
 527             }
 528           }
 529         }
 530       }
 531     }
 532   }
 533
 534   // ACTIONS
 535
 536   action(a_issueGETS, "a", desc="Issue GETS") {
 537     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 538       assert(is_valid(tbe));
 539       out_msg.Addr := address;
 540       out_msg.Type := CoherenceRequestType:GETS;
 541       out_msg.Requestor := machineID;
 542       out_msg.Destination.add(map_Address_to_Directory(address));
 543       out_msg.MessageSize := MessageSizeType:Request_Control;
 544       out_msg.InitialRequestTime := curCycle();
 545
 546       // One from each other cache (n-1) plus the memory (+1)
 547       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
 548     }
 549   }
 550
 551   action(b_issueGETX, "b", desc="Issue GETX") {
 552     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 553       assert(is_valid(tbe));
 554       out_msg.Addr := address;
 555       out_msg.Type := CoherenceRequestType:GETX;
 556       out_msg.Requestor := machineID;
 557       out_msg.Destination.add(map_Address_to_Directory(address));
 558       out_msg.MessageSize := MessageSizeType:Request_Control;
 559       out_msg.InitialRequestTime := curCycle();
 560
 561       // One from each other cache (n-1) plus the memory (+1)
 562       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
 563     }
 564   }
 565
 566   action(b_issueGETXIfMoreThanOne, "bo", desc="Issue GETX") {
 567     if (machineCount(MachineType:L1Cache) > 1) {
 568       enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 569         assert(is_valid(tbe));
 570         out_msg.Addr := address;
 571         out_msg.Type := CoherenceRequestType:GETX;
 572         out_msg.Requestor := machineID;
 573         out_msg.Destination.add(map_Address_to_Directory(address));
 574         out_msg.MessageSize := MessageSizeType:Request_Control;
 575         out_msg.InitialRequestTime := curCycle();
 576       }
 577     }
 578
 579     // One from each other cache (n-1) plus the memory (+1)
 580     tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
 581   }
 582
 583   action(bf_issueGETF, "bf", desc="Issue GETF") {
 584     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 585       assert(is_valid(tbe));
 586       out_msg.Addr := address;
 587       out_msg.Type := CoherenceRequestType:GETF;
 588       out_msg.Requestor := machineID;
 589       out_msg.Destination.add(map_Address_to_Directory(address));
 590       out_msg.MessageSize := MessageSizeType:Request_Control;
 591       out_msg.InitialRequestTime := curCycle();
 592
 593       // One from each other cache (n-1) plus the memory (+1)
 594       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
 595     }
 596   }
 597
 598   action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") {
 599     peek(forwardToCache_in, RequestMsg) {
 600       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 601         assert(is_valid(cache_entry));
 602         out_msg.Addr := address;
 603         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 604         out_msg.Sender := machineID;
 605         out_msg.Destination.add(in_msg.Requestor);
 606         out_msg.DataBlk := cache_entry.DataBlk;
 607         out_msg.Dirty := cache_entry.Dirty;
 608         if (in_msg.DirectedProbe) {
 609           out_msg.Acks := machineCount(MachineType:L1Cache);
 610         } else {
 611           out_msg.Acks := 2;
 612         }
 613         out_msg.SilentAcks := in_msg.SilentAcks;
 614         out_msg.MessageSize := MessageSizeType:Response_Data;
 615         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 616         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 617       }
 618     }
 619   }
 620
 621   action(ct_sendExclusiveDataFromTBE, "ct", desc="Send exclusive data from tbe to requestor") {
 622     peek(forwardToCache_in, RequestMsg) {
 623       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 624         assert(is_valid(tbe));
 625         out_msg.Addr := address;
 626         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 627         out_msg.Sender := machineID;
 628         out_msg.Destination.add(in_msg.Requestor);
 629         out_msg.DataBlk := tbe.DataBlk;
 630         out_msg.Dirty := tbe.Dirty;
 631         if (in_msg.DirectedProbe) {
 632           out_msg.Acks := machineCount(MachineType:L1Cache);
 633         } else {
 634           out_msg.Acks := 2;
 635         }
 636         out_msg.SilentAcks := in_msg.SilentAcks;
 637         out_msg.MessageSize := MessageSizeType:Response_Data;
 638         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 639         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 640       }
 641     }
 642   }
 643
 644   action(d_issuePUT, "d", desc="Issue PUT") {
 645     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 646       out_msg.Addr := address;
 647       out_msg.Type := CoherenceRequestType:PUT;
 648       out_msg.Requestor := machineID;
 649       out_msg.Destination.add(map_Address_to_Directory(address));
 650       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 651     }
 652   }
 653
 654   action(df_issuePUTF, "df", desc="Issue PUTF") {
 655     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 656       out_msg.Addr := address;
 657       out_msg.Type := CoherenceRequestType:PUTF;
 658       out_msg.Requestor := machineID;
 659       out_msg.Destination.add(map_Address_to_Directory(address));
 660       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 661     }
 662   }
 663
 664   action(e_sendData, "e", desc="Send data from cache to requestor") {
 665     peek(forwardToCache_in, RequestMsg) {
 666       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 667         assert(is_valid(cache_entry));
 668         out_msg.Addr := address;
 669         out_msg.Type := CoherenceResponseType:DATA;
 670         out_msg.Sender := machineID;
 671         out_msg.Destination.add(in_msg.Requestor);
 672         out_msg.DataBlk := cache_entry.DataBlk;
 673         out_msg.Dirty := cache_entry.Dirty;
 674         if (in_msg.DirectedProbe) {
 675           out_msg.Acks := machineCount(MachineType:L1Cache);
 676         } else {
 677           out_msg.Acks := 2;
 678         }
 679         out_msg.SilentAcks := in_msg.SilentAcks;
 680         out_msg.MessageSize := MessageSizeType:Response_Data;
 681         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 682         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 683       }
 684     }
 685   }
 686
 687   action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, remaining the owner") {
 688     peek(forwardToCache_in, RequestMsg) {
 689       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 690         assert(is_valid(cache_entry));
 691         out_msg.Addr := address;
 692         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 693         out_msg.Sender := machineID;
 694         out_msg.Destination.add(in_msg.Requestor);
 695         out_msg.DataBlk := cache_entry.DataBlk;
 696         out_msg.Dirty := cache_entry.Dirty;
 697         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 698         if (in_msg.DirectedProbe) {
 699           out_msg.Acks := machineCount(MachineType:L1Cache);
 700         } else {
 701           out_msg.Acks := 2;
 702         }
 703         out_msg.SilentAcks := in_msg.SilentAcks;
 704         out_msg.MessageSize := MessageSizeType:Response_Data;
 705         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 706         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 707       }
 708     }
 709   }
 710
 711   action(et_sendDataSharedFromTBE, "\et", desc="Send data from TBE to requestor, keep a shared copy") {
 712     peek(forwardToCache_in, RequestMsg) {
 713       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 714         assert(is_valid(tbe));
 715         out_msg.Addr := address;
 716         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 717         out_msg.Sender := machineID;
 718         out_msg.Destination.add(in_msg.Requestor);
 719         out_msg.DataBlk := tbe.DataBlk;
 720         out_msg.Dirty := tbe.Dirty;
 721         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 722         if (in_msg.DirectedProbe) {
 723           out_msg.Acks := machineCount(MachineType:L1Cache);
 724         } else {
 725           out_msg.Acks := 2;
 726         }
 727         out_msg.SilentAcks := in_msg.SilentAcks;
 728         out_msg.MessageSize := MessageSizeType:Response_Data;
 729         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 730         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 731       }
 732     }
 733   }
 734
 735   action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors, still the owner") {
 736     peek(forwardToCache_in, RequestMsg) {
 737       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 738         assert(is_valid(cache_entry));
 739         out_msg.Addr := address;
 740         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 741         out_msg.Sender := machineID;
 742         out_msg.Destination := in_msg.MergedRequestors;
 743         out_msg.DataBlk := cache_entry.DataBlk;
 744         out_msg.Dirty := cache_entry.Dirty;
 745         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 746         out_msg.Acks := machineCount(MachineType:L1Cache);
 747         out_msg.SilentAcks := in_msg.SilentAcks;
 748         out_msg.MessageSize := MessageSizeType:Response_Data;
 749         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 750         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 751       }
 752     }
 753   }
 754
 755   action(emt_sendDataSharedMultipleFromTBE, "emt", desc="Send data from tbe to all requestors") {
 756     peek(forwardToCache_in, RequestMsg) {
 757       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 758         assert(is_valid(tbe));
 759         out_msg.Addr := address;
 760         out_msg.Type := CoherenceResponseType:DATA_SHARED;
 761         out_msg.Sender := machineID;
 762         out_msg.Destination := in_msg.MergedRequestors;
 763         out_msg.DataBlk := tbe.DataBlk;
 764         out_msg.Dirty := tbe.Dirty;
 765         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 766         out_msg.Acks := machineCount(MachineType:L1Cache);
 767         out_msg.SilentAcks := in_msg.SilentAcks;
 768         out_msg.MessageSize := MessageSizeType:Response_Data;
 769         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 770         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 771       }
 772     }
 773   }
 774
 775   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 776     peek(forwardToCache_in, RequestMsg) {
 777       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 778         out_msg.Addr := address;
 779         out_msg.Type := CoherenceResponseType:ACK;
 780         out_msg.Sender := machineID;
 781         out_msg.Destination.add(in_msg.Requestor);
 782         out_msg.Acks := 1;
 783         out_msg.SilentAcks := in_msg.SilentAcks;
 784         assert(in_msg.DirectedProbe == false);
 785         out_msg.MessageSize := MessageSizeType:Response_Control;
 786         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 787         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 788       }
 789     }
 790   }
 791
 792   action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") {
 793     peek(forwardToCache_in, RequestMsg) {
 794       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 795         out_msg.Addr := address;
 796         out_msg.Type := CoherenceResponseType:ACK_SHARED;
 797         out_msg.Sender := machineID;
 798         out_msg.Destination.add(in_msg.Requestor);
 799         out_msg.Acks := 1;
 800         out_msg.SilentAcks := in_msg.SilentAcks;
 801         assert(in_msg.DirectedProbe == false);
 802         out_msg.MessageSize := MessageSizeType:Response_Control;
 803         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 804         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
 805       }
 806     }
 807   }
 808
 809   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 810     enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
 811       out_msg.Addr := address;
 812       out_msg.Type := CoherenceResponseType:UNBLOCK;
 813       out_msg.Sender := machineID;
 814       out_msg.Destination.add(map_Address_to_Directory(address));
 815       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 816     }
 817   }
 818
 819   action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") {
 820     enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
 821       out_msg.Addr := address;
 822       out_msg.Type := CoherenceResponseType:UNBLOCKM;
 823       out_msg.Sender := machineID;
 824       out_msg.Destination.add(map_Address_to_Directory(address));
 825       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 826     }
 827   }
 828
 829   action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") {
 830     enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
 831       assert(is_valid(tbe));
 832       out_msg.Addr := address;
 833       out_msg.Type := CoherenceResponseType:UNBLOCKS;
 834       out_msg.Sender := machineID;
 835       out_msg.CurOwner := tbe.CurOwner;
 836       out_msg.Destination.add(map_Address_to_Directory(address));
 837       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 838     }
 839   }
 840
 841   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 842     assert(is_valid(cache_entry));
 843     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 844     sequencer.readCallback(address, cache_entry.DataBlk, false,
 845                            testAndClearLocalHit(cache_entry));
 846   }
 847
 848   action(hx_external_load_hit, "hx", desc="load required external msgs") {
 849     assert(is_valid(cache_entry));
 850     assert(is_valid(tbe));
 851     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 852     peek(responseToCache_in, ResponseMsg) {
 853
 854       sequencer.readCallback(address, cache_entry.DataBlk, true,
 855                  machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
 856                  tbe.ForwardRequestTime, tbe.FirstResponseTime);
 857     }
 858   }
 859
 860   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 861     assert(is_valid(cache_entry));
 862     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 863     peek(mandatoryQueue_in, RubyRequest) {
 864       sequencer.writeCallback(address, cache_entry.DataBlk, false,
 865                               testAndClearLocalHit(cache_entry));
 866
 867       cache_entry.Dirty := true;
 868       if (in_msg.Type == RubyRequestType:ATOMIC) {
 869         cache_entry.AtomicAccessed := true;
 870       }
 871     }
 872   }
 873
 874   action(hh_flush_hit, "\hf", desc="Notify sequencer that flush completed.") {
 875     assert(is_valid(tbe));
 876     DPRINTF(RubySlicc, "%s\n", tbe.DataBlk);
 877     sequencer.writeCallback(address, tbe.DataBlk, false, MachineType:L1Cache);
 878   }
 879
 880   action(sx_external_store_hit, "sx", desc="store required external msgs.") {
 881     assert(is_valid(cache_entry));
 882     assert(is_valid(tbe));
 883     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 884     peek(responseToCache_in, ResponseMsg) {
 885
 886       sequencer.writeCallback(address, cache_entry.DataBlk, true,
 887               machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
 888               tbe.ForwardRequestTime, tbe.FirstResponseTime);
 889     }
 890     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 891     cache_entry.Dirty := true;
 892   }
 893
 894   action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
 895     assert(is_valid(cache_entry));
 896     assert(is_valid(tbe));
 897     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 898
 899     sequencer.writeCallback(address, cache_entry.DataBlk, true,
 900             machineIDToMachineType(tbe.LastResponder), tbe.InitialRequestTime,
 901             tbe.ForwardRequestTime, tbe.FirstResponseTime);
 902
 903     cache_entry.Dirty := true;
 904   }
 905
 906   action(i_allocateTBE, "i", desc="Allocate TBE") {
 907     check_allocate(TBEs);
 908     assert(is_valid(cache_entry));
 909     TBEs.allocate(address);
 910     set_tbe(TBEs[address]);
 911     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
 912     tbe.Dirty := cache_entry.Dirty;
 913     tbe.Sharers := false;
 914   }
 915
 916   action(it_allocateTBE, "it", desc="Allocate TBE") {
 917     check_allocate(TBEs);
 918     TBEs.allocate(address);
 919     set_tbe(TBEs[address]);
 920     tbe.Dirty := false;
 921     tbe.Sharers := false;
 922   }
 923
 924   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 925     triggerQueue_in.dequeue();
 926   }
 927
 928   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 929     mandatoryQueue_in.dequeue();
 930   }
 931
 932   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 933     forwardToCache_in.dequeue();
 934   }
 935
 936   action(hp_copyFromTBEToL2, "li", desc="Copy data from TBE to L2 cache entry.") {
 937     assert(is_valid(cache_entry));
 938     assert(is_valid(tbe));
 939     cache_entry.Dirty   := tbe.Dirty;
 940     cache_entry.DataBlk := tbe.DataBlk;
 941   }
 942
 943   action(nb_copyFromTBEToL1, "fu", desc="Copy data from TBE to L1 cache entry.") {
 944     assert(is_valid(cache_entry));
 945     assert(is_valid(tbe));
 946     cache_entry.Dirty   := tbe.Dirty;
 947     cache_entry.DataBlk := tbe.DataBlk;
 948     cache_entry.FromL2 := true;
 949   }
 950
 951   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 952     peek(responseToCache_in, ResponseMsg) {
 953       assert(in_msg.Acks >= 0);
 954       assert(is_valid(tbe));
 955       DPRINTF(RubySlicc, "Sender = %s\n", in_msg.Sender);
 956       DPRINTF(RubySlicc, "SilentAcks = %d\n", in_msg.SilentAcks);
 957       if (tbe.AppliedSilentAcks == false) {
 958         tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.SilentAcks;
 959         tbe.AppliedSilentAcks := true;
 960       }
 961       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 962       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 963       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 964       APPEND_TRANSITION_COMMENT(tbe.NumPendingMsgs);
 965       APPEND_TRANSITION_COMMENT(in_msg.Sender);
 966       tbe.LastResponder := in_msg.Sender;
 967       if (tbe.InitialRequestTime != zero_time() && in_msg.InitialRequestTime != zero_time()) {
 968         assert(tbe.InitialRequestTime == in_msg.InitialRequestTime);
 969       }
 970       if (in_msg.InitialRequestTime != zero_time()) {
 971         tbe.InitialRequestTime := in_msg.InitialRequestTime;
 972       }
 973       if (tbe.ForwardRequestTime != zero_time() && in_msg.ForwardRequestTime != zero_time()) {
 974         assert(tbe.ForwardRequestTime == in_msg.ForwardRequestTime);
 975       }
 976       if (in_msg.ForwardRequestTime != zero_time()) {
 977         tbe.ForwardRequestTime := in_msg.ForwardRequestTime;
 978       }
 979       if (tbe.FirstResponseTime == zero_time()) {
 980         tbe.FirstResponseTime := curCycle();
 981       }
 982     }
 983   }
 984   action(uo_updateCurrentOwner, "uo", desc="When moving SS state, update current owner.") {
 985     peek(responseToCache_in, ResponseMsg) {
 986       assert(is_valid(tbe));
 987       tbe.CurOwner := in_msg.Sender;
 988     }
 989   }
 990
 991   action(n_popResponseQueue, "n", desc="Pop response queue") {
 992     responseToCache_in.dequeue();
 993   }
 994
 995   action(ll_L2toL1Transfer, "ll", desc="") {
 996     enqueue(triggerQueue_out, TriggerMsg, l2_cache_hit_latency) {
 997       out_msg.Addr := address;
 998       out_msg.Type := TriggerType:L2_to_L1;
 999     }
1000   }
1001
1002   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
1003     assert(is_valid(tbe));
1004     if (tbe.NumPendingMsgs == 0) {
1005       enqueue(triggerQueue_out, TriggerMsg) {
1006         out_msg.Addr := address;
1007         if (tbe.Sharers) {
1008           out_msg.Type := TriggerType:ALL_ACKS;
1009         } else {
1010           out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
1011         }
1012       }
1013     }
1014   }
1015
1016   action(p_decrementNumberOfMessagesByOne, "p", desc="Decrement the number of messages for which we're waiting by one") {
1017     assert(is_valid(tbe));
1018     tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
1019   }
1020
1021   action(pp_incrementNumberOfMessagesByOne, "\p", desc="Increment the number of messages for which we're waiting by one") {
1022     assert(is_valid(tbe));
1023     tbe.NumPendingMsgs := tbe.NumPendingMsgs + 1;
1024   }
1025
1026   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
1027     peek(forwardToCache_in, RequestMsg) {
1028         assert(in_msg.Requestor != machineID);
1029       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
1030         assert(is_valid(tbe));
1031         out_msg.Addr := address;
1032         out_msg.Type := CoherenceResponseType:DATA;
1033         out_msg.Sender := machineID;
1034         out_msg.Destination.add(in_msg.Requestor);
1035         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
1036         out_msg.DataBlk := tbe.DataBlk;
1037         out_msg.Dirty := tbe.Dirty;
1038         if (in_msg.DirectedProbe) {
1039           out_msg.Acks := machineCount(MachineType:L1Cache);
1040         } else {
1041           out_msg.Acks := 2;
1042         }
1043         out_msg.SilentAcks := in_msg.SilentAcks;
1044         out_msg.MessageSize := MessageSizeType:Response_Data;
1045         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
1046         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
1047       }
1048     }
1049   }
1050
1051   action(sq_sendSharedDataFromTBEToCache, "sq", desc="Send shared data from TBE to cache, still the owner") {
1052     peek(forwardToCache_in, RequestMsg) {
1053         assert(in_msg.Requestor != machineID);
1054       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
1055         assert(is_valid(tbe));
1056         out_msg.Addr := address;
1057         out_msg.Type := CoherenceResponseType:DATA_SHARED;
1058         out_msg.Sender := machineID;
1059         out_msg.Destination.add(in_msg.Requestor);
1060         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
1061         out_msg.DataBlk := tbe.DataBlk;
1062         out_msg.Dirty := tbe.Dirty;
1063         if (in_msg.DirectedProbe) {
1064           out_msg.Acks := machineCount(MachineType:L1Cache);
1065         } else {
1066           out_msg.Acks := 2;
1067         }
1068         out_msg.SilentAcks := in_msg.SilentAcks;
1069         out_msg.MessageSize := MessageSizeType:Response_Data;
1070         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
1071         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
1072       }
1073     }
1074   }
1075
1076   action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, multiple sharers, still the owner") {
1077     peek(forwardToCache_in, RequestMsg) {
1078       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
1079         assert(is_valid(tbe));
1080         out_msg.Addr := address;
1081         out_msg.Type := CoherenceResponseType:DATA_SHARED;
1082         out_msg.Sender := machineID;
1083         out_msg.Destination := in_msg.MergedRequestors;
1084         DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
1085         out_msg.DataBlk := tbe.DataBlk;
1086         out_msg.Dirty := tbe.Dirty;
1087         out_msg.Acks := machineCount(MachineType:L1Cache);
1088         out_msg.SilentAcks := in_msg.SilentAcks;
1089         out_msg.MessageSize := MessageSizeType:Response_Data;
1090         out_msg.InitialRequestTime := in_msg.InitialRequestTime;
1091         out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
1092       }
1093     }
1094   }
1095
1096   action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
1097     enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
1098       assert(is_valid(tbe));
1099       out_msg.Addr := address;
1100       out_msg.Sender := machineID;
1101       out_msg.Destination.add(map_Address_to_Directory(address));
1102       out_msg.Dirty := tbe.Dirty;
1103       if (tbe.Dirty) {
1104         out_msg.Type := CoherenceResponseType:WB_DIRTY;
1105         out_msg.DataBlk := tbe.DataBlk;
1106         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1107       } else {
1108         out_msg.Type := CoherenceResponseType:WB_CLEAN;
1109         // NOTE: in a real system this would not send data.  We send
1110         // data here only so we can check it at the memory
1111         out_msg.DataBlk := tbe.DataBlk;
1112         out_msg.MessageSize := MessageSizeType:Writeback_Control;
1113       }
1114     }
1115   }
1116
1117   action(r_setSharerBit, "r", desc="We saw other sharers") {
1118     assert(is_valid(tbe));
1119     tbe.Sharers := true;
1120   }
1121
1122   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
1123     TBEs.deallocate(address);
1124     unset_tbe();
1125   }
1126
1127   action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") {
1128     enqueue(unblockNetwork_out, ResponseMsg, cache_response_latency) {
1129       assert(is_valid(tbe));
1130       out_msg.Addr := address;
1131       out_msg.Sender := machineID;
1132       out_msg.Destination.add(map_Address_to_Directory(address));
1133       out_msg.DataBlk := tbe.DataBlk;
1134       out_msg.Dirty := tbe.Dirty;
1135       if (tbe.Dirty) {
1136         out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_DIRTY;
1137         out_msg.DataBlk := tbe.DataBlk;
1138         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1139       } else {
1140         out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_CLEAN;
1141         // NOTE: in a real system this would not send data.  We send
1142         // data here only so we can check it at the memory
1143         out_msg.DataBlk := tbe.DataBlk;
1144         out_msg.MessageSize := MessageSizeType:Writeback_Control;
1145       }
1146     }
1147   }
1148
1149   action(u_writeDataToCache, "u", desc="Write data to cache") {
1150     peek(responseToCache_in, ResponseMsg) {
1151       assert(is_valid(cache_entry));
1152       cache_entry.DataBlk := in_msg.DataBlk;
1153       cache_entry.Dirty := in_msg.Dirty;
1154     }
1155   }
1156
1157   action(uf_writeDataToCacheTBE, "uf", desc="Write data to TBE") {
1158     peek(responseToCache_in, ResponseMsg) {
1159       assert(is_valid(tbe));
1160       tbe.DataBlk := in_msg.DataBlk;
1161       tbe.Dirty := in_msg.Dirty;
1162     }
1163   }
1164
1165   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
1166     peek(responseToCache_in, ResponseMsg) {
1167       assert(is_valid(cache_entry));
1168       DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
1169               cache_entry.DataBlk, in_msg.DataBlk);
1170       assert(cache_entry.DataBlk == in_msg.DataBlk);
1171       cache_entry.DataBlk := in_msg.DataBlk;
1172       cache_entry.Dirty := in_msg.Dirty || cache_entry.Dirty;
1173     }
1174   }
1175
1176   action(vt_writeDataToTBEVerify, "vt", desc="Write data to TBE, assert it was same as before") {
1177     peek(responseToCache_in, ResponseMsg) {
1178       assert(is_valid(tbe));
1179       DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
1180               tbe.DataBlk, in_msg.DataBlk);
1181       assert(tbe.DataBlk == in_msg.DataBlk);
1182       tbe.DataBlk := in_msg.DataBlk;
1183       tbe.Dirty := in_msg.Dirty || tbe.Dirty;
1184     }
1185   }
1186
1187   action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
1188     if (L1Dcache.isTagPresent(address)) {
1189       L1Dcache.deallocate(address);
1190     } else {
1191       L1Icache.deallocate(address);
1192     }
1193     unset_cache_entry();
1194   }
1195
1196   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
1197     if (is_invalid(cache_entry)) {
1198       set_cache_entry(L1Dcache.allocate(address, new Entry));
1199     }
1200   }
1201
1202   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
1203     if (is_invalid(cache_entry)) {
1204       set_cache_entry(L1Icache.allocate(address, new Entry));
1205     }
1206   }
1207
1208   action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
1209     set_cache_entry(L2cache.allocate(address, new Entry));
1210   }
1211
1212   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
1213     L2cache.deallocate(address);
1214     unset_cache_entry();
1215   }
1216
1217   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
1218     if (send_evictions) {
1219       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1220       sequencer.evictionCallback(address);
1221     }
1222   }
1223
1224   action(uu_profileL1DataMiss, "\udm", desc="Profile the demand miss") {
1225       ++L1Dcache.demand_misses;
1226   }
1227
1228   action(uu_profileL1DataHit, "\udh", desc="Profile the demand hits") {
1229       ++L1Dcache.demand_hits;
1230   }
1231
1232   action(uu_profileL1InstMiss, "\uim", desc="Profile the demand miss") {
1233       ++L1Icache.demand_misses;
1234   }
1235
1236   action(uu_profileL1InstHit, "\uih", desc="Profile the demand hits") {
1237       ++L1Icache.demand_hits;
1238   }
1239
1240   action(uu_profileL2Miss, "\um", desc="Profile the demand miss") {
1241       ++L2cache.demand_misses;
1242   }
1243
1244   action(uu_profileL2Hit, "\uh", desc="Profile the demand hits ") {
1245       ++L2cache.demand_hits;
1246   }
1247
1248   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
1249     stall_and_wait(mandatoryQueue_in, address);
1250   }
1251
1252   action(z_stall, "z", desc="stall") {
1253     // do nothing and the special z_stall action will return a protocol stall
1254     // so that the next port is checked
1255   }
1256
1257   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
1258     wakeUpBuffers(address);
1259   }
1260
1261   action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
1262     wakeUpAllBuffers();
1263   }
1264
1265   //*****************************************************
1266   // TRANSITIONS
1267   //*****************************************************
1268
1269   // Transitions for Load/Store/L2_Replacement from transient states
1270   transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) {
1271     zz_stallAndWaitMandatoryQueue;
1272   }
1273
1274   transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II}, {Flush_line}) {
1275     zz_stallAndWaitMandatoryQueue;
1276   }
1277
1278   transition({M_W, MM_W}, {L2_Replacement, Flush_line}) {
1279     zz_stallAndWaitMandatoryQueue;
1280   }
1281
1282   transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT, MI_F, MM_F, OM_F, IM_F, ISM_F, SM_F, MM_WF}, {Load, Ifetch}) {
1283     zz_stallAndWaitMandatoryQueue;
1284   }
1285
1286   transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F, IR, SR, OR, MR, MMR}, L1_to_L2) {
1287     zz_stallAndWaitMandatoryQueue;
1288   }
1289
1290   transition({MI_F, MM_F}, {Store}) {
1291     zz_stallAndWaitMandatoryQueue;
1292   }
1293
1294   transition({MM_F, MI_F}, {Flush_line}) {
1295     zz_stallAndWaitMandatoryQueue;
1296   }
1297
1298   transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) {
1299     z_stall;
1300   }
1301
1302   transition({IR, SR, OR, MR, MMR}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
1303     z_stall;
1304   }
1305
1306   // Transitions moving data between the L1 and L2 caches
1307   transition({I, S, O, M, MM}, L1_to_L2) {
1308     i_allocateTBE;
1309     gg_deallocateL1CacheBlock;
1310     vv_allocateL2CacheBlock;
1311     hp_copyFromTBEToL2;
1312     s_deallocateTBE;
1313   }
1314
1315   transition(I, Trigger_L2_to_L1D, IT) {
1316     i_allocateTBE;
1317     rr_deallocateL2CacheBlock;
1318     ii_allocateL1DCacheBlock;
1319     nb_copyFromTBEToL1; // Not really needed for state I
1320     s_deallocateTBE;
1321     zz_stallAndWaitMandatoryQueue;
1322     ll_L2toL1Transfer;
1323   }
1324
1325   transition(S, Trigger_L2_to_L1D, ST) {
1326     i_allocateTBE;
1327     rr_deallocateL2CacheBlock;
1328     ii_allocateL1DCacheBlock;
1329     nb_copyFromTBEToL1;
1330     s_deallocateTBE;
1331     zz_stallAndWaitMandatoryQueue;
1332     ll_L2toL1Transfer;
1333   }
1334
1335   transition(O, Trigger_L2_to_L1D, OT) {
1336     i_allocateTBE;
1337     rr_deallocateL2CacheBlock;
1338     ii_allocateL1DCacheBlock;
1339     nb_copyFromTBEToL1;
1340     s_deallocateTBE;
1341     zz_stallAndWaitMandatoryQueue;
1342     ll_L2toL1Transfer;
1343   }
1344
1345   transition(M, Trigger_L2_to_L1D, MT) {
1346     i_allocateTBE;
1347     rr_deallocateL2CacheBlock;
1348     ii_allocateL1DCacheBlock;
1349     nb_copyFromTBEToL1;
1350     s_deallocateTBE;
1351     zz_stallAndWaitMandatoryQueue;
1352     ll_L2toL1Transfer;
1353   }
1354
1355   transition(MM, Trigger_L2_to_L1D, MMT) {
1356     i_allocateTBE;
1357     rr_deallocateL2CacheBlock;
1358     ii_allocateL1DCacheBlock;
1359     nb_copyFromTBEToL1;
1360     s_deallocateTBE;
1361     zz_stallAndWaitMandatoryQueue;
1362     ll_L2toL1Transfer;
1363   }
1364
1365   transition(I, Trigger_L2_to_L1I, IT) {
1366     i_allocateTBE;
1367     rr_deallocateL2CacheBlock;
1368     jj_allocateL1ICacheBlock;
1369     nb_copyFromTBEToL1;
1370     s_deallocateTBE;
1371     zz_stallAndWaitMandatoryQueue;
1372     ll_L2toL1Transfer;
1373   }
1374
1375   transition(S, Trigger_L2_to_L1I, ST) {
1376     i_allocateTBE;
1377     rr_deallocateL2CacheBlock;
1378     jj_allocateL1ICacheBlock;
1379     nb_copyFromTBEToL1;
1380     s_deallocateTBE;
1381     zz_stallAndWaitMandatoryQueue;
1382     ll_L2toL1Transfer;
1383   }
1384
1385   transition(O, Trigger_L2_to_L1I, OT) {
1386     i_allocateTBE;
1387     rr_deallocateL2CacheBlock;
1388     jj_allocateL1ICacheBlock;
1389     nb_copyFromTBEToL1;
1390     s_deallocateTBE;
1391     zz_stallAndWaitMandatoryQueue;
1392     ll_L2toL1Transfer;
1393   }
1394
1395   transition(M, Trigger_L2_to_L1I, MT) {
1396     i_allocateTBE;
1397     rr_deallocateL2CacheBlock;
1398     jj_allocateL1ICacheBlock;
1399     nb_copyFromTBEToL1;
1400     s_deallocateTBE;
1401     zz_stallAndWaitMandatoryQueue;
1402     ll_L2toL1Transfer;
1403   }
1404
1405   transition(MM, Trigger_L2_to_L1I, MMT) {
1406     i_allocateTBE;
1407     rr_deallocateL2CacheBlock;
1408     jj_allocateL1ICacheBlock;
1409     nb_copyFromTBEToL1;
1410     s_deallocateTBE;
1411     zz_stallAndWaitMandatoryQueue;
1412     ll_L2toL1Transfer;
1413   }
1414
1415   transition(IT, Complete_L2_to_L1, IR) {
1416     j_popTriggerQueue;
1417     kd_wakeUpDependents;
1418   }
1419
1420   transition(ST, Complete_L2_to_L1, SR) {
1421     j_popTriggerQueue;
1422     kd_wakeUpDependents;
1423   }
1424
1425   transition(OT, Complete_L2_to_L1, OR) {
1426     j_popTriggerQueue;
1427     kd_wakeUpDependents;
1428   }
1429
1430   transition(MT, Complete_L2_to_L1, MR) {
1431     j_popTriggerQueue;
1432     kd_wakeUpDependents;
1433   }
1434
1435   transition(MMT, Complete_L2_to_L1, MMR) {
1436     j_popTriggerQueue;
1437     kd_wakeUpDependents;
1438   }
1439
1440   // Transitions from Idle
1441   transition({I,IR}, Load, IS) {
1442     ii_allocateL1DCacheBlock;
1443     i_allocateTBE;
1444     a_issueGETS;
1445     uu_profileL1DataMiss;
1446     uu_profileL2Miss;
1447     k_popMandatoryQueue;
1448   }
1449
1450   transition({I,IR}, Ifetch, IS) {
1451     jj_allocateL1ICacheBlock;
1452     i_allocateTBE;
1453     a_issueGETS;
1454     uu_profileL1InstMiss;
1455     uu_profileL2Miss;
1456     k_popMandatoryQueue;
1457   }
1458
1459   transition({I,IR}, Store, IM) {
1460     ii_allocateL1DCacheBlock;
1461     i_allocateTBE;
1462     b_issueGETX;
1463     uu_profileL1DataMiss;
1464     uu_profileL2Miss;
1465     k_popMandatoryQueue;
1466   }
1467
1468   transition({I, IR}, Flush_line, IM_F) {
1469     it_allocateTBE;
1470     bf_issueGETF;
1471     k_popMandatoryQueue;
1472   }
1473
1474   transition(I, L2_Replacement) {
1475     rr_deallocateL2CacheBlock;
1476     ka_wakeUpAllDependents;
1477   }
1478
1479   transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1480     f_sendAck;
1481     l_popForwardQueue;
1482   }
1483
1484   // Transitions from Shared
1485   transition({S, SM, ISM}, Load) {
1486     h_load_hit;
1487     uu_profileL1DataHit;
1488     k_popMandatoryQueue;
1489   }
1490
1491   transition({S, SM, ISM}, Ifetch) {
1492     h_load_hit;
1493     uu_profileL1InstHit;
1494     k_popMandatoryQueue;
1495   }
1496
1497   transition(SR, Load, S) {
1498     h_load_hit;
1499     uu_profileL1DataMiss;
1500     uu_profileL2Hit;
1501     k_popMandatoryQueue;
1502     ka_wakeUpAllDependents;
1503   }
1504
1505   transition(SR, Ifetch, S) {
1506     h_load_hit;
1507     uu_profileL1InstMiss;
1508     uu_profileL2Hit;
1509     k_popMandatoryQueue;
1510     ka_wakeUpAllDependents;
1511   }
1512
1513   transition({S,SR}, Store, SM) {
1514     i_allocateTBE;
1515     b_issueGETX;
1516     uu_profileL1DataMiss;
1517     uu_profileL2Miss;
1518     k_popMandatoryQueue;
1519   }
1520
1521   transition({S, SR}, Flush_line, SM_F) {
1522     i_allocateTBE;
1523     bf_issueGETF;
1524     forward_eviction_to_cpu;
1525     gg_deallocateL1CacheBlock;
1526     k_popMandatoryQueue;
1527   }
1528
1529   transition(S, L2_Replacement, I) {
1530     forward_eviction_to_cpu;
1531     rr_deallocateL2CacheBlock;
1532     ka_wakeUpAllDependents;
1533   }
1534
1535   transition(S, {Other_GETX, Invalidate}, I) {
1536     f_sendAck;
1537     forward_eviction_to_cpu;
1538     l_popForwardQueue;
1539   }
1540
1541   transition(S, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1542     ff_sendAckShared;
1543     l_popForwardQueue;
1544   }
1545
1546   // Transitions from Owned
1547   transition({O, OM, SS, MM_W, M_W}, {Load}) {
1548     h_load_hit;
1549     uu_profileL1DataHit;
1550     k_popMandatoryQueue;
1551   }
1552
1553   transition({O, OM, SS, MM_W, M_W}, {Ifetch}) {
1554     h_load_hit;
1555     uu_profileL1InstHit;
1556     k_popMandatoryQueue;
1557   }
1558
1559   transition(OR, Load, O) {
1560     h_load_hit;
1561     uu_profileL1DataMiss;
1562     uu_profileL2Hit;
1563     k_popMandatoryQueue;
1564     ka_wakeUpAllDependents;
1565   }
1566
1567   transition(OR, Ifetch, O) {
1568     h_load_hit;
1569     uu_profileL1InstMiss;
1570     uu_profileL2Hit;
1571     k_popMandatoryQueue;
1572     ka_wakeUpAllDependents;
1573   }
1574
1575   transition({O,OR}, Store, OM) {
1576     i_allocateTBE;
1577     b_issueGETX;
1578     p_decrementNumberOfMessagesByOne;
1579     uu_profileL1DataMiss;
1580     uu_profileL2Miss;
1581     k_popMandatoryQueue;
1582   }
1583
1584   transition({O, OR}, Flush_line, OM_F) {
1585     i_allocateTBE;
1586     bf_issueGETF;
1587     p_decrementNumberOfMessagesByOne;
1588     forward_eviction_to_cpu;
1589     gg_deallocateL1CacheBlock;
1590     k_popMandatoryQueue;
1591   }
1592
1593   transition(O, L2_Replacement, OI) {
1594     i_allocateTBE;
1595     d_issuePUT;
1596     forward_eviction_to_cpu;
1597     rr_deallocateL2CacheBlock;
1598     ka_wakeUpAllDependents;
1599   }
1600
1601   transition(O, {Other_GETX, Invalidate}, I) {
1602     e_sendData;
1603     forward_eviction_to_cpu;
1604     l_popForwardQueue;
1605   }
1606
1607   transition(O, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1608     ee_sendDataShared;
1609     l_popForwardQueue;
1610   }
1611
1612   transition(O, Merged_GETS) {
1613     em_sendDataSharedMultiple;
1614     l_popForwardQueue;
1615   }
1616
1617   // Transitions from Modified
1618   transition({MM, M}, {Ifetch}) {
1619     h_load_hit;
1620     uu_profileL1InstHit;
1621     k_popMandatoryQueue;
1622   }
1623
1624   transition({MM, M}, {Load}) {
1625     h_load_hit;
1626     uu_profileL1DataHit;
1627     k_popMandatoryQueue;
1628   }
1629
1630   transition(MM, Store) {
1631     hh_store_hit;
1632     uu_profileL1DataHit;
1633     k_popMandatoryQueue;
1634   }
1635
1636   transition(MMR, Load, MM) {
1637     h_load_hit;
1638     uu_profileL1DataMiss;
1639     uu_profileL2Hit;
1640     k_popMandatoryQueue;
1641     ka_wakeUpAllDependents;
1642   }
1643
1644   transition(MMR, Ifetch, MM) {
1645     h_load_hit;
1646     uu_profileL1InstMiss;
1647     uu_profileL2Hit;
1648     k_popMandatoryQueue;
1649     ka_wakeUpAllDependents;
1650   }
1651
1652   transition(MMR, Store, MM) {
1653     hh_store_hit;
1654     uu_profileL1DataMiss;
1655     uu_profileL2Hit;
1656     k_popMandatoryQueue;
1657     ka_wakeUpAllDependents;
1658   }
1659
1660   transition({MM, M, MMR, MR}, Flush_line, MM_F) {
1661     i_allocateTBE;
1662     bf_issueGETF;
1663     p_decrementNumberOfMessagesByOne;
1664     forward_eviction_to_cpu;
1665     gg_deallocateL1CacheBlock;
1666     k_popMandatoryQueue;
1667   }
1668
1669   transition(MM_F, Block_Ack, MI_F) {
1670     df_issuePUTF;
1671     l_popForwardQueue;
1672     kd_wakeUpDependents;
1673   }
1674
1675   transition(MM, L2_Replacement, MI) {
1676     i_allocateTBE;
1677     d_issuePUT;
1678     forward_eviction_to_cpu;
1679     rr_deallocateL2CacheBlock;
1680     ka_wakeUpAllDependents;
1681   }
1682
1683   transition(MM, {Other_GETX, Invalidate}, I) {
1684     c_sendExclusiveData;
1685     forward_eviction_to_cpu;
1686     l_popForwardQueue;
1687   }
1688
1689   transition(MM, Other_GETS, I) {
1690     c_sendExclusiveData;
1691     forward_eviction_to_cpu;
1692     l_popForwardQueue;
1693   }
1694
1695   transition(MM, NC_DMA_GETS, O) {
1696     ee_sendDataShared;
1697     l_popForwardQueue;
1698   }
1699
1700   transition(MM, Other_GETS_No_Mig, O) {
1701     ee_sendDataShared;
1702     l_popForwardQueue;
1703   }
1704
1705   transition(MM, Merged_GETS, O) {
1706     em_sendDataSharedMultiple;
1707     l_popForwardQueue;
1708   }
1709
1710   // Transitions from Dirty Exclusive
1711   transition(M, Store, MM) {
1712     hh_store_hit;
1713     uu_profileL1DataHit;
1714     k_popMandatoryQueue;
1715   }
1716
1717   transition(MR, Load, M) {
1718     h_load_hit;
1719     uu_profileL1DataMiss;
1720     uu_profileL2Hit;
1721     k_popMandatoryQueue;
1722     ka_wakeUpAllDependents;
1723   }
1724
1725   transition(MR, Ifetch, M) {
1726     h_load_hit;
1727     uu_profileL1InstMiss;
1728     uu_profileL2Hit;
1729     k_popMandatoryQueue;
1730     ka_wakeUpAllDependents;
1731   }
1732
1733   transition(MR, Store, MM) {
1734     hh_store_hit;
1735     uu_profileL1DataMiss;
1736     uu_profileL2Hit;
1737     k_popMandatoryQueue;
1738     ka_wakeUpAllDependents;
1739   }
1740
1741   transition(M, L2_Replacement, MI) {
1742     i_allocateTBE;
1743     d_issuePUT;
1744     forward_eviction_to_cpu;
1745     rr_deallocateL2CacheBlock;
1746     ka_wakeUpAllDependents;
1747   }
1748
1749   transition(M, {Other_GETX, Invalidate}, I) {
1750     c_sendExclusiveData;
1751     forward_eviction_to_cpu;
1752     l_popForwardQueue;
1753   }
1754
1755   transition(M, {Other_GETS, Other_GETS_No_Mig}, O) {
1756     ee_sendDataShared;
1757     l_popForwardQueue;
1758   }
1759
1760   transition(M, NC_DMA_GETS, O) {
1761     ee_sendDataShared;
1762     l_popForwardQueue;
1763   }
1764
1765   transition(M, Merged_GETS, O) {
1766     em_sendDataSharedMultiple;
1767     l_popForwardQueue;
1768   }
1769
1770   // Transitions from IM
1771
1772   transition({IM, IM_F}, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1773     f_sendAck;
1774     l_popForwardQueue;
1775   }
1776
1777   transition({IM, IM_F, MM_F}, Ack) {
1778     m_decrementNumberOfMessages;
1779     o_checkForCompletion;
1780     n_popResponseQueue;
1781   }
1782
1783   transition(IM, Data, ISM) {
1784     u_writeDataToCache;
1785     m_decrementNumberOfMessages;
1786     o_checkForCompletion;
1787     n_popResponseQueue;
1788   }
1789
1790   transition(IM_F, Data, ISM_F) {
1791       uf_writeDataToCacheTBE;
1792       m_decrementNumberOfMessages;
1793       o_checkForCompletion;
1794       n_popResponseQueue;
1795   }
1796
1797   transition(IM, Exclusive_Data, MM_W) {
1798     u_writeDataToCache;
1799     m_decrementNumberOfMessages;
1800     o_checkForCompletion;
1801     sx_external_store_hit;
1802     n_popResponseQueue;
1803     kd_wakeUpDependents;
1804   }
1805
1806   transition(IM_F, Exclusive_Data, MM_WF) {
1807       uf_writeDataToCacheTBE;
1808       m_decrementNumberOfMessages;
1809       o_checkForCompletion;
1810       n_popResponseQueue;
1811   }
1812
1813   // Transitions from SM
1814   transition({SM, SM_F}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1815     ff_sendAckShared;
1816     l_popForwardQueue;
1817   }
1818
1819   transition(SM, {Other_GETX, Invalidate}, IM) {
1820     f_sendAck;
1821     forward_eviction_to_cpu;
1822     l_popForwardQueue;
1823   }
1824
1825   transition(SM_F, {Other_GETX, Invalidate}, IM_F) {
1826     f_sendAck;
1827     forward_eviction_to_cpu;
1828     l_popForwardQueue;
1829   }
1830
1831   transition({SM, SM_F}, Ack) {
1832     m_decrementNumberOfMessages;
1833     o_checkForCompletion;
1834     n_popResponseQueue;
1835   }
1836
1837   transition(SM, {Data, Exclusive_Data}, ISM) {
1838     v_writeDataToCacheVerify;
1839     m_decrementNumberOfMessages;
1840     o_checkForCompletion;
1841     n_popResponseQueue;
1842   }
1843
1844   transition(SM_F, {Data, Exclusive_Data}, ISM_F) {
1845     vt_writeDataToTBEVerify;
1846     m_decrementNumberOfMessages;
1847     o_checkForCompletion;
1848     n_popResponseQueue;
1849   }
1850
1851   // Transitions from ISM
1852   transition({ISM, ISM_F}, Ack) {
1853     m_decrementNumberOfMessages;
1854     o_checkForCompletion;
1855     n_popResponseQueue;
1856   }
1857
1858   transition(ISM, All_acks_no_sharers, MM) {
1859     sxt_trig_ext_store_hit;
1860     gm_sendUnblockM;
1861     s_deallocateTBE;
1862     j_popTriggerQueue;
1863     kd_wakeUpDependents;
1864   }
1865
1866   transition(ISM_F, All_acks_no_sharers, MI_F) {
1867     df_issuePUTF;
1868     j_popTriggerQueue;
1869     kd_wakeUpDependents;
1870   }
1871
1872   // Transitions from OM
1873
1874   transition(OM, {Other_GETX, Invalidate}, IM) {
1875     e_sendData;
1876     pp_incrementNumberOfMessagesByOne;
1877     forward_eviction_to_cpu;
1878     l_popForwardQueue;
1879   }
1880
1881   transition(OM_F, {Other_GETX, Invalidate}, IM_F) {
1882     q_sendDataFromTBEToCache;
1883     pp_incrementNumberOfMessagesByOne;
1884     forward_eviction_to_cpu;
1885     l_popForwardQueue;
1886   }
1887
1888   transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1889     ee_sendDataShared;
1890     l_popForwardQueue;
1891   }
1892
1893   transition(OM, Merged_GETS) {
1894     em_sendDataSharedMultiple;
1895     l_popForwardQueue;
1896   }
1897
1898   transition(OM_F, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
1899     et_sendDataSharedFromTBE;
1900     l_popForwardQueue;
1901   }
1902
1903   transition(OM_F, Merged_GETS) {
1904     emt_sendDataSharedMultipleFromTBE;
1905     l_popForwardQueue;
1906   }
1907
1908   transition({OM, OM_F}, Ack) {
1909     m_decrementNumberOfMessages;
1910     o_checkForCompletion;
1911     n_popResponseQueue;
1912   }
1913
1914   transition(OM, {All_acks, All_acks_no_sharers}, MM) {
1915     sxt_trig_ext_store_hit;
1916     gm_sendUnblockM;
1917     s_deallocateTBE;
1918     j_popTriggerQueue;
1919     kd_wakeUpDependents;
1920   }
1921
1922   transition({MM_F, OM_F}, {All_acks, All_acks_no_sharers}, MI_F) {
1923     df_issuePUTF;
1924     j_popTriggerQueue;
1925     kd_wakeUpDependents;
1926   }
1927   // Transitions from IS
1928
1929   transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
1930     f_sendAck;
1931     l_popForwardQueue;
1932   }
1933
1934   transition(IS, Ack) {
1935     m_decrementNumberOfMessages;
1936     o_checkForCompletion;
1937     n_popResponseQueue;
1938   }
1939
1940   transition(IS, Shared_Ack) {
1941     m_decrementNumberOfMessages;
1942     r_setSharerBit;
1943     o_checkForCompletion;
1944     n_popResponseQueue;
1945   }
1946
1947   transition(IS, Data, SS) {
1948     u_writeDataToCache;
1949     m_decrementNumberOfMessages;
1950     o_checkForCompletion;
1951     hx_external_load_hit;
1952     uo_updateCurrentOwner;
1953     n_popResponseQueue;
1954     kd_wakeUpDependents;
1955   }
1956
1957   transition(IS, Exclusive_Data, M_W) {
1958     u_writeDataToCache;
1959     m_decrementNumberOfMessages;
1960     o_checkForCompletion;
1961     hx_external_load_hit;
1962     n_popResponseQueue;
1963     kd_wakeUpDependents;
1964   }
1965
1966   transition(IS, Shared_Data, SS) {
1967     u_writeDataToCache;
1968     r_setSharerBit;
1969     m_decrementNumberOfMessages;
1970     o_checkForCompletion;
1971     hx_external_load_hit;
1972     uo_updateCurrentOwner;
1973     n_popResponseQueue;
1974     kd_wakeUpDependents;
1975   }
1976
1977   // Transitions from SS
1978
1979   transition(SS, Ack) {
1980     m_decrementNumberOfMessages;
1981     o_checkForCompletion;
1982     n_popResponseQueue;
1983   }
1984
1985   transition(SS, Shared_Ack) {
1986     m_decrementNumberOfMessages;
1987     r_setSharerBit;
1988     o_checkForCompletion;
1989     n_popResponseQueue;
1990   }
1991
1992   transition(SS, All_acks, S) {
1993     gs_sendUnblockS;
1994     s_deallocateTBE;
1995     j_popTriggerQueue;
1996     kd_wakeUpDependents;
1997   }
1998
1999   transition(SS, All_acks_no_sharers, S) {
2000     // Note: The directory might still be the owner, so that is why we go to S
2001     gs_sendUnblockS;
2002     s_deallocateTBE;
2003     j_popTriggerQueue;
2004     kd_wakeUpDependents;
2005   }
2006
2007   // Transitions from MM_W
2008
2009   transition(MM_W, Store) {
2010     hh_store_hit;
2011     uu_profileL1DataHit;
2012     k_popMandatoryQueue;
2013   }
2014
2015   transition({MM_W, MM_WF}, Ack) {
2016     m_decrementNumberOfMessages;
2017     o_checkForCompletion;
2018     n_popResponseQueue;
2019   }
2020
2021   transition(MM_W, All_acks_no_sharers, MM) {
2022     gm_sendUnblockM;
2023     s_deallocateTBE;
2024     j_popTriggerQueue;
2025     kd_wakeUpDependents;
2026   }
2027
2028   transition(MM_WF, All_acks_no_sharers, MI_F) {
2029     df_issuePUTF;
2030     j_popTriggerQueue;
2031     kd_wakeUpDependents;
2032   }
2033   // Transitions from M_W
2034
2035   transition(M_W, Store, MM_W) {
2036     hh_store_hit;
2037     uu_profileL1DataHit;
2038     k_popMandatoryQueue;
2039   }
2040
2041   transition(M_W, Ack) {
2042     m_decrementNumberOfMessages;
2043     o_checkForCompletion;
2044     n_popResponseQueue;
2045   }
2046
2047   transition(M_W, All_acks_no_sharers, M) {
2048     gm_sendUnblockM;
2049     s_deallocateTBE;
2050     j_popTriggerQueue;
2051     kd_wakeUpDependents;
2052   }
2053
2054   // Transitions from OI/MI
2055
2056   transition({OI, MI}, {Other_GETX, Invalidate}, II) {
2057     q_sendDataFromTBEToCache;
2058     l_popForwardQueue;
2059   }
2060
2061   transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
2062     sq_sendSharedDataFromTBEToCache;
2063     l_popForwardQueue;
2064   }
2065
2066   transition({OI, MI}, Merged_GETS, OI) {
2067     qm_sendDataFromTBEToCache;
2068     l_popForwardQueue;
2069   }
2070
2071   transition(MI, Writeback_Ack, I) {
2072     t_sendExclusiveDataFromTBEToMemory;
2073     s_deallocateTBE;
2074     l_popForwardQueue;
2075     kd_wakeUpDependents;
2076   }
2077
2078   transition(MI_F, Writeback_Ack, I) {
2079       hh_flush_hit;
2080       t_sendExclusiveDataFromTBEToMemory;
2081       s_deallocateTBE;
2082       l_popForwardQueue;
2083       kd_wakeUpDependents;
2084   }
2085
2086   transition(OI, Writeback_Ack, I) {
2087     qq_sendDataFromTBEToMemory;
2088     s_deallocateTBE;
2089     l_popForwardQueue;
2090     kd_wakeUpDependents;
2091   }
2092
2093   // Transitions from II
2094   transition(II, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
2095     f_sendAck;
2096     l_popForwardQueue;
2097   }
2098
2099   transition(II, Writeback_Ack, I) {
2100     g_sendUnblock;
2101     s_deallocateTBE;
2102     l_popForwardQueue;
2103     kd_wakeUpDependents;
2104   }
2105
2106   transition(II, Writeback_Nack, I) {
2107     s_deallocateTBE;
2108     l_popForwardQueue;
2109     kd_wakeUpDependents;
2110   }
2111
2112   transition(MM_F, {Other_GETX, Invalidate}, IM_F) {
2113     ct_sendExclusiveDataFromTBE;
2114     pp_incrementNumberOfMessagesByOne;
2115     l_popForwardQueue;
2116   }
2117
2118   transition(MM_F, Other_GETS, IM_F) {
2119     ct_sendExclusiveDataFromTBE;
2120     pp_incrementNumberOfMessagesByOne;
2121     l_popForwardQueue;
2122   }
2123
2124   transition(MM_F, NC_DMA_GETS, OM_F) {
2125     sq_sendSharedDataFromTBEToCache;
2126     l_popForwardQueue;
2127   }
2128
2129   transition(MM_F, Other_GETS_No_Mig, OM_F) {
2130     et_sendDataSharedFromTBE;
2131     l_popForwardQueue;
2132   }
2133
2134   transition(MM_F, Merged_GETS, OM_F) {
2135     emt_sendDataSharedMultipleFromTBE;
2136     l_popForwardQueue;
2137   }
2138 }