src/mem/protocol/MOESI_hammer-dir.sm

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * AMD's contributions to the MOESI hammer protocol do not constitute an
  30  * endorsement of its similarity to any AMD products.
  31  *
  32  * Authors: Milo Martin
  33  *          Brad Beckmann
  34  */
  35
  36 machine(Directory, "AMD Hammer-like protocol")
  37 : DirectoryMemory * directory,
  38   CacheMemory * probeFilter,
  39   MemoryControl * memBuffer,
  40   int memory_controller_latency = 2,
  41   bool probe_filter_enabled = false,
  42   bool full_bit_dir_enabled = false
  43 {
  44
  45   MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false";
  46   MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false";
  47   //
  48   // For a finite buffered network, note that the DMA response network only
  49   // works at this relatively lower numbered (lower priority) virtual network
  50   // because the trigger queue decouples cache responses from DMA responses.
  51   //
  52   MessageBuffer dmaResponseFromDir, network="To", virtual_network="1", ordered="true";
  53
  54   MessageBuffer unblockToDir, network="From", virtual_network="5", ordered="false";
  55   MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false";
  56   MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false", recycle_latency="1";
  57   MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true";
  58
  59   // STATES
  60   enumeration(State, desc="Directory states", default="Directory_State_E") {
  61     // Base states
  62     NX,             desc="Not Owner, probe filter entry exists, block in O at Owner";
  63     NO,             desc="Not Owner, probe filter entry exists, block in E/M at Owner";
  64     S,              desc="Data clean, probe filter entry exists pointing to the current owner";
  65     O,              desc="Data clean, probe filter entry exists";
  66     E,              desc="Exclusive Owner, no probe filter entry";
  67
  68     O_R,            desc="Was data Owner, replacing probe filter entry";
  69     S_R,            desc="Was Not Owner or Sharer, replacing probe filter entry";
  70     NO_R,           desc="Was Not Owner or Sharer, replacing probe filter entry";
  71
  72     NO_B,  "NO^B",  desc="Not Owner, Blocked";
  73     NO_B_X,  "NO^B",  desc="Not Owner, Blocked, next queued request GETX";
  74     NO_B_S,  "NO^B",  desc="Not Owner, Blocked, next queued request GETS";
  75     NO_B_S_W,  "NO^B",  desc="Not Owner, Blocked, forwarded merged GETS, waiting for responses";
  76     O_B,   "O^B",   desc="Owner, Blocked";
  77     NO_B_W,         desc="Not Owner, Blocked, waiting for Dram";
  78     O_B_W,          desc="Owner, Blocked, waiting for Dram";
  79     NO_W,           desc="Not Owner, waiting for Dram";
  80     O_W,            desc="Owner, waiting for Dram";
  81     NO_DW_B_W,      desc="Not Owner, Dma Write waiting for Dram and cache responses";
  82     NO_DR_B_W,      desc="Not Owner, Dma Read waiting for Dram and cache responses";
  83     NO_DR_B_D,      desc="Not Owner, Dma Read waiting for cache responses including dirty data";
  84     NO_DR_B,        desc="Not Owner, Dma Read waiting for cache responses";
  85     NO_DW_W,        desc="Not Owner, Dma Write waiting for Dram";
  86     O_DR_B_W,       desc="Owner, Dma Read waiting for Dram and cache responses";
  87     O_DR_B,         desc="Owner, Dma Read waiting for cache responses";
  88     WB,             desc="Blocked on a writeback";
  89     WB_O_W,         desc="Blocked on memory write, will go to O";
  90     WB_E_W,         desc="Blocked on memory write, will go to E";
  91   }
  92
  93   // Events
  94   enumeration(Event, desc="Directory events") {
  95     GETX,                      desc="A GETX arrives";
  96     GETS,                      desc="A GETS arrives";
  97     PUT,                       desc="A PUT arrives";
  98     Unblock,                   desc="An unblock message arrives";
  99     UnblockS,                   desc="An unblock message arrives";
 100     UnblockM,                   desc="An unblock message arrives";
 101     Writeback_Clean,           desc="The final part of a PutX (no data)";
 102     Writeback_Dirty,           desc="The final part of a PutX (data)";
 103     Writeback_Exclusive_Clean, desc="The final part of a PutX (no data, exclusive)";
 104     Writeback_Exclusive_Dirty, desc="The final part of a PutX (data, exclusive)";
 105
 106     // Probe filter
 107     Pf_Replacement,            desc="probe filter replacement";
 108
 109     // DMA requests
 110     DMA_READ, desc="A DMA Read memory request";
 111     DMA_WRITE, desc="A DMA Write memory request";
 112
 113     // Memory Controller
 114     Memory_Data, desc="Fetched data from memory arrives";
 115     Memory_Ack, desc="Writeback Ack from memory arrives";
 116
 117     // Cache responses required to handle DMA
 118     Ack,             desc="Received an ack message";
 119     Shared_Ack,      desc="Received an ack message, responder has a shared copy";
 120     Shared_Data,     desc="Received a data message, responder has a shared copy";
 121     Data,            desc="Received a data message, responder had a owner or exclusive copy, they gave it to us";
 122     Exclusive_Data,  desc="Received a data message, responder had an exclusive copy, they gave it to us";
 123
 124     // Triggers
 125     All_acks_and_shared_data,     desc="Received shared data and message acks";
 126     All_acks_and_owner_data,     desc="Received shared data and message acks";
 127     All_acks_and_data_no_sharers, desc="Received all acks and no other processor has a shared copy";
 128     All_Unblocks, desc="Received all unblocks for a merged gets request";
 129   }
 130
 131   // TYPES
 132
 133   // DirectoryEntry
 134   structure(Entry, desc="...", interface="AbstractEntry") {
 135     State DirectoryState,          desc="Directory state";
 136     DataBlock DataBlk,             desc="data for the block";
 137   }
 138
 139   // ProbeFilterEntry
 140   structure(PfEntry, desc="...", interface="AbstractCacheEntry") {
 141     State PfState,                 desc="Directory state";
 142     MachineID Owner,               desc="Owner node";
 143     DataBlock DataBlk,             desc="data for the block";
 144     Set Sharers,                   desc="sharing vector for full bit directory";
 145   }
 146
 147   // TBE entries for DMA requests
 148   structure(TBE, desc="TBE entries for outstanding DMA requests") {
 149     Address PhysicalAddress, desc="physical address";
 150     State TBEState,        desc="Transient State";
 151     CoherenceResponseType ResponseType, desc="The type for the subsequent response message";
 152     int Acks, default="0", desc="The number of acks that the waiting response represents";
 153     int SilentAcks, default="0", desc="The number of silent acks associated with this transaction";
 154     DataBlock DmaDataBlk,  desc="DMA Data to be written.  Partial blocks need to merged with system memory";
 155     DataBlock DataBlk,     desc="The current view of system memory";
 156     int Len,               desc="...";
 157     MachineID DmaRequestor, desc="DMA requestor";
 158     NetDest GetSRequestors, desc="GETS merged requestors";
 159     int NumPendingMsgs,    desc="Number of pending acks/messages";
 160     bool CacheDirty, default="false", desc="Indicates whether a cache has responded with dirty data";
 161     bool Sharers, default="false", desc="Indicates whether a cache has indicated it is currently a sharer";
 162     bool Owned, default="false", desc="Indicates whether a cache has indicated it is currently a sharer";
 163   }
 164
 165   external_type(TBETable) {
 166     TBE lookup(Address);
 167     void allocate(Address);
 168     void deallocate(Address);
 169     bool isPresent(Address);
 170   }
 171
 172   void set_cache_entry(AbstractCacheEntry b);
 173   void unset_cache_entry();
 174   void set_tbe(TBE a);
 175   void unset_tbe();
 176
 177   // ** OBJECTS **
 178
 179   Set fwd_set;
 180
 181   TBETable TBEs, template_hack="<Directory_TBE>";
 182
 183   Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
 184     return static_cast(Entry, directory[addr]);
 185   }
 186
 187   PfEntry getProbeFilterEntry(Address addr), return_by_pointer="yes" {
 188     if(probe_filter_enabled) {
 189       PfEntry pfEntry := static_cast(PfEntry, "pointer", probeFilter.lookup(addr));
 190       return pfEntry;
 191     }
 192     return OOD;
 193   }
 194
 195   State getState(TBE tbe, PfEntry pf_entry, Address addr) {
 196     if (is_valid(tbe)) {
 197       return tbe.TBEState;
 198     } else {
 199       if (probe_filter_enabled || full_bit_dir_enabled) {
 200         if (is_valid(pf_entry)) {
 201           assert(pf_entry.PfState == getDirectoryEntry(addr).DirectoryState);
 202         } else {
 203           assert(getDirectoryEntry(addr).DirectoryState == State:E);
 204         }
 205       }
 206       return getDirectoryEntry(addr).DirectoryState;
 207     }
 208   }
 209
 210   void setState(TBE tbe, PfEntry pf_entry, Address addr, State state) {
 211     if (is_valid(tbe)) {
 212       tbe.TBEState := state;
 213     }
 214     if (probe_filter_enabled || full_bit_dir_enabled) {
 215       if (is_valid(pf_entry)) {
 216         pf_entry.PfState := state;
 217       }
 218       if (state == State:NX || state == State:NO || state == State:S || state == State:O) {
 219         assert(is_valid(pf_entry));
 220       }
 221     }
 222     if (state == State:E || state == State:NX || state == State:NO || state == State:S ||
 223         state == State:O) {
 224       assert(is_valid(tbe) == false);
 225     }
 226     getDirectoryEntry(addr).DirectoryState := state;
 227   }
 228
 229   Event cache_request_to_event(CoherenceRequestType type) {
 230     if (type == CoherenceRequestType:GETS) {
 231       return Event:GETS;
 232     } else if (type == CoherenceRequestType:GETX) {
 233       return Event:GETX;
 234     } else {
 235       error("Invalid CoherenceRequestType");
 236     }
 237   }
 238
 239   MessageBuffer triggerQueue, ordered="true";
 240
 241   // ** OUT_PORTS **
 242   out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
 243   out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
 244   out_port(responseNetwork_out, ResponseMsg, responseFromDir);
 245   out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
 246   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 247
 248   //
 249   // Memory buffer for memory controller to DIMM communication
 250   //
 251   out_port(memQueue_out, MemoryMsg, memBuffer);
 252
 253   // ** IN_PORTS **
 254
 255   // Trigger Queue
 256   in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=5) {
 257     if (triggerQueue_in.isReady()) {
 258       peek(triggerQueue_in, TriggerMsg) {
 259         PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
 260         TBE tbe := TBEs[in_msg.Address];
 261         if (in_msg.Type == TriggerType:ALL_ACKS) {
 262           trigger(Event:All_acks_and_owner_data, in_msg.Address,
 263                   pf_entry, tbe);
 264         } else if (in_msg.Type == TriggerType:ALL_ACKS_OWNER_EXISTS) {
 265           trigger(Event:All_acks_and_shared_data, in_msg.Address,
 266                   pf_entry, tbe);
 267         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
 268           trigger(Event:All_acks_and_data_no_sharers, in_msg.Address,
 269                   pf_entry, tbe);
 270         } else if (in_msg.Type == TriggerType:ALL_UNBLOCKS) {
 271           trigger(Event:All_Unblocks, in_msg.Address,
 272                   pf_entry, tbe);
 273         } else {
 274           error("Unexpected message");
 275         }
 276       }
 277     }
 278   }
 279
 280   in_port(unblockNetwork_in, ResponseMsg, unblockToDir, rank=4) {
 281     if (unblockNetwork_in.isReady()) {
 282       peek(unblockNetwork_in, ResponseMsg) {
 283         PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
 284         TBE tbe := TBEs[in_msg.Address];
 285         if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
 286           trigger(Event:Unblock, in_msg.Address, pf_entry, tbe);
 287         } else if (in_msg.Type == CoherenceResponseType:UNBLOCKS) {
 288           trigger(Event:UnblockS, in_msg.Address, pf_entry, tbe);
 289         } else if (in_msg.Type == CoherenceResponseType:UNBLOCKM) {
 290           trigger(Event:UnblockM, in_msg.Address, pf_entry, tbe);
 291         } else if (in_msg.Type == CoherenceResponseType:WB_CLEAN) {
 292           trigger(Event:Writeback_Clean, in_msg.Address, pf_entry, tbe);
 293         } else if (in_msg.Type == CoherenceResponseType:WB_DIRTY) {
 294           trigger(Event:Writeback_Dirty, in_msg.Address, pf_entry, tbe);
 295         } else if (in_msg.Type == CoherenceResponseType:WB_EXCLUSIVE_CLEAN) {
 296           trigger(Event:Writeback_Exclusive_Clean, in_msg.Address,
 297                   pf_entry, tbe);
 298         } else if (in_msg.Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) {
 299           trigger(Event:Writeback_Exclusive_Dirty, in_msg.Address,
 300                   pf_entry, tbe);
 301         } else {
 302           error("Invalid message");
 303         }
 304       }
 305     }
 306   }
 307
 308   // Response Network
 309   in_port(responseToDir_in, ResponseMsg, responseToDir, rank=3) {
 310     if (responseToDir_in.isReady()) {
 311       peek(responseToDir_in, ResponseMsg) {
 312         PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
 313         TBE tbe := TBEs[in_msg.Address];
 314         if (in_msg.Type == CoherenceResponseType:ACK) {
 315           trigger(Event:Ack, in_msg.Address, pf_entry, tbe);
 316         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
 317           trigger(Event:Shared_Ack, in_msg.Address, pf_entry, tbe);
 318         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
 319           trigger(Event:Shared_Data, in_msg.Address, pf_entry, tbe);
 320         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 321           trigger(Event:Data, in_msg.Address, pf_entry, tbe);
 322         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 323           trigger(Event:Exclusive_Data, in_msg.Address, pf_entry, tbe);
 324         } else {
 325           error("Unexpected message");
 326         }
 327       }
 328     }
 329   }
 330
 331   // off-chip memory request/response is done
 332   in_port(memQueue_in, MemoryMsg, memBuffer, rank=2) {
 333     if (memQueue_in.isReady()) {
 334       peek(memQueue_in, MemoryMsg) {
 335         PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
 336         TBE tbe := TBEs[in_msg.Address];
 337         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
 338           trigger(Event:Memory_Data, in_msg.Address, pf_entry, tbe);
 339         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
 340           trigger(Event:Memory_Ack, in_msg.Address, pf_entry, tbe);
 341         } else {
 342           DPRINTF(RubySlicc, "%d\n", in_msg.Type);
 343           error("Invalid message");
 344         }
 345       }
 346     }
 347   }
 348
 349   in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
 350     if (requestQueue_in.isReady()) {
 351       peek(requestQueue_in, RequestMsg) {
 352         PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
 353         TBE tbe := TBEs[in_msg.Address];
 354         if (in_msg.Type == CoherenceRequestType:PUT) {
 355           trigger(Event:PUT, in_msg.Address, pf_entry, tbe);
 356         } else {
 357           if (probe_filter_enabled || full_bit_dir_enabled) {
 358             if (is_valid(pf_entry)) {
 359               trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
 360                       pf_entry, tbe);
 361             } else {
 362               if (probeFilter.cacheAvail(in_msg.Address)) {
 363                 trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
 364                         pf_entry, tbe);
 365               } else {
 366                 trigger(Event:Pf_Replacement,
 367                         probeFilter.cacheProbe(in_msg.Address),
 368                         getProbeFilterEntry(probeFilter.cacheProbe(in_msg.Address)),
 369                         TBEs[probeFilter.cacheProbe(in_msg.Address)]);
 370               }
 371             }
 372           } else {
 373             trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
 374                     pf_entry, tbe);
 375           }
 376         }
 377       }
 378     }
 379   }
 380
 381   in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir, rank=0) {
 382     if (dmaRequestQueue_in.isReady()) {
 383       peek(dmaRequestQueue_in, DMARequestMsg) {
 384         PfEntry pf_entry := getProbeFilterEntry(in_msg.LineAddress);
 385         TBE tbe := TBEs[in_msg.LineAddress];
 386         if (in_msg.Type == DMARequestType:READ) {
 387           trigger(Event:DMA_READ, in_msg.LineAddress, pf_entry, tbe);
 388         } else if (in_msg.Type == DMARequestType:WRITE) {
 389           trigger(Event:DMA_WRITE, in_msg.LineAddress, pf_entry, tbe);
 390         } else {
 391           error("Invalid message");
 392         }
 393       }
 394     }
 395   }
 396
 397   // Actions
 398
 399   action(r_setMRU, "\rr", desc="manually set the MRU bit for pf entry" ) {
 400     if (probe_filter_enabled || full_bit_dir_enabled) {
 401       assert(is_valid(cache_entry));
 402       probeFilter.setMRU(address);
 403     }
 404   }
 405
 406   action(auno_assertUnblockerNotOwner, "auno", desc="assert unblocker not owner") {
 407     if (probe_filter_enabled || full_bit_dir_enabled) {
 408       assert(is_valid(cache_entry));
 409       peek(unblockNetwork_in, ResponseMsg) {
 410         assert(cache_entry.Owner != in_msg.Sender);
 411         if (full_bit_dir_enabled) {
 412           assert(cache_entry.Sharers.isElement(machineIDToNodeID(in_msg.Sender)) == false);
 413         }
 414       }
 415     }
 416   }
 417
 418   action(uo_updateOwnerIfPf, "uo", desc="update owner") {
 419     if (probe_filter_enabled || full_bit_dir_enabled) {
 420       assert(is_valid(cache_entry));
 421       peek(unblockNetwork_in, ResponseMsg) {
 422         cache_entry.Owner := in_msg.Sender;
 423         if (full_bit_dir_enabled) {
 424           cache_entry.Sharers.clear();
 425           cache_entry.Sharers.add(machineIDToNodeID(in_msg.Sender));
 426           APPEND_TRANSITION_COMMENT(cache_entry.Sharers);
 427           DPRINTF(RubySlicc, "Sharers = %d\n", cache_entry.Sharers);
 428         }
 429       }
 430     }
 431   }
 432
 433   action(us_updateSharerIfFBD, "us", desc="update sharer if full-bit directory") {
 434    if (full_bit_dir_enabled) {
 435       assert(probeFilter.isTagPresent(address));
 436       peek(unblockNetwork_in, ResponseMsg) {
 437         cache_entry.Sharers.add(machineIDToNodeID(in_msg.Sender));
 438       }
 439     }
 440   }
 441
 442   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
 443     peek(requestQueue_in, RequestMsg) {
 444       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 445         out_msg.Address := address;
 446         out_msg.Type := CoherenceRequestType:WB_ACK;
 447         out_msg.Requestor := in_msg.Requestor;
 448         out_msg.Destination.add(in_msg.Requestor);
 449         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 450       }
 451     }
 452   }
 453
 454   action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
 455     peek(requestQueue_in, RequestMsg) {
 456       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 457         out_msg.Address := address;
 458         out_msg.Type := CoherenceRequestType:WB_NACK;
 459         out_msg.Requestor := in_msg.Requestor;
 460         out_msg.Destination.add(in_msg.Requestor);
 461         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 462       }
 463     }
 464   }
 465
 466   action(pfa_probeFilterAllocate, "pfa", desc="Allocate ProbeFilterEntry") {
 467     if (probe_filter_enabled || full_bit_dir_enabled) {
 468       peek(requestQueue_in, RequestMsg) {
 469         set_cache_entry(probeFilter.allocate(address, new PfEntry));
 470         cache_entry.Owner := in_msg.Requestor;
 471       }
 472     }
 473   }
 474
 475   action(pfd_probeFilterDeallocate, "pfd", desc="Deallocate ProbeFilterEntry") {
 476     if (probe_filter_enabled || full_bit_dir_enabled) {
 477       probeFilter.deallocate(address);
 478       unset_cache_entry();
 479     }
 480   }
 481
 482   action(ppfd_possibleProbeFilterDeallocate, "ppfd", desc="Deallocate ProbeFilterEntry") {
 483     if ((probe_filter_enabled || full_bit_dir_enabled) && is_valid(cache_entry)) {
 484       probeFilter.deallocate(address);
 485       unset_cache_entry();
 486     }
 487   }
 488
 489   action(v_allocateTBE, "v", desc="Allocate TBE") {
 490     peek(requestQueue_in, RequestMsg) {
 491       TBEs.allocate(address);
 492       set_tbe(TBEs[address]);
 493       tbe.PhysicalAddress := address;
 494       tbe.ResponseType := CoherenceResponseType:NULL;
 495     }
 496   }
 497
 498   action(vd_allocateDmaRequestInTBE, "vd", desc="Record Data in TBE") {
 499     peek(dmaRequestQueue_in, DMARequestMsg) {
 500       TBEs.allocate(address);
 501       set_tbe(TBEs[address]);
 502       tbe.DmaDataBlk := in_msg.DataBlk;
 503       tbe.PhysicalAddress := in_msg.PhysicalAddress;
 504       tbe.Len := in_msg.Len;
 505       tbe.DmaRequestor := in_msg.Requestor;
 506       tbe.ResponseType := CoherenceResponseType:DATA_EXCLUSIVE;
 507       //
 508       // One ack for each last-level cache
 509       //
 510       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
 511       //
 512       // Assume initially that the caches store a clean copy and that memory
 513       // will provide the data
 514       //
 515       tbe.CacheDirty := false;
 516     }
 517   }
 518
 519   action(pa_setPendingMsgsToAll, "pa", desc="set pending msgs to all") {
 520     assert(is_valid(tbe));
 521     if (full_bit_dir_enabled) {
 522       assert(is_valid(cache_entry));
 523       tbe.NumPendingMsgs := cache_entry.Sharers.count();
 524     } else {
 525       tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
 526     }
 527   }
 528
 529   action(po_setPendingMsgsToOne, "po", desc="set pending msgs to one") {
 530     assert(is_valid(tbe));
 531     tbe.NumPendingMsgs := 1;
 532   }
 533
 534   action(w_deallocateTBE, "w", desc="Deallocate TBE") {
 535     TBEs.deallocate(address);
 536     unset_tbe();
 537   }
 538
 539   action(sa_setAcksToOne, "sa", desc="Forwarded request, set the ack amount to one") {
 540     assert(is_valid(tbe));
 541     peek(requestQueue_in, RequestMsg) {
 542       if (full_bit_dir_enabled) {
 543         assert(is_valid(cache_entry));
 544         //
 545         // If we are using the full-bit directory and no sharers exists beyond
 546         // the requestor, then we must set the ack number to all, not one
 547         //
 548         fwd_set := cache_entry.Sharers;
 549         fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
 550         if (fwd_set.count() > 0) {
 551           tbe.Acks := 1;
 552           tbe.SilentAcks := machineCount(MachineType:L1Cache) - fwd_set.count();
 553           tbe.SilentAcks := tbe.SilentAcks - 1;
 554         } else {
 555           tbe.Acks := machineCount(MachineType:L1Cache);
 556           tbe.SilentAcks := 0;
 557         }
 558       } else {
 559         tbe.Acks := 1;
 560       }
 561     }
 562   }
 563
 564   action(saa_setAcksToAllIfPF, "saa", desc="Non-forwarded request, set the ack amount to all") {
 565     assert(is_valid(tbe));
 566     if (probe_filter_enabled || full_bit_dir_enabled) {
 567       tbe.Acks := machineCount(MachineType:L1Cache);
 568       tbe.SilentAcks := 0;
 569     } else {
 570       tbe.Acks := 1;
 571     }
 572   }
 573
 574   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 575     peek(responseToDir_in, ResponseMsg) {
 576       assert(is_valid(tbe));
 577       assert(in_msg.Acks > 0);
 578       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 579       //
 580       // Note that cache data responses will have an ack count of 2.  However,
 581       // directory DMA requests must wait for acks from all LLC caches, so
 582       // only decrement by 1.
 583       //
 584       tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
 585       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 586     }
 587   }
 588
 589   action(mu_decrementNumberOfUnblocks, "mu", desc="Decrement the number of messages for which we're waiting") {
 590     peek(unblockNetwork_in, ResponseMsg) {
 591       assert(is_valid(tbe));
 592       assert(in_msg.Type == CoherenceResponseType:UNBLOCKS);
 593       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 594       //
 595       // Note that cache data responses will have an ack count of 2.  However,
 596       // directory DMA requests must wait for acks from all LLC caches, so
 597       // only decrement by 1.
 598       //
 599       tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
 600       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
 601     }
 602   }
 603
 604   action(n_popResponseQueue, "n", desc="Pop response queue") {
 605     responseToDir_in.dequeue();
 606   }
 607
 608   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 609     assert(is_valid(tbe));
 610     if (tbe.NumPendingMsgs == 0) {
 611       enqueue(triggerQueue_out, TriggerMsg) {
 612         out_msg.Address := address;
 613         if (tbe.Sharers) {
 614           if (tbe.Owned) {
 615             out_msg.Type := TriggerType:ALL_ACKS_OWNER_EXISTS;
 616           } else {
 617             out_msg.Type := TriggerType:ALL_ACKS;
 618           }
 619         } else {
 620           out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
 621         }
 622       }
 623     }
 624   }
 625
 626   action(os_checkForMergedGetSCompletion, "os", desc="Check for merged GETS completion") {
 627     assert(is_valid(tbe));
 628     if (tbe.NumPendingMsgs == 0) {
 629       enqueue(triggerQueue_out, TriggerMsg) {
 630         out_msg.Address := address;
 631         out_msg.Type := TriggerType:ALL_UNBLOCKS;
 632       }
 633     }
 634   }
 635
 636   action(sp_setPendingMsgsToMergedSharers, "sp", desc="Set pending messages to waiting sharers") {
 637     assert(is_valid(tbe));
 638     tbe.NumPendingMsgs := tbe.GetSRequestors.count();
 639   }
 640
 641   action(spa_setPendingAcksToZeroIfPF, "spa", desc="if probe filter, no need to wait for acks") {
 642     if (probe_filter_enabled || full_bit_dir_enabled) {
 643       assert(is_valid(tbe));
 644       tbe.NumPendingMsgs := 0;
 645     }
 646   }
 647
 648   action(sc_signalCompletionIfPF, "sc", desc="indicate that we should skip waiting for cpu acks") {
 649     assert(is_valid(tbe));
 650     if (tbe.NumPendingMsgs == 0) {
 651       assert(probe_filter_enabled || full_bit_dir_enabled);
 652       enqueue(triggerQueue_out, TriggerMsg) {
 653         out_msg.Address := address;
 654         out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
 655       }
 656     }
 657   }
 658
 659   action(d_sendData, "d", desc="Send data to requestor") {
 660     peek(memQueue_in, MemoryMsg) {
 661       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 662         assert(is_valid(tbe));
 663         out_msg.Address := address;
 664         out_msg.Type := tbe.ResponseType;
 665         out_msg.Sender := machineID;
 666         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
 667         out_msg.DataBlk := in_msg.DataBlk;
 668         DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
 669         out_msg.Dirty := false; // By definition, the block is now clean
 670         out_msg.Acks := tbe.Acks;
 671         out_msg.SilentAcks := tbe.SilentAcks;
 672         DPRINTF(RubySlicc, "%d\n", out_msg.Acks);
 673         assert(out_msg.Acks > 0);
 674         out_msg.MessageSize := MessageSizeType:Response_Data;
 675       }
 676     }
 677   }
 678
 679   action(dr_sendDmaData, "dr", desc="Send Data to DMA controller from memory") {
 680     peek(memQueue_in, MemoryMsg) {
 681       enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
 682         assert(is_valid(tbe));
 683         out_msg.PhysicalAddress := address;
 684         out_msg.LineAddress := address;
 685         out_msg.Type := DMAResponseType:DATA;
 686         //
 687         // we send the entire data block and rely on the dma controller to
 688         // split it up if need be
 689         //
 690         out_msg.DataBlk := in_msg.DataBlk;
 691         out_msg.Destination.add(tbe.DmaRequestor);
 692         out_msg.MessageSize := MessageSizeType:Response_Data;
 693       }
 694     }
 695   }
 696
 697   action(dt_sendDmaDataFromTbe, "dt", desc="Send Data to DMA controller from tbe") {
 698     peek(triggerQueue_in, TriggerMsg) {
 699       enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
 700         assert(is_valid(tbe));
 701         out_msg.PhysicalAddress := address;
 702         out_msg.LineAddress := address;
 703         out_msg.Type := DMAResponseType:DATA;
 704         //
 705         // we send the entire data block and rely on the dma controller to
 706         // split it up if need be
 707         //
 708         out_msg.DataBlk := tbe.DataBlk;
 709         out_msg.Destination.add(tbe.DmaRequestor);
 710         out_msg.MessageSize := MessageSizeType:Response_Data;
 711       }
 712     }
 713   }
 714
 715   action(da_sendDmaAck, "da", desc="Send Ack to DMA controller") {
 716     enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
 717       assert(is_valid(tbe));
 718       out_msg.PhysicalAddress := address;
 719       out_msg.LineAddress := address;
 720       out_msg.Type := DMAResponseType:ACK;
 721       out_msg.Destination.add(tbe.DmaRequestor);
 722       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 723     }
 724   }
 725
 726   action(rx_recordExclusiveInTBE, "rx", desc="Record Exclusive in TBE") {
 727     peek(requestQueue_in, RequestMsg) {
 728       assert(is_valid(tbe));
 729       tbe.ResponseType := CoherenceResponseType:DATA_EXCLUSIVE;
 730     }
 731   }
 732
 733   action(r_recordDataInTBE, "rt", desc="Record Data in TBE") {
 734     peek(requestQueue_in, RequestMsg) {
 735       assert(is_valid(tbe));
 736       if (full_bit_dir_enabled) {
 737         fwd_set := cache_entry.Sharers;
 738         fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
 739         if (fwd_set.count() > 0) {
 740           tbe.ResponseType := CoherenceResponseType:DATA;
 741         } else {
 742           tbe.ResponseType := CoherenceResponseType:DATA_EXCLUSIVE;
 743         }
 744       } else {
 745         tbe.ResponseType := CoherenceResponseType:DATA;
 746       }
 747     }
 748   }
 749
 750   action(rs_recordGetSRequestor, "rs", desc="Record GETS requestor in TBE") {
 751     peek(requestQueue_in, RequestMsg) {
 752       assert(is_valid(tbe));
 753       tbe.GetSRequestors.add(in_msg.Requestor);
 754     }
 755   }
 756
 757   action(r_setSharerBit, "r", desc="We saw other sharers") {
 758     assert(is_valid(tbe));
 759     tbe.Sharers := true;
 760   }
 761
 762   action(so_setOwnerBit, "so", desc="We saw other sharers") {
 763     assert(is_valid(tbe));
 764     tbe.Sharers := true;
 765     tbe.Owned := true;
 766   }
 767
 768   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
 769     peek(requestQueue_in, RequestMsg) {
 770       enqueue(memQueue_out, MemoryMsg, latency="1") {
 771         out_msg.Address := address;
 772         out_msg.Type := MemoryRequestType:MEMORY_READ;
 773         out_msg.Sender := machineID;
 774         out_msg.OriginalRequestorMachId := in_msg.Requestor;
 775         out_msg.MessageSize := in_msg.MessageSize;
 776         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
 777         DPRINTF(RubySlicc, "%s\n", out_msg);
 778       }
 779     }
 780   }
 781
 782   action(qd_queueMemoryRequestFromDmaRead, "qd", desc="Queue off-chip fetch request") {
 783     peek(dmaRequestQueue_in, DMARequestMsg) {
 784       enqueue(memQueue_out, MemoryMsg, latency="1") {
 785         out_msg.Address := address;
 786         out_msg.Type := MemoryRequestType:MEMORY_READ;
 787         out_msg.Sender := machineID;
 788         out_msg.OriginalRequestorMachId := in_msg.Requestor;
 789         out_msg.MessageSize := in_msg.MessageSize;
 790         out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
 791         DPRINTF(RubySlicc, "%s\n", out_msg);
 792       }
 793     }
 794   }
 795
 796   action(fn_forwardRequestIfNecessary, "fn", desc="Forward requests if necessary") {
 797     assert(is_valid(tbe));
 798     if ((machineCount(MachineType:L1Cache) > 1) && (tbe.Acks <= 1)) {
 799       if (full_bit_dir_enabled) {
 800         assert(is_valid(cache_entry));
 801         peek(requestQueue_in, RequestMsg) {
 802           fwd_set := cache_entry.Sharers;
 803           fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
 804           if (fwd_set.count() > 0) {
 805             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 806               out_msg.Address := address;
 807               out_msg.Type := in_msg.Type;
 808               out_msg.Requestor := in_msg.Requestor;
 809               out_msg.Destination.setNetDest(MachineType:L1Cache, fwd_set);
 810               out_msg.MessageSize := MessageSizeType:Multicast_Control;
 811               out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 812               out_msg.ForwardRequestTime := get_time();
 813               assert(tbe.SilentAcks > 0);
 814               out_msg.SilentAcks := tbe.SilentAcks;
 815             }
 816           }
 817         }
 818       } else {
 819         peek(requestQueue_in, RequestMsg) {
 820           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 821             out_msg.Address := address;
 822             out_msg.Type := in_msg.Type;
 823             out_msg.Requestor := in_msg.Requestor;
 824             out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
 825             out_msg.Destination.remove(in_msg.Requestor); // Don't include the original requestor
 826             out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 827             out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 828             out_msg.ForwardRequestTime := get_time();
 829           }
 830         }
 831       }
 832     }
 833   }
 834
 835   action(ia_invalidateAllRequest, "ia", desc="invalidate all copies") {
 836     if (machineCount(MachineType:L1Cache) > 1) {
 837       if (full_bit_dir_enabled) {
 838         assert(cache_entry.Sharers.count() > 0);
 839         peek(requestQueue_in, RequestMsg) {
 840           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 841             out_msg.Address := address;
 842             out_msg.Type := CoherenceRequestType:INV;
 843             out_msg.Requestor := machineID;
 844             out_msg.Destination.setNetDest(MachineType:L1Cache, cache_entry.Sharers);
 845             out_msg.MessageSize := MessageSizeType:Multicast_Control;
 846           }
 847         }
 848       } else {
 849         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 850           out_msg.Address := address;
 851           out_msg.Type := CoherenceRequestType:INV;
 852           out_msg.Requestor := machineID;
 853           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
 854           out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 855         }
 856       }
 857     }
 858   }
 859
 860   action(io_invalidateOwnerRequest, "io", desc="invalidate all copies") {
 861     if (machineCount(MachineType:L1Cache) > 1) {
 862       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 863         assert(is_valid(cache_entry));
 864         out_msg.Address := address;
 865         out_msg.Type := CoherenceRequestType:INV;
 866         out_msg.Requestor := machineID;
 867         out_msg.Destination.add(cache_entry.Owner);
 868         out_msg.MessageSize := MessageSizeType:Request_Control;
 869         out_msg.DirectedProbe := true;
 870       }
 871     }
 872   }
 873
 874   action(fb_forwardRequestBcast, "fb", desc="Forward requests to all nodes") {
 875     if (machineCount(MachineType:L1Cache) > 1) {
 876       peek(requestQueue_in, RequestMsg) {
 877         if (full_bit_dir_enabled) {
 878           fwd_set := cache_entry.Sharers;
 879           fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
 880           if (fwd_set.count() > 0) {
 881             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 882                   out_msg.Address := address;
 883                   out_msg.Type := in_msg.Type;
 884                   out_msg.Requestor := in_msg.Requestor;
 885                   out_msg.Destination.setNetDest(MachineType:L1Cache, fwd_set);
 886                   out_msg.MessageSize := MessageSizeType:Multicast_Control;
 887                   out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 888                   out_msg.ForwardRequestTime := get_time();
 889                   out_msg.SilentAcks := machineCount(MachineType:L1Cache) - fwd_set.count();
 890                   out_msg.SilentAcks := out_msg.SilentAcks - 1;
 891               }
 892           }
 893         } else {
 894             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 895                 out_msg.Address := address;
 896                 out_msg.Type := in_msg.Type;
 897                 out_msg.Requestor := in_msg.Requestor;
 898                 out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
 899                 out_msg.Destination.remove(in_msg.Requestor); // Don't include the original requestor
 900                 out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 901                 out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 902                 out_msg.ForwardRequestTime := get_time();
 903             }
 904         }
 905       }
 906     }
 907   }
 908
 909   action(fr_forwardMergeReadRequestsToOwner, "frr", desc="Forward coalesced read request to owner") {
 910     assert(machineCount(MachineType:L1Cache) > 1);
 911     //
 912     // Fixme! The unblock network should not stall on the forward network.  Add a trigger queue to
 913     // decouple the two.
 914     //
 915     peek(unblockNetwork_in, ResponseMsg) {
 916       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 917         assert(is_valid(tbe));
 918         out_msg.Address := address;
 919         out_msg.Type := CoherenceRequestType:MERGED_GETS;
 920         out_msg.MergedRequestors := tbe.GetSRequestors;
 921         if (in_msg.Type == CoherenceResponseType:UNBLOCKS) {
 922           out_msg.Destination.add(in_msg.CurOwner);
 923         } else {
 924           out_msg.Destination.add(in_msg.Sender);
 925         }
 926         out_msg.MessageSize := MessageSizeType:Request_Control;
 927         out_msg.InitialRequestTime := zero_time();
 928         out_msg.ForwardRequestTime := get_time();
 929       }
 930     }
 931   }
 932
 933   action(fc_forwardRequestConditionalOwner, "fc", desc="Forward request to one or more nodes") {
 934     assert(machineCount(MachineType:L1Cache) > 1);
 935     if (probe_filter_enabled || full_bit_dir_enabled) {
 936       peek(requestQueue_in, RequestMsg) {
 937         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 938           assert(is_valid(cache_entry));
 939           out_msg.Address := address;
 940           out_msg.Type := in_msg.Type;
 941           out_msg.Requestor := in_msg.Requestor;
 942           out_msg.Destination.add(cache_entry.Owner);
 943           out_msg.MessageSize := MessageSizeType:Request_Control;
 944           out_msg.DirectedProbe := true;
 945           out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 946           out_msg.ForwardRequestTime := get_time();
 947         }
 948       }
 949     } else {
 950       peek(requestQueue_in, RequestMsg) {
 951         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 952           out_msg.Address := address;
 953           out_msg.Type := in_msg.Type;
 954           out_msg.Requestor := in_msg.Requestor;
 955           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
 956           out_msg.Destination.remove(in_msg.Requestor); // Don't include the original requestor
 957           out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 958           out_msg.InitialRequestTime := in_msg.InitialRequestTime;
 959           out_msg.ForwardRequestTime := get_time();
 960         }
 961       }
 962     }
 963   }
 964
 965   action(f_forwardWriteFromDma, "fw", desc="Forward requests") {
 966     assert(is_valid(tbe));
 967     if (tbe.NumPendingMsgs > 0) {
 968       peek(dmaRequestQueue_in, DMARequestMsg) {
 969         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 970           out_msg.Address := address;
 971           out_msg.Type := CoherenceRequestType:GETX;
 972           //
 973           // Send to all L1 caches, since the requestor is the memory controller
 974           // itself
 975           //
 976           out_msg.Requestor := machineID;
 977           out_msg.Destination.broadcast(MachineType:L1Cache);
 978           out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 979         }
 980       }
 981     }
 982   }
 983
 984   action(f_forwardReadFromDma, "fr", desc="Forward requests") {
 985     assert(is_valid(tbe));
 986     if (tbe.NumPendingMsgs > 0) {
 987       peek(dmaRequestQueue_in, DMARequestMsg) {
 988         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
 989           out_msg.Address := address;
 990           out_msg.Type := CoherenceRequestType:GETS;
 991           //
 992           // Send to all L1 caches, since the requestor is the memory controller
 993           // itself
 994           //
 995           out_msg.Requestor := machineID;
 996           out_msg.Destination.broadcast(MachineType:L1Cache);
 997           out_msg.MessageSize := MessageSizeType:Broadcast_Control;
 998         }
 999       }
1000     }
1001   }
1002
1003   action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
1004     requestQueue_in.dequeue();
1005   }
1006
1007   action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") {
1008     peek(unblockNetwork_in, ResponseMsg) {
1009         APPEND_TRANSITION_COMMENT(in_msg.Sender);
1010     }
1011     unblockNetwork_in.dequeue();
1012   }
1013
1014   action(k_wakeUpDependents, "k", desc="wake-up dependents") {
1015     wake_up_dependents(address);
1016   }
1017
1018   action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
1019     memQueue_in.dequeue();
1020   }
1021
1022   action(g_popTriggerQueue, "g", desc="Pop trigger queue") {
1023     triggerQueue_in.dequeue();
1024   }
1025
1026   action(p_popDmaRequestQueue, "pd", desc="pop dma request queue") {
1027     dmaRequestQueue_in.dequeue();
1028   }
1029
1030   action(zd_stallAndWaitDMARequest, "zd", desc="Stall and wait the dma request queue") {
1031     peek(dmaRequestQueue_in, DMARequestMsg) {
1032         APPEND_TRANSITION_COMMENT(in_msg.Requestor);
1033     }
1034     stall_and_wait(dmaRequestQueue_in, address);
1035   }
1036
1037   action(r_recordMemoryData, "rd", desc="record data from memory to TBE") {
1038     peek(memQueue_in, MemoryMsg) {
1039       assert(is_valid(tbe));
1040       if (tbe.CacheDirty == false) {
1041         tbe.DataBlk := in_msg.DataBlk;
1042       }
1043     }
1044   }
1045
1046   action(r_recordCacheData, "rc", desc="record data from cache response to TBE") {
1047     peek(responseToDir_in, ResponseMsg) {
1048       assert(is_valid(tbe));
1049       tbe.CacheDirty := true;
1050       tbe.DataBlk := in_msg.DataBlk;
1051     }
1052   }
1053
1054   action(wr_writeResponseDataToMemory, "wr", desc="Write response data to memory") {
1055     peek(responseToDir_in, ResponseMsg) {
1056       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
1057       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1058               in_msg.Address, in_msg.DataBlk);
1059     }
1060   }
1061
1062   action(l_writeDataToMemory, "l", desc="Write PUTX/PUTO data to memory") {
1063     peek(unblockNetwork_in, ResponseMsg) {
1064       assert(in_msg.Dirty);
1065       assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
1066       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
1067       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
1068               in_msg.Address, in_msg.DataBlk);
1069     }
1070   }
1071
1072   action(dwt_writeDmaDataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
1073     DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
1074     assert(is_valid(tbe));
1075     getDirectoryEntry(address).DataBlk := tbe.DataBlk;
1076     DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
1077     getDirectoryEntry(address).DataBlk.copyPartial(tbe.DmaDataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
1078     DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
1079   }
1080
1081   action(wdt_writeDataFromTBE, "wdt", desc="DMA Write data to memory from TBE") {
1082     assert(is_valid(tbe));
1083     DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
1084     getDirectoryEntry(address).DataBlk := tbe.DataBlk;
1085     DPRINTF(RubySlicc, "%s\n", getDirectoryEntry(address).DataBlk);
1086   }
1087
1088   action(a_assertCacheData, "ac", desc="Assert that a cache provided the data") {
1089     assert(is_valid(tbe));
1090     assert(tbe.CacheDirty);
1091   }
1092
1093   action(ano_assertNotOwner, "ano", desc="Assert that request is not current owner") {
1094     if (probe_filter_enabled || full_bit_dir_enabled) {
1095       peek(requestQueue_in, RequestMsg) {
1096         assert(is_valid(cache_entry));
1097         assert(cache_entry.Owner != in_msg.Requestor);
1098       }
1099     }
1100   }
1101
1102   action(ans_assertNotSharer, "ans", desc="Assert that request is not a current sharer") {
1103     if (full_bit_dir_enabled) {
1104       peek(requestQueue_in, RequestMsg) {
1105         assert(cache_entry.Sharers.isElement(machineIDToNodeID(in_msg.Requestor)) == false);
1106       }
1107     }
1108   }
1109
1110   action(rs_removeSharer, "s", desc="remove current sharer") {
1111     if (full_bit_dir_enabled) {
1112       peek(unblockNetwork_in, ResponseMsg) {
1113         assert(cache_entry.Sharers.isElement(machineIDToNodeID(in_msg.Sender)));
1114         cache_entry.Sharers.remove(machineIDToNodeID(in_msg.Sender));
1115       }
1116     }
1117   }
1118
1119   action(cs_clearSharers, "cs", desc="clear current sharers") {
1120     if (full_bit_dir_enabled) {
1121       peek(requestQueue_in, RequestMsg) {
1122         cache_entry.Sharers.clear();
1123         cache_entry.Sharers.add(machineIDToNodeID(in_msg.Requestor));
1124       }
1125     }
1126   }
1127
1128   action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
1129     peek(unblockNetwork_in, ResponseMsg) {
1130       enqueue(memQueue_out, MemoryMsg, latency="1") {
1131         out_msg.Address := address;
1132         out_msg.Type := MemoryRequestType:MEMORY_WB;
1133         DPRINTF(RubySlicc, "%s\n", out_msg);
1134       }
1135     }
1136   }
1137
1138   action(ld_queueMemoryDmaWrite, "ld", desc="Write DMA data to memory") {
1139     enqueue(memQueue_out, MemoryMsg, latency="1") {
1140       assert(is_valid(tbe));
1141       out_msg.Address := address;
1142       out_msg.Type := MemoryRequestType:MEMORY_WB;
1143       // first, initialize the data blk to the current version of system memory
1144       out_msg.DataBlk := tbe.DataBlk;
1145       // then add the dma write data
1146       out_msg.DataBlk.copyPartial(tbe.DmaDataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
1147       DPRINTF(RubySlicc, "%s\n", out_msg);
1148     }
1149   }
1150
1151   action(ll_checkIncomingWriteback, "\l", desc="Check PUTX/PUTO response message") {
1152     peek(unblockNetwork_in, ResponseMsg) {
1153       assert(in_msg.Dirty == false);
1154       assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
1155
1156       // NOTE: The following check would not be valid in a real
1157       // implementation.  We include the data in the "dataless"
1158       // message so we can assert the clean data matches the datablock
1159       // in memory
1160       assert(getDirectoryEntry(address).DataBlk == in_msg.DataBlk);
1161     }
1162   }
1163
1164   action(z_stallAndWaitRequest, "z", desc="Recycle the request queue") {
1165     peek(requestQueue_in, RequestMsg) {
1166         APPEND_TRANSITION_COMMENT(in_msg.Requestor);
1167     }
1168     stall_and_wait(requestQueue_in, address);
1169   }
1170
1171   // TRANSITIONS
1172
1173   // Transitions out of E state
1174   transition(E, GETX, NO_B_W) {
1175     pfa_probeFilterAllocate;
1176     v_allocateTBE;
1177     rx_recordExclusiveInTBE;
1178     saa_setAcksToAllIfPF;
1179     qf_queueMemoryFetchRequest;
1180     fn_forwardRequestIfNecessary;
1181     i_popIncomingRequestQueue;
1182   }
1183
1184   transition(E, GETS, NO_B_W) {
1185     pfa_probeFilterAllocate;
1186     v_allocateTBE;
1187     rx_recordExclusiveInTBE;
1188     saa_setAcksToAllIfPF;
1189     qf_queueMemoryFetchRequest;
1190     fn_forwardRequestIfNecessary;
1191     i_popIncomingRequestQueue;
1192   }
1193
1194   transition(E, DMA_READ, NO_DR_B_W) {
1195     vd_allocateDmaRequestInTBE;
1196     qd_queueMemoryRequestFromDmaRead;
1197     spa_setPendingAcksToZeroIfPF;
1198     f_forwardReadFromDma;
1199     p_popDmaRequestQueue;
1200   }
1201
1202   transition(E, DMA_WRITE, NO_DW_B_W) {
1203     vd_allocateDmaRequestInTBE;
1204     spa_setPendingAcksToZeroIfPF;
1205     sc_signalCompletionIfPF;
1206     f_forwardWriteFromDma;
1207     p_popDmaRequestQueue;
1208   }
1209
1210   // Transitions out of O state
1211   transition(O, GETX, NO_B_W) {
1212     r_setMRU;
1213     v_allocateTBE;
1214     r_recordDataInTBE;
1215     sa_setAcksToOne;
1216     qf_queueMemoryFetchRequest;
1217     fb_forwardRequestBcast;
1218     cs_clearSharers;
1219     i_popIncomingRequestQueue;
1220   }
1221
1222   // This transition is dumb, if a shared copy exists on-chip, then that should
1223   // provide data, not slow off-chip dram.  The problem is that the current
1224   // caches don't provide data in S state
1225   transition(O, GETS, O_B_W) {
1226     r_setMRU;
1227     v_allocateTBE;
1228     r_recordDataInTBE;
1229     saa_setAcksToAllIfPF;
1230     qf_queueMemoryFetchRequest;
1231     fn_forwardRequestIfNecessary;
1232     i_popIncomingRequestQueue;
1233   }
1234
1235   transition(O, DMA_READ, O_DR_B_W) {
1236     vd_allocateDmaRequestInTBE;
1237     spa_setPendingAcksToZeroIfPF;
1238     qd_queueMemoryRequestFromDmaRead;
1239     f_forwardReadFromDma;
1240     p_popDmaRequestQueue;
1241   }
1242
1243   transition(O, Pf_Replacement, O_R) {
1244     v_allocateTBE;
1245     pa_setPendingMsgsToAll;
1246     ia_invalidateAllRequest;
1247     pfd_probeFilterDeallocate;
1248   }
1249
1250   transition(S, Pf_Replacement, S_R) {
1251     v_allocateTBE;
1252     pa_setPendingMsgsToAll;
1253     ia_invalidateAllRequest;
1254     pfd_probeFilterDeallocate;
1255   }
1256
1257   transition(NO, Pf_Replacement, NO_R) {
1258     v_allocateTBE;
1259     po_setPendingMsgsToOne;
1260     io_invalidateOwnerRequest;
1261     pfd_probeFilterDeallocate;
1262   }
1263
1264   transition(NX, Pf_Replacement, NO_R) {
1265     v_allocateTBE;
1266     pa_setPendingMsgsToAll;
1267     ia_invalidateAllRequest;
1268     pfd_probeFilterDeallocate;
1269   }
1270
1271   transition({O, S, NO, NX}, DMA_WRITE, NO_DW_B_W) {
1272     vd_allocateDmaRequestInTBE;
1273     f_forwardWriteFromDma;
1274     p_popDmaRequestQueue;
1275   }
1276
1277   // Transitions out of NO state
1278   transition(NX, GETX, NO_B) {
1279     r_setMRU;
1280     fb_forwardRequestBcast;
1281     cs_clearSharers;
1282     i_popIncomingRequestQueue;
1283   }
1284
1285   // Transitions out of NO state
1286   transition(NO, GETX, NO_B) {
1287     r_setMRU;
1288     ano_assertNotOwner;
1289     fc_forwardRequestConditionalOwner;
1290     cs_clearSharers;
1291     i_popIncomingRequestQueue;
1292   }
1293
1294   transition(S, GETX, NO_B) {
1295     r_setMRU;
1296     fb_forwardRequestBcast;
1297     cs_clearSharers;
1298     i_popIncomingRequestQueue;
1299   }
1300
1301   transition(S, GETS, NO_B) {
1302     r_setMRU;
1303     ano_assertNotOwner;
1304     fb_forwardRequestBcast;
1305     i_popIncomingRequestQueue;
1306   }
1307
1308   transition(NO, GETS, NO_B) {
1309     r_setMRU;
1310     ano_assertNotOwner;
1311     ans_assertNotSharer;
1312     fc_forwardRequestConditionalOwner;
1313     i_popIncomingRequestQueue;
1314   }
1315
1316   transition(NX, GETS, NO_B) {
1317     r_setMRU;
1318     ano_assertNotOwner;
1319     fc_forwardRequestConditionalOwner;
1320     i_popIncomingRequestQueue;
1321   }
1322
1323   transition({NO, NX, S}, PUT, WB) {
1324     //
1325     // note that the PUT requestor may not be the current owner if an invalidate
1326     // raced with PUT
1327     //
1328     a_sendWriteBackAck;
1329     i_popIncomingRequestQueue;
1330   }
1331
1332   transition({NO, NX, S}, DMA_READ, NO_DR_B_D) {
1333     vd_allocateDmaRequestInTBE;
1334     f_forwardReadFromDma;
1335     p_popDmaRequestQueue;
1336   }
1337
1338   // Nack PUT requests when races cause us to believe we own the data
1339   transition({O, E}, PUT) {
1340     b_sendWriteBackNack;
1341     i_popIncomingRequestQueue;
1342   }
1343
1344   // Blocked transient states
1345   transition({NO_B_X, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
1346               NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W,
1347               NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R},
1348              {GETS, GETX, PUT, Pf_Replacement}) {
1349     z_stallAndWaitRequest;
1350   }
1351
1352   transition(NO_B, GETX, NO_B_X) {
1353     z_stallAndWaitRequest;
1354   }
1355
1356   transition(NO_B, {PUT, Pf_Replacement}) {
1357     z_stallAndWaitRequest;
1358   }
1359
1360   transition(NO_B_S, {GETX, PUT, Pf_Replacement}) {
1361     z_stallAndWaitRequest;
1362   }
1363
1364   transition({NO_B_X, NO_B, NO_B_S, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
1365               NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W,
1366               NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R},
1367              {DMA_READ, DMA_WRITE}) {
1368     zd_stallAndWaitDMARequest;
1369   }
1370
1371   // merge GETS into one response
1372   transition(NO_B, GETS, NO_B_S) {
1373     v_allocateTBE;
1374     rs_recordGetSRequestor;
1375     i_popIncomingRequestQueue;
1376   }
1377
1378   transition(NO_B_S, GETS) {
1379     rs_recordGetSRequestor;
1380     i_popIncomingRequestQueue;
1381   }
1382
1383   // unblock responses
1384   transition({NO_B, NO_B_X}, UnblockS, NX) {
1385     us_updateSharerIfFBD;
1386     k_wakeUpDependents;
1387     j_popIncomingUnblockQueue;
1388   }
1389
1390   transition({NO_B, NO_B_X}, UnblockM, NO) {
1391     uo_updateOwnerIfPf;
1392     us_updateSharerIfFBD;
1393     k_wakeUpDependents;
1394     j_popIncomingUnblockQueue;
1395   }
1396
1397   transition(NO_B_S, UnblockS, NO_B_S_W) {
1398     us_updateSharerIfFBD;
1399     fr_forwardMergeReadRequestsToOwner;
1400     sp_setPendingMsgsToMergedSharers;
1401     j_popIncomingUnblockQueue;
1402   }
1403
1404   transition(NO_B_S, UnblockM, NO_B_S_W) {
1405     uo_updateOwnerIfPf;
1406     fr_forwardMergeReadRequestsToOwner;
1407     sp_setPendingMsgsToMergedSharers;
1408     j_popIncomingUnblockQueue;
1409   }
1410
1411   transition(NO_B_S_W, UnblockS) {
1412     us_updateSharerIfFBD;
1413     mu_decrementNumberOfUnblocks;
1414     os_checkForMergedGetSCompletion;
1415     j_popIncomingUnblockQueue;
1416   }
1417
1418   transition(NO_B_S_W, All_Unblocks, NX) {
1419     w_deallocateTBE;
1420     k_wakeUpDependents;
1421     g_popTriggerQueue;
1422   }
1423
1424   transition(O_B, UnblockS, O) {
1425     us_updateSharerIfFBD;
1426     k_wakeUpDependents;
1427     j_popIncomingUnblockQueue;
1428   }
1429
1430   transition(O_B, UnblockM, NO) {
1431     us_updateSharerIfFBD;
1432     uo_updateOwnerIfPf;
1433     k_wakeUpDependents;
1434     j_popIncomingUnblockQueue;
1435   }
1436
1437   transition(NO_B_W, Memory_Data, NO_B) {
1438     d_sendData;
1439     w_deallocateTBE;
1440     l_popMemQueue;
1441   }
1442
1443   transition(NO_DR_B_W, Memory_Data, NO_DR_B) {
1444     r_recordMemoryData;
1445     o_checkForCompletion;
1446     l_popMemQueue;
1447   }
1448
1449   transition(O_DR_B_W, Memory_Data, O_DR_B) {
1450     r_recordMemoryData;
1451     dr_sendDmaData;
1452     o_checkForCompletion;
1453     l_popMemQueue;
1454   }
1455
1456   transition({NO_DR_B, O_DR_B, NO_DR_B_D, NO_DW_B_W}, Ack) {
1457     m_decrementNumberOfMessages;
1458     o_checkForCompletion;
1459     n_popResponseQueue;
1460   }
1461
1462   transition({O_R, S_R, NO_R}, Ack) {
1463     m_decrementNumberOfMessages;
1464     o_checkForCompletion;
1465     n_popResponseQueue;
1466   }
1467
1468   transition(S_R, Data) {
1469     wr_writeResponseDataToMemory;
1470     m_decrementNumberOfMessages;
1471     o_checkForCompletion;
1472     n_popResponseQueue;
1473   }
1474
1475   transition(NO_R, {Data, Exclusive_Data}) {
1476     wr_writeResponseDataToMemory;
1477     m_decrementNumberOfMessages;
1478     o_checkForCompletion;
1479     n_popResponseQueue;
1480   }
1481
1482   transition({O_R, S_R, NO_R}, All_acks_and_data_no_sharers, E) {
1483     w_deallocateTBE;
1484     k_wakeUpDependents;
1485     g_popTriggerQueue;
1486   }
1487
1488   transition({NO_DR_B_W, O_DR_B_W}, Ack) {
1489     m_decrementNumberOfMessages;
1490     n_popResponseQueue;
1491   }
1492
1493   transition(NO_DR_B_W, Shared_Ack) {
1494     m_decrementNumberOfMessages;
1495     r_setSharerBit;
1496     n_popResponseQueue;
1497   }
1498
1499   transition(O_DR_B, Shared_Ack) {
1500     m_decrementNumberOfMessages;
1501     so_setOwnerBit;
1502     o_checkForCompletion;
1503     n_popResponseQueue;
1504   }
1505
1506   transition(O_DR_B_W, Shared_Ack) {
1507     m_decrementNumberOfMessages;
1508     so_setOwnerBit;
1509     n_popResponseQueue;
1510   }
1511
1512   transition({NO_DR_B, NO_DR_B_D}, Shared_Ack) {
1513     m_decrementNumberOfMessages;
1514     r_setSharerBit;
1515     o_checkForCompletion;
1516     n_popResponseQueue;
1517   }
1518
1519   transition(NO_DR_B_W, Shared_Data) {
1520     r_recordCacheData;
1521     m_decrementNumberOfMessages;
1522     so_setOwnerBit;
1523     o_checkForCompletion;
1524     n_popResponseQueue;
1525   }
1526
1527   transition({NO_DR_B, NO_DR_B_D}, Shared_Data) {
1528     r_recordCacheData;
1529     m_decrementNumberOfMessages;
1530     so_setOwnerBit;
1531     o_checkForCompletion;
1532     n_popResponseQueue;
1533   }
1534
1535   transition(NO_DR_B_W, {Exclusive_Data, Data}) {
1536     r_recordCacheData;
1537     m_decrementNumberOfMessages;
1538     n_popResponseQueue;
1539   }
1540
1541   transition({NO_DR_B, NO_DR_B_D, NO_DW_B_W}, {Exclusive_Data, Data}) {
1542     r_recordCacheData;
1543     m_decrementNumberOfMessages;
1544     o_checkForCompletion;
1545     n_popResponseQueue;
1546   }
1547
1548   transition(NO_DR_B, All_acks_and_owner_data, O) {
1549     //
1550     // Note that the DMA consistency model allows us to send the DMA device
1551     // a response as soon as we receive valid data and prior to receiving
1552     // all acks.  However, to simplify the protocol we wait for all acks.
1553     //
1554     dt_sendDmaDataFromTbe;
1555     wdt_writeDataFromTBE;
1556     w_deallocateTBE;
1557     k_wakeUpDependents;
1558     g_popTriggerQueue;
1559   }
1560
1561   transition(NO_DR_B, All_acks_and_shared_data, S) {
1562     //
1563     // Note that the DMA consistency model allows us to send the DMA device
1564     // a response as soon as we receive valid data and prior to receiving
1565     // all acks.  However, to simplify the protocol we wait for all acks.
1566     //
1567     dt_sendDmaDataFromTbe;
1568     wdt_writeDataFromTBE;
1569     w_deallocateTBE;
1570     k_wakeUpDependents;
1571     g_popTriggerQueue;
1572   }
1573
1574   transition(NO_DR_B_D, All_acks_and_owner_data, O) {
1575     //
1576     // Note that the DMA consistency model allows us to send the DMA device
1577     // a response as soon as we receive valid data and prior to receiving
1578     // all acks.  However, to simplify the protocol we wait for all acks.
1579     //
1580     dt_sendDmaDataFromTbe;
1581     wdt_writeDataFromTBE;
1582     w_deallocateTBE;
1583     k_wakeUpDependents;
1584     g_popTriggerQueue;
1585   }
1586
1587   transition(NO_DR_B_D, All_acks_and_shared_data, S) {
1588     //
1589     // Note that the DMA consistency model allows us to send the DMA device
1590     // a response as soon as we receive valid data and prior to receiving
1591     // all acks.  However, to simplify the protocol we wait for all acks.
1592     //
1593     dt_sendDmaDataFromTbe;
1594     wdt_writeDataFromTBE;
1595     w_deallocateTBE;
1596     k_wakeUpDependents;
1597     g_popTriggerQueue;
1598   }
1599
1600   transition(O_DR_B, All_acks_and_owner_data, O) {
1601     wdt_writeDataFromTBE;
1602     w_deallocateTBE;
1603     k_wakeUpDependents;
1604     g_popTriggerQueue;
1605   }
1606
1607   transition(O_DR_B, All_acks_and_data_no_sharers, E) {
1608     wdt_writeDataFromTBE;
1609     w_deallocateTBE;
1610     pfd_probeFilterDeallocate;
1611     k_wakeUpDependents;
1612     g_popTriggerQueue;
1613   }
1614
1615   transition(NO_DR_B, All_acks_and_data_no_sharers, E) {
1616     //
1617     // Note that the DMA consistency model allows us to send the DMA device
1618     // a response as soon as we receive valid data and prior to receiving
1619     // all acks.  However, to simplify the protocol we wait for all acks.
1620     //
1621     dt_sendDmaDataFromTbe;
1622     wdt_writeDataFromTBE;
1623     w_deallocateTBE;
1624     ppfd_possibleProbeFilterDeallocate;
1625     k_wakeUpDependents;
1626     g_popTriggerQueue;
1627   }
1628
1629   transition(NO_DR_B_D, All_acks_and_data_no_sharers, E) {
1630     a_assertCacheData;
1631     //
1632     // Note that the DMA consistency model allows us to send the DMA device
1633     // a response as soon as we receive valid data and prior to receiving
1634     // all acks.  However, to simplify the protocol we wait for all acks.
1635     //
1636     dt_sendDmaDataFromTbe;
1637     wdt_writeDataFromTBE;
1638     w_deallocateTBE;
1639     ppfd_possibleProbeFilterDeallocate;
1640     k_wakeUpDependents;
1641     g_popTriggerQueue;
1642   }
1643
1644   transition(NO_DW_B_W, All_acks_and_data_no_sharers, NO_DW_W) {
1645     dwt_writeDmaDataFromTBE;
1646     ld_queueMemoryDmaWrite;
1647     g_popTriggerQueue;
1648   }
1649
1650   transition(NO_DW_W, Memory_Ack, E) {
1651     da_sendDmaAck;
1652     w_deallocateTBE;
1653     ppfd_possibleProbeFilterDeallocate;
1654     k_wakeUpDependents;
1655     l_popMemQueue;
1656   }
1657
1658   transition(O_B_W, Memory_Data, O_B) {
1659     d_sendData;
1660     w_deallocateTBE;
1661     l_popMemQueue;
1662   }
1663
1664   transition(NO_B_W, UnblockM, NO_W) {
1665     uo_updateOwnerIfPf;
1666     j_popIncomingUnblockQueue;
1667   }
1668
1669   transition(NO_B_W, UnblockS, NO_W) {
1670     us_updateSharerIfFBD;
1671     j_popIncomingUnblockQueue;
1672   }
1673
1674   transition(O_B_W, UnblockS, O_W) {
1675     us_updateSharerIfFBD;
1676     j_popIncomingUnblockQueue;
1677   }
1678
1679   transition(NO_W, Memory_Data, NO) {
1680     w_deallocateTBE;
1681     k_wakeUpDependents;
1682     l_popMemQueue;
1683   }
1684
1685   transition(O_W, Memory_Data, O) {
1686     w_deallocateTBE;
1687     k_wakeUpDependents;
1688     l_popMemQueue;
1689   }
1690
1691   // WB State Transistions
1692   transition(WB, Writeback_Dirty, WB_O_W) {
1693     l_writeDataToMemory;
1694     rs_removeSharer;
1695     l_queueMemoryWBRequest;
1696     j_popIncomingUnblockQueue;
1697   }
1698
1699   transition(WB, Writeback_Exclusive_Dirty, WB_E_W) {
1700     l_writeDataToMemory;
1701     rs_removeSharer;
1702     l_queueMemoryWBRequest;
1703     j_popIncomingUnblockQueue;
1704   }
1705
1706   transition(WB_E_W, Memory_Ack, E) {
1707     pfd_probeFilterDeallocate;
1708     k_wakeUpDependents;
1709     l_popMemQueue;
1710   }
1711
1712   transition(WB_O_W, Memory_Ack, O) {
1713     k_wakeUpDependents;
1714     l_popMemQueue;
1715   }
1716
1717   transition(WB, Writeback_Clean, O) {
1718     ll_checkIncomingWriteback;
1719     rs_removeSharer;
1720     k_wakeUpDependents;
1721     j_popIncomingUnblockQueue;
1722   }
1723
1724   transition(WB, Writeback_Exclusive_Clean, E) {
1725     ll_checkIncomingWriteback;
1726     rs_removeSharer;
1727     pfd_probeFilterDeallocate;
1728     k_wakeUpDependents;
1729     j_popIncomingUnblockQueue;
1730   }
1731
1732   transition(WB, Unblock, NX) {
1733     auno_assertUnblockerNotOwner;
1734     k_wakeUpDependents;
1735     j_popIncomingUnblockQueue;
1736   }
1737 }