src/mem/protocol/MOESI_hammer-dma.sm

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29
  30 machine(DMA, "DMA Controller")
  31     : DMASequencer * dma_sequencer;
  32       Cycles request_latency := 6;
  33
  34       MessageBuffer * responseFromDir, network="From", virtual_network="1",
  35             vnet_type="response";
  36       MessageBuffer * requestToDir, network="To", virtual_network="0",
  37             vnet_type="request";
  38       MessageBuffer * mandatoryQueue;
  39 {
  40   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  41     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  42     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  43     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  44   }
  45
  46   enumeration(Event, desc="DMA events") {
  47     ReadRequest,  desc="A new read request";
  48     WriteRequest, desc="A new write request";
  49     Data,         desc="Data from a DMA memory read";
  50     Ack,          desc="DMA write to memory completed";
  51   }
  52
  53   State cur_state;
  54
  55   Tick clockEdge();
  56
  57   State getState(Addr addr) {
  58     return cur_state;
  59   }
  60   void setState(Addr addr, State state) {
  61     cur_state := state;
  62   }
  63
  64   AccessPermission getAccessPermission(Addr addr) {
  65     return AccessPermission:NotPresent;
  66   }
  67
  68   void setAccessPermission(Addr addr, State state) {
  69   }
  70
  71   void functionalRead(Addr addr, Packet *pkt) {
  72     error("DMA does not support functional read.");
  73   }
  74
  75   int functionalWrite(Addr addr, Packet *pkt) {
  76     error("DMA does not support functional write.");
  77   }
  78
  79   out_port(requestToDir_out, DMARequestMsg, requestToDir, desc="...");
  80
  81   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  82     if (dmaRequestQueue_in.isReady(clockEdge())) {
  83       peek(dmaRequestQueue_in, SequencerMsg) {
  84         if (in_msg.Type == SequencerRequestType:LD ) {
  85           trigger(Event:ReadRequest, in_msg.LineAddress);
  86         } else if (in_msg.Type == SequencerRequestType:ST) {
  87           trigger(Event:WriteRequest, in_msg.LineAddress);
  88         } else {
  89           error("Invalid request type");
  90         }
  91       }
  92     }
  93   }
  94
  95   in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
  96     if (dmaResponseQueue_in.isReady(clockEdge())) {
  97       peek( dmaResponseQueue_in, DMAResponseMsg) {
  98         if (in_msg.Type == DMAResponseType:ACK) {
  99           trigger(Event:Ack, in_msg.LineAddress);
 100         } else if (in_msg.Type == DMAResponseType:DATA) {
 101           trigger(Event:Data, in_msg.LineAddress);
 102         } else {
 103           error("Invalid response type");
 104         }
 105       }
 106     }
 107   }
 108
 109   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 110     peek(dmaRequestQueue_in, SequencerMsg) {
 111       enqueue(requestToDir_out, DMARequestMsg, request_latency) {
 112         out_msg.PhysicalAddress := in_msg.PhysicalAddress;
 113         out_msg.LineAddress := in_msg.LineAddress;
 114         out_msg.Type := DMARequestType:READ;
 115         out_msg.Requestor := machineID;
 116         out_msg.DataBlk := in_msg.DataBlk;
 117         out_msg.Len := in_msg.Len;
 118         out_msg.Destination.add(map_Address_to_Directory(address));
 119         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 120       }
 121     }
 122   }
 123
 124   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 125     peek(dmaRequestQueue_in, SequencerMsg) {
 126       enqueue(requestToDir_out, DMARequestMsg, request_latency) {
 127           out_msg.PhysicalAddress := in_msg.PhysicalAddress;
 128           out_msg.LineAddress := in_msg.LineAddress;
 129           out_msg.Type := DMARequestType:WRITE;
 130           out_msg.Requestor := machineID;
 131           out_msg.DataBlk := in_msg.DataBlk;
 132           out_msg.Len := in_msg.Len;
 133           out_msg.Destination.add(map_Address_to_Directory(address));
 134           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 135         }
 136       }
 137   }
 138
 139   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 140     peek (dmaResponseQueue_in, DMAResponseMsg) {
 141       dma_sequencer.ackCallback();
 142     }
 143   }
 144
 145   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
 146     peek (dmaResponseQueue_in, DMAResponseMsg) {
 147       dma_sequencer.dataCallback(in_msg.DataBlk);
 148     }
 149   }
 150
 151   action(p_popRequestQueue, "p", desc="Pop request queue") {
 152     dmaRequestQueue_in.dequeue(clockEdge());
 153   }
 154
 155   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 156     dmaResponseQueue_in.dequeue(clockEdge());
 157   }
 158
 159   transition(READY, ReadRequest, BUSY_RD) {
 160     s_sendReadRequest;
 161     p_popRequestQueue;
 162   }
 163
 164   transition(READY, WriteRequest, BUSY_WR) {
 165     s_sendWriteRequest;
 166     p_popRequestQueue;
 167   }
 168
 169   transition(BUSY_RD, Data, READY) {
 170     d_dataCallback;
 171     p_popResponseQueue;
 172   }
 173
 174   transition(BUSY_WR, Ack, READY) {
 175     a_ackCallback;
 176     p_popResponseQueue;
 177   }
 178 }