src/mem/protocol/MOESI_hammer-dma.sm

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29
  30 machine(DMA, "DMA Controller")
  31 : DMASequencer * dma_sequencer,
  32   int request_latency = 6
  33 {
  34
  35   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
  36   MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
  37
  38   state_declaration(State,
  39                     desc="DMA states",
  40                     default="DMA_State_READY") {
  41     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  42     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  43     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  44   }
  45
  46   enumeration(Event, desc="DMA events") {
  47     ReadRequest,  desc="A new read request";
  48     WriteRequest, desc="A new write request";
  49     Data,         desc="Data from a DMA memory read";
  50     Ack,          desc="DMA write to memory completed";
  51   }
  52
  53   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
  54   State cur_state, no_vector="true";
  55
  56   State getState(Address addr) {
  57     return cur_state;
  58   }
  59   void setState(Address addr, State state) {
  60     cur_state := state;
  61   }
  62
  63   AccessPermission getAccessPermission(Address addr) {
  64     return AccessPermission:NotPresent;
  65   }
  66
  67   void setAccessPermission(Address addr, State state) {
  68   }
  69
  70   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
  71     error("DMA Controller does not support getDataBlock function.\n");
  72   }
  73
  74   out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
  75
  76   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  77     if (dmaRequestQueue_in.isReady()) {
  78       peek(dmaRequestQueue_in, SequencerMsg) {
  79         if (in_msg.Type == SequencerRequestType:LD ) {
  80           trigger(Event:ReadRequest, in_msg.LineAddress);
  81         } else if (in_msg.Type == SequencerRequestType:ST) {
  82           trigger(Event:WriteRequest, in_msg.LineAddress);
  83         } else {
  84           error("Invalid request type");
  85         }
  86       }
  87     }
  88   }
  89
  90   in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
  91     if (dmaResponseQueue_in.isReady()) {
  92       peek( dmaResponseQueue_in, DMAResponseMsg) {
  93         if (in_msg.Type == DMAResponseType:ACK) {
  94           trigger(Event:Ack, in_msg.LineAddress);
  95         } else if (in_msg.Type == DMAResponseType:DATA) {
  96           trigger(Event:Data, in_msg.LineAddress);
  97         } else {
  98           error("Invalid response type");
  99         }
 100       }
 101     }
 102   }
 103
 104   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 105     peek(dmaRequestQueue_in, SequencerMsg) {
 106       enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
 107         out_msg.PhysicalAddress := in_msg.PhysicalAddress;
 108         out_msg.LineAddress := in_msg.LineAddress;
 109         out_msg.Type := DMARequestType:READ;
 110         out_msg.Requestor := machineID;
 111         out_msg.DataBlk := in_msg.DataBlk;
 112         out_msg.Len := in_msg.Len;
 113         out_msg.Destination.add(map_Address_to_Directory(address));
 114         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 115       }
 116     }
 117   }
 118
 119   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 120     peek(dmaRequestQueue_in, SequencerMsg) {
 121       enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
 122           out_msg.PhysicalAddress := in_msg.PhysicalAddress;
 123           out_msg.LineAddress := in_msg.LineAddress;
 124           out_msg.Type := DMARequestType:WRITE;
 125           out_msg.Requestor := machineID;
 126           out_msg.DataBlk := in_msg.DataBlk;
 127           out_msg.Len := in_msg.Len;
 128           out_msg.Destination.add(map_Address_to_Directory(address));
 129           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 130         }
 131       }
 132   }
 133
 134   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 135     peek (dmaResponseQueue_in, DMAResponseMsg) {
 136       dma_sequencer.ackCallback();
 137     }
 138   }
 139
 140   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
 141     peek (dmaResponseQueue_in, DMAResponseMsg) {
 142       dma_sequencer.dataCallback(in_msg.DataBlk);
 143     }
 144   }
 145
 146   action(p_popRequestQueue, "p", desc="Pop request queue") {
 147     dmaRequestQueue_in.dequeue();
 148   }
 149
 150   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 151     dmaResponseQueue_in.dequeue();
 152   }
 153
 154   transition(READY, ReadRequest, BUSY_RD) {
 155     s_sendReadRequest;
 156     p_popRequestQueue;
 157   }
 158
 159   transition(READY, WriteRequest, BUSY_WR) {
 160     s_sendWriteRequest;
 161     p_popRequestQueue;
 162   }
 163
 164   transition(BUSY_RD, Data, READY) {
 165     d_dataCallback;
 166     p_popResponseQueue;
 167   }
 168
 169   transition(BUSY_WR, Ack, READY) {
 170     a_ackCallback;
 171     p_popResponseQueue;
 172   }
 173 }