2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30 machine(DMA, "DMA Controller")
31 : DMASequencer * dma_sequencer,
32 int request_latency = 6
35 MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
36 MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
38 enumeration(State, desc="DMA states", default="DMA_State_READY") {
39 READY, desc="Ready to accept a new request";
40 BUSY_RD, desc="Busy: currently processing a request";
41 BUSY_WR, desc="Busy: currently processing a request";
44 enumeration(Event, desc="DMA events") {
45 ReadRequest, desc="A new read request";
46 WriteRequest, desc="A new write request";
47 Data, desc="Data from a DMA memory read";
48 Ack, desc="DMA write to memory completed";
51 MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
52 State cur_state, no_vector="true";
54 State getState(Address addr) {
57 void setState(Address addr, State state) {
61 out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
63 in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
64 if (dmaRequestQueue_in.isReady()) {
65 peek(dmaRequestQueue_in, SequencerMsg) {
66 if (in_msg.Type == SequencerRequestType:LD ) {
67 trigger(Event:ReadRequest, in_msg.LineAddress);
68 } else if (in_msg.Type == SequencerRequestType:ST) {
69 trigger(Event:WriteRequest, in_msg.LineAddress);
71 error("Invalid request type");
77 in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
78 if (dmaResponseQueue_in.isReady()) {
79 peek( dmaResponseQueue_in, DMAResponseMsg) {
80 if (in_msg.Type == DMAResponseType:ACK) {
81 trigger(Event:Ack, in_msg.LineAddress);
82 } else if (in_msg.Type == DMAResponseType:DATA) {
83 trigger(Event:Data, in_msg.LineAddress);
85 error("Invalid response type");
91 action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
92 peek(dmaRequestQueue_in, SequencerMsg) {
93 enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
94 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
95 out_msg.LineAddress := in_msg.LineAddress;
96 out_msg.Type := DMARequestType:READ;
97 out_msg.Requestor := machineID;
98 out_msg.DataBlk := in_msg.DataBlk;
99 out_msg.Len := in_msg.Len;
100 out_msg.Destination.add(map_Address_to_Directory(address));
101 out_msg.MessageSize := MessageSizeType:Writeback_Control;
106 action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
107 peek(dmaRequestQueue_in, SequencerMsg) {
108 enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
109 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
110 out_msg.LineAddress := in_msg.LineAddress;
111 out_msg.Type := DMARequestType:WRITE;
112 out_msg.Requestor := machineID;
113 out_msg.DataBlk := in_msg.DataBlk;
114 out_msg.Len := in_msg.Len;
115 out_msg.Destination.add(map_Address_to_Directory(address));
116 out_msg.MessageSize := MessageSizeType:Writeback_Control;
121 action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
122 peek (dmaResponseQueue_in, DMAResponseMsg) {
123 dma_sequencer.ackCallback();
127 action(d_dataCallback, "d", desc="Write data to dma sequencer") {
128 peek (dmaResponseQueue_in, DMAResponseMsg) {
129 dma_sequencer.dataCallback(in_msg.DataBlk);
133 action(p_popRequestQueue, "p", desc="Pop request queue") {
134 dmaRequestQueue_in.dequeue();
137 action(p_popResponseQueue, "\p", desc="Pop request queue") {
138 dmaResponseQueue_in.dequeue();
141 transition(READY, ReadRequest, BUSY_RD) {
146 transition(READY, WriteRequest, BUSY_WR) {
151 transition(BUSY_RD, Data, READY) {
156 transition(BUSY_WR, Ack, READY) {