src/mem/protocol/MOESI_hammer-dma.sm

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29
  30 machine(DMA, "DMA Controller")
  31 : DMASequencer * dma_sequencer,
  32   int request_latency = 6
  33 {
  34
  35   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
  36   MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
  37
  38   state_declaration(State,
  39                     desc="DMA states",
  40                     default="DMA_State_READY") {
  41     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  42     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  43     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  44   }
  45
  46   enumeration(Event, desc="DMA events") {
  47     ReadRequest,  desc="A new read request";
  48     WriteRequest, desc="A new write request";
  49     Data,         desc="Data from a DMA memory read";
  50     Ack,          desc="DMA write to memory completed";
  51   }
  52
  53   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
  54   State cur_state, no_vector="true";
  55
  56   State getState(Address addr) {
  57     return cur_state;
  58   }
  59   void setState(Address addr, State state) {
  60     cur_state := state;
  61   }
  62
  63   out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
  64
  65   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  66     if (dmaRequestQueue_in.isReady()) {
  67       peek(dmaRequestQueue_in, SequencerMsg) {
  68         if (in_msg.Type == SequencerRequestType:LD ) {
  69           trigger(Event:ReadRequest, in_msg.LineAddress);
  70         } else if (in_msg.Type == SequencerRequestType:ST) {
  71           trigger(Event:WriteRequest, in_msg.LineAddress);
  72         } else {
  73           error("Invalid request type");
  74         }
  75       }
  76     }
  77   }
  78
  79   in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
  80     if (dmaResponseQueue_in.isReady()) {
  81       peek( dmaResponseQueue_in, DMAResponseMsg) {
  82         if (in_msg.Type == DMAResponseType:ACK) {
  83           trigger(Event:Ack, in_msg.LineAddress);
  84         } else if (in_msg.Type == DMAResponseType:DATA) {
  85           trigger(Event:Data, in_msg.LineAddress);
  86         } else {
  87           error("Invalid response type");
  88         }
  89       }
  90     }
  91   }
  92
  93   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
  94     peek(dmaRequestQueue_in, SequencerMsg) {
  95       enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
  96         out_msg.PhysicalAddress := in_msg.PhysicalAddress;
  97         out_msg.LineAddress := in_msg.LineAddress;
  98         out_msg.Type := DMARequestType:READ;
  99         out_msg.Requestor := machineID;
 100         out_msg.DataBlk := in_msg.DataBlk;
 101         out_msg.Len := in_msg.Len;
 102         out_msg.Destination.add(map_Address_to_Directory(address));
 103         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 104       }
 105     }
 106   }
 107
 108   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 109     peek(dmaRequestQueue_in, SequencerMsg) {
 110       enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
 111           out_msg.PhysicalAddress := in_msg.PhysicalAddress;
 112           out_msg.LineAddress := in_msg.LineAddress;
 113           out_msg.Type := DMARequestType:WRITE;
 114           out_msg.Requestor := machineID;
 115           out_msg.DataBlk := in_msg.DataBlk;
 116           out_msg.Len := in_msg.Len;
 117           out_msg.Destination.add(map_Address_to_Directory(address));
 118           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 119         }
 120       }
 121   }
 122
 123   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 124     peek (dmaResponseQueue_in, DMAResponseMsg) {
 125       dma_sequencer.ackCallback();
 126     }
 127   }
 128
 129   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
 130     peek (dmaResponseQueue_in, DMAResponseMsg) {
 131       dma_sequencer.dataCallback(in_msg.DataBlk);
 132     }
 133   }
 134
 135   action(p_popRequestQueue, "p", desc="Pop request queue") {
 136     dmaRequestQueue_in.dequeue();
 137   }
 138
 139   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 140     dmaResponseQueue_in.dequeue();
 141   }
 142
 143   transition(READY, ReadRequest, BUSY_RD) {
 144     s_sendReadRequest;
 145     p_popRequestQueue;
 146   }
 147
 148   transition(READY, WriteRequest, BUSY_WR) {
 149     s_sendWriteRequest;
 150     p_popRequestQueue;
 151   }
 152
 153   transition(BUSY_RD, Data, READY) {
 154     d_dataCallback;
 155     p_popResponseQueue;
 156   }
 157
 158   transition(BUSY_WR, Ack, READY) {
 159     a_ackCallback;
 160     p_popResponseQueue;
 161   }
 162 }