2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30 machine(DMA, "DMA Controller")
34 MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true";
35 MessageBuffer reqToDirectory, network="To", virtual_network="5", ordered="false", no_vector="true";
37 enumeration(State, desc="DMA states", default="DMA_State_READY") {
38 READY, desc="Ready to accept a new request";
39 BUSY_RD, desc="Busy: currently processing a request";
40 BUSY_WR, desc="Busy: currently processing a request";
43 enumeration(Event, desc="DMA events") {
44 ReadRequest, desc="A new read request";
45 WriteRequest, desc="A new write request";
46 Data, desc="Data from a DMA memory read";
47 Ack, desc="DMA write to memory completed";
50 external_type(DMASequencer) {
52 void dataCallback(DataBlock);
55 MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
56 DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
57 State cur_state, no_vector="true";
59 State getState(Address addr) {
62 void setState(Address addr, State state) {
66 out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
68 in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
69 if (dmaRequestQueue_in.isReady()) {
70 peek(dmaRequestQueue_in, SequencerMsg) {
71 if (in_msg.Type == SequencerRequestType:LD ) {
72 trigger(Event:ReadRequest, in_msg.LineAddress);
73 } else if (in_msg.Type == SequencerRequestType:ST) {
74 trigger(Event:WriteRequest, in_msg.LineAddress);
76 error("Invalid request type");
82 in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
83 if (dmaResponseQueue_in.isReady()) {
84 peek( dmaResponseQueue_in, DMAResponseMsg) {
85 if (in_msg.Type == DMAResponseType:ACK) {
86 trigger(Event:Ack, in_msg.LineAddress);
87 } else if (in_msg.Type == DMAResponseType:DATA) {
88 trigger(Event:Data, in_msg.LineAddress);
90 error("Invalid response type");
96 action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
97 peek(dmaRequestQueue_in, SequencerMsg) {
98 enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
99 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
100 out_msg.LineAddress := in_msg.LineAddress;
101 out_msg.Type := DMARequestType:READ;
102 out_msg.Requestor := machineID;
103 out_msg.DataBlk := in_msg.DataBlk;
104 out_msg.Len := in_msg.Len;
105 out_msg.Destination.add(map_Address_to_Directory(address));
106 out_msg.MessageSize := MessageSizeType:Writeback_Control;
111 action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
112 peek(dmaRequestQueue_in, SequencerMsg) {
113 enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
114 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
115 out_msg.LineAddress := in_msg.LineAddress;
116 out_msg.Type := DMARequestType:WRITE;
117 out_msg.Requestor := machineID;
118 out_msg.DataBlk := in_msg.DataBlk;
119 out_msg.Len := in_msg.Len;
120 out_msg.Destination.add(map_Address_to_Directory(address));
121 out_msg.MessageSize := MessageSizeType:Writeback_Control;
126 action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
127 peek (dmaResponseQueue_in, DMAResponseMsg) {
128 dma_sequencer.ackCallback();
132 action(d_dataCallback, "d", desc="Write data to dma sequencer") {
133 peek (dmaResponseQueue_in, DMAResponseMsg) {
134 dma_sequencer.dataCallback(in_msg.DataBlk);
138 action(p_popRequestQueue, "p", desc="Pop request queue") {
139 dmaRequestQueue_in.dequeue();
142 action(p_popResponseQueue, "\p", desc="Pop request queue") {
143 dmaResponseQueue_in.dequeue();
146 transition(READY, ReadRequest, BUSY_RD) {
151 transition(READY, WriteRequest, BUSY_WR) {
156 transition(BUSY_RD, Data, READY) {
161 transition(BUSY_WR, Ack, READY) {