2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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30 machine(DMA, "DMA Controller")
31 : DMASequencer * dma_sequencer,
32 int request_latency = 6
35 MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
36 MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
38 state_declaration(State,
40 default="DMA_State_READY") {
41 READY, AccessPermission:Invalid, desc="Ready to accept a new request";
42 BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
43 BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
46 enumeration(Event, desc="DMA events") {
47 ReadRequest, desc="A new read request";
48 WriteRequest, desc="A new write request";
49 Data, desc="Data from a DMA memory read";
50 Ack, desc="DMA write to memory completed";
53 MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
54 State cur_state, no_vector="true";
56 State getState(Address addr) {
59 void setState(Address addr, State state) {
63 AccessPermission getAccessPermission(Address addr) {
64 return AccessPermission:NotPresent;
67 void setAccessPermission(Address addr, State state) {
70 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
71 error("DMA Controller does not support getDataBlock function.\n");
74 out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
76 in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
77 if (dmaRequestQueue_in.isReady()) {
78 peek(dmaRequestQueue_in, SequencerMsg) {
79 if (in_msg.Type == SequencerRequestType:LD ) {
80 trigger(Event:ReadRequest, in_msg.LineAddress);
81 } else if (in_msg.Type == SequencerRequestType:ST) {
82 trigger(Event:WriteRequest, in_msg.LineAddress);
84 error("Invalid request type");
90 in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
91 if (dmaResponseQueue_in.isReady()) {
92 peek( dmaResponseQueue_in, DMAResponseMsg) {
93 if (in_msg.Type == DMAResponseType:ACK) {
94 trigger(Event:Ack, in_msg.LineAddress);
95 } else if (in_msg.Type == DMAResponseType:DATA) {
96 trigger(Event:Data, in_msg.LineAddress);
98 error("Invalid response type");
104 action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
105 peek(dmaRequestQueue_in, SequencerMsg) {
106 enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
107 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
108 out_msg.LineAddress := in_msg.LineAddress;
109 out_msg.Type := DMARequestType:READ;
110 out_msg.Requestor := machineID;
111 out_msg.DataBlk := in_msg.DataBlk;
112 out_msg.Len := in_msg.Len;
113 out_msg.Destination.add(map_Address_to_Directory(address));
114 out_msg.MessageSize := MessageSizeType:Writeback_Control;
119 action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
120 peek(dmaRequestQueue_in, SequencerMsg) {
121 enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
122 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
123 out_msg.LineAddress := in_msg.LineAddress;
124 out_msg.Type := DMARequestType:WRITE;
125 out_msg.Requestor := machineID;
126 out_msg.DataBlk := in_msg.DataBlk;
127 out_msg.Len := in_msg.Len;
128 out_msg.Destination.add(map_Address_to_Directory(address));
129 out_msg.MessageSize := MessageSizeType:Writeback_Control;
134 action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
135 peek (dmaResponseQueue_in, DMAResponseMsg) {
136 dma_sequencer.ackCallback();
140 action(d_dataCallback, "d", desc="Write data to dma sequencer") {
141 peek (dmaResponseQueue_in, DMAResponseMsg) {
142 dma_sequencer.dataCallback(in_msg.DataBlk);
146 action(p_popRequestQueue, "p", desc="Pop request queue") {
147 dmaRequestQueue_in.dequeue();
150 action(p_popResponseQueue, "\p", desc="Pop request queue") {
151 dmaResponseQueue_in.dequeue();
154 transition(READY, ReadRequest, BUSY_RD) {
159 transition(READY, WriteRequest, BUSY_WR) {
164 transition(BUSY_RD, Data, READY) {
169 transition(BUSY_WR, Ack, READY) {