cpu: Add TraceCPU to playback elastic traces
[gem5.git] / src / mem / protocol / MOESI_hammer-msg.sm
1 /*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * AMD's contributions to the MOESI hammer protocol do not constitute an
29 * endorsement of its similarity to any AMD products.
30 */
31
32 // CoherenceRequestType
33 enumeration(CoherenceRequestType, desc="...") {
34 GETX, desc="Get eXclusive";
35 GETS, desc="Get Shared";
36 MERGED_GETS, desc="Get Shared";
37 PUT, desc="Put Ownership";
38 WB_ACK, desc="Writeback ack";
39 WB_NACK, desc="Writeback neg. ack";
40 PUTF, desc="PUT on a Flush";
41 GETF, desc="Issue exclusive for Flushing";
42 BLOCK_ACK, desc="Dir Block ack";
43 INV, desc="Invalidate";
44 }
45
46 // CoherenceResponseType
47 enumeration(CoherenceResponseType, desc="...") {
48 ACK, desc="ACKnowledgment, responder does not have a copy";
49 ACK_SHARED, desc="ACKnowledgment, responder has a shared copy";
50 DATA, desc="Data, responder does not have a copy";
51 DATA_SHARED, desc="Data, responder has a shared copy";
52 DATA_EXCLUSIVE, desc="Data, responder was exclusive, gave us a copy, and they went to invalid";
53 WB_CLEAN, desc="Clean writeback";
54 WB_DIRTY, desc="Dirty writeback";
55 WB_EXCLUSIVE_CLEAN, desc="Clean writeback of exclusive data";
56 WB_EXCLUSIVE_DIRTY, desc="Dirty writeback of exclusive data";
57 UNBLOCK, desc="Unblock for writeback";
58 UNBLOCKS, desc="Unblock now in S";
59 UNBLOCKM, desc="Unblock now in M/O/E";
60 NULL, desc="Null value";
61 }
62
63 // TriggerType
64 enumeration(TriggerType, desc="...") {
65 L2_to_L1, desc="L2 to L1 transfer";
66 ALL_ACKS, desc="See corresponding event";
67 ALL_ACKS_OWNER_EXISTS,desc="See corresponding event";
68 ALL_ACKS_NO_SHARERS, desc="See corresponding event";
69 ALL_UNBLOCKS, desc="all unblockS received";
70 }
71
72 // TriggerMsg
73 structure(TriggerMsg, desc="...", interface="Message") {
74 Addr addr, desc="Physical address for this request";
75 TriggerType Type, desc="Type of trigger";
76
77 bool functionalRead(Packet *pkt) {
78 // Trigger messages do not hold any data!
79 return false;
80 }
81
82 bool functionalWrite(Packet *pkt) {
83 // Trigger messages do not hold any data!
84 return false;
85 }
86 }
87
88 // RequestMsg (and also forwarded requests)
89 structure(RequestMsg, desc="...", interface="Message") {
90 Addr addr, desc="Physical address for this request";
91 CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
92 MachineID Requestor, desc="Node who initiated the request";
93 NetDest MergedRequestors, desc="Merge set of read requestors";
94 NetDest Destination, desc="Multicast destination mask";
95 MessageSizeType MessageSize, desc="size category of the message";
96 bool DirectedProbe, default="false", desc="probe filter directed probe";
97
98 Cycles InitialRequestTime, default="Cycles(0)",
99 desc="time the initial requests was sent from the L1Cache";
100 Cycles ForwardRequestTime, default="Cycles(0)",
101 desc="time the dir forwarded the request";
102 int SilentAcks, default="0", desc="silent acks from the full-bit directory";
103
104 bool functionalRead(Packet *pkt) {
105 // Request messages do not hold any data
106 return false;
107 }
108
109 bool functionalWrite(Packet *pkt) {
110 // Request messages do not hold any data
111 return false;
112 }
113 }
114
115 // ResponseMsg (and also unblock requests)
116 structure(ResponseMsg, desc="...", interface="Message") {
117 Addr addr, desc="Physical address for this request";
118 CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
119 MachineID Sender, desc="Node who sent the data";
120 MachineID CurOwner, desc="current owner of the block, used for UnblockS responses";
121 NetDest Destination, desc="Node to whom the data is sent";
122 DataBlock DataBlk, desc="data for the cache line";
123 bool Dirty, desc="Is the data dirty (different than memory)?";
124 int Acks, default="0", desc="How many messages this counts as";
125 MessageSizeType MessageSize, desc="size category of the message";
126
127 Cycles InitialRequestTime, default="Cycles(0)",
128 desc="time the initial requests was sent from the L1Cache";
129 Cycles ForwardRequestTime, default="Cycles(0)",
130 desc="time the dir forwarded the request";
131 int SilentAcks, default="0", desc="silent acks from the full-bit directory";
132
133 bool functionalRead(Packet *pkt) {
134 // The check below ensures that data is read only from messages that
135 // actually hold data.
136 if (Type == CoherenceResponseType:DATA ||
137 Type == CoherenceResponseType:DATA_SHARED ||
138 Type == CoherenceResponseType:DATA_EXCLUSIVE ||
139 Type == CoherenceResponseType:WB_DIRTY ||
140 Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) {
141 return testAndRead(addr, DataBlk, pkt);
142 }
143
144 return false;
145 }
146
147 bool functionalWrite(Packet *pkt) {
148 // Message type does not matter since all messages are written.
149 // If a protocol reads data from a packet that is not supposed
150 // to hold the data, then the fault lies with the protocol.
151 return testAndWrite(addr, DataBlk, pkt);
152 }
153 }
154
155 enumeration(DMARequestType, desc="...", default="DMARequestType_NULL") {
156 READ, desc="Memory Read";
157 WRITE, desc="Memory Write";
158 NULL, desc="Invalid";
159 }
160
161 enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
162 DATA, desc="DATA read";
163 ACK, desc="ACK write";
164 NULL, desc="Invalid";
165 }
166
167 structure(DMARequestMsg, desc="...", interface="Message") {
168 DMARequestType Type, desc="Request type (read/write)";
169 Addr PhysicalAddress, desc="Physical address for this request";
170 Addr LineAddress, desc="Line address for this request";
171 MachineID Requestor, desc="Node who initiated the request";
172 NetDest Destination, desc="Destination";
173 DataBlock DataBlk, desc="DataBlk attached to this request";
174 int Len, desc="The length of the request";
175 MessageSizeType MessageSize, desc="size category of the message";
176
177 bool functionalRead(Packet *pkt) {
178 return testAndRead(LineAddress, DataBlk, pkt);
179 }
180
181 bool functionalWrite(Packet *pkt) {
182 return testAndWrite(LineAddress, DataBlk, pkt);
183 }
184 }
185
186 structure(DMAResponseMsg, desc="...", interface="Message") {
187 DMAResponseType Type, desc="Response type (DATA/ACK)";
188 Addr PhysicalAddress, desc="Physical address for this request";
189 Addr LineAddress, desc="Line address for this request";
190 NetDest Destination, desc="Destination";
191 DataBlock DataBlk, desc="DataBlk attached to this request";
192 MessageSizeType MessageSize, desc="size category of the message";
193
194 bool functionalRead(Packet *pkt) {
195 return testAndRead(LineAddress, DataBlk, pkt);
196 }
197
198 bool functionalWrite(Packet *pkt) {
199 return testAndWrite(LineAddress, DataBlk, pkt);
200 }
201 }