3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
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17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34 machine(L1Cache, "MOSI Broadcast Optimized") {
36 MessageBuffer addressFromCache, network="To", virtual_network="0", ordered="true";
37 MessageBuffer dataFromCache, network="To", virtual_network="1", ordered="false";
39 MessageBuffer addressToCache, network="From", virtual_network="0", ordered="true";
40 MessageBuffer dataToCache, network="From", virtual_network="1", ordered="false";
44 enumeration(State, desc="Cache states", default="L1Cache_State_I") {
45 NP, desc="Not Present";
49 M, desc="Modified", format="!b";
50 IS_AD, "IS^AD", desc="idle, issued GETS, have not seen GETS or data yet";
51 IM_AD, "IM^AD", desc="idle, issued GETX, have not seen GETX or data yet";
52 SM_AD, "SM^AD",desc="shared, issued GETX, have not seen GETX or data yet";
53 OM_A, "OM^A",desc="owned, issued GETX, have not seen GETX yet", format="!b";
55 IS_A, "IS^A",desc="idle, issued GETS, have not seen GETS, have seen data";
56 IM_A, "IM^A",desc="idle, issued GETX, have not seen GETX, have seen data";
57 SM_A, "SM^A",desc="shared, issued GETX, have not seen GETX, have seen data", format="!b";
59 MI_A, "MI^A", desc="modified, issued PUTX, have not seen PUTX yet";
60 OI_A, "OI^A", desc="owned, issued PUTX, have not seen PUTX yet";
61 II_A, "II^A", desc="modified, issued PUTX, have not seen PUTX, then saw other GETX", format="!b";
63 IS_D, "IS^D", desc="idle, issued GETS, have seen GETS, have not seen data yet";
64 IS_D_I, "IS^D^I", desc="idle, issued GETS, have seen GETS, have not seen data, then saw other GETX";
65 IM_D, "IM^D", desc="idle, issued GETX, have seen GETX, have not seen data yet";
66 IM_D_O, "IM^D^O", desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
67 IM_D_I, "IM^D^I", desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETX";
68 IM_D_OI, "IM^D^OI", desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS, then saw other GETX";
69 SM_D, "SM^D", desc="shared, issued GETX, have seen GETX, have not seen data yet";
70 SM_D_O, "SM^D^O", desc="shared, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
75 enumeration(Event, desc="Cache events") {
77 Load, desc="Load request from the processor";
78 Ifetch, desc="I-fetch request from the processor";
79 Store, desc="Store request from the processor";
80 L1_to_L2, desc="L1 to L2 transfer";
81 L2_to_L1D, desc="L2 to L1-Data transfer";
82 L2_to_L1I, desc="L2 to L1-Instruction transfer";
83 L2_Replacement, desc="L2 Replacement";
85 // From Address network
86 Own_GETS, desc="Occurs when we observe our own GETS request in the global order";
87 Own_GET_INSTR, desc="Occurs when we observe our own GETInstr request in the global order";
88 Own_GETX, desc="Occurs when we observe our own GETX request in the global order";
89 Own_PUTX, desc="Occurs when we observe our own PUTX request in the global order", format="!r";
90 Other_GETS, desc="Occurs when we observe a GETS request from another processor";
91 Other_GET_INSTR, desc="Occurs when we observe a GETInstr request from another processor";
92 Other_GETX, desc="Occurs when we observe a GETX request from another processor";
93 Other_PUTX, desc="Occurs when we observe a PUTX request from another processor", format="!r";
96 Data, desc="Data for this block from the data network";
102 structure(Entry, desc="...", interface="AbstractCacheEntry") {
103 State CacheState, desc="cache state";
104 DataBlock DataBlk, desc="data for the block";
108 structure(TBE, desc="...") {
109 Address Address, desc="Physical address for this TBE";
110 State TBEState, desc="Transient state";
111 DataBlock DataBlk, desc="Buffer for the data block";
112 NetDest ForwardIDs, desc="IDs of the processors to forward the block";
113 Address ForwardAddress, desc="Address of request for forwarding";
117 external_type(CacheMemory) {
118 bool cacheAvail(Address);
119 Address cacheProbe(Address);
120 void allocate(Address);
121 void deallocate(Address);
122 Entry lookup(Address);
123 void changePermission(Address, AccessPermission);
124 bool isTagPresent(Address);
127 external_type(TBETable) {
129 void allocate(Address);
130 void deallocate(Address);
131 bool isPresent(Address);
134 TBETable TBEs, template_hack="<L1Cache_TBE>";
135 CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
136 CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
137 CacheMemory L2cacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L2"', abstract_chip_ptr="true";
139 MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
140 Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
141 StoreBuffer storeBuffer, abstract_chip_ptr="true", constructor_hack="i";
143 int cache_state_to_int(State state);
145 Entry getCacheEntry(Address addr), return_by_ref="yes" {
146 if (L2cacheMemory.isTagPresent(addr)) {
147 return L2cacheMemory[addr];
148 } else if (L1DcacheMemory.isTagPresent(addr)) {
149 return L1DcacheMemory[addr];
151 return L1IcacheMemory[addr];
155 void changePermission(Address addr, AccessPermission permission) {
156 if (L2cacheMemory.isTagPresent(addr)) {
157 return L2cacheMemory.changePermission(addr, permission);
158 } else if (L1DcacheMemory.isTagPresent(addr)) {
159 return L1DcacheMemory.changePermission(addr, permission);
161 return L1IcacheMemory.changePermission(addr, permission);
165 bool isCacheTagPresent(Address addr) {
166 return (L2cacheMemory.isTagPresent(addr) || L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
169 State getState(Address addr) {
170 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
171 assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
172 assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
174 if(TBEs.isPresent(addr)) {
175 return TBEs[addr].TBEState;
176 } else if (isCacheTagPresent(addr)) {
177 return getCacheEntry(addr).CacheState;
182 void setState(Address addr, State state) {
183 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
184 assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
185 assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
187 if (TBEs.isPresent(addr)) {
188 TBEs[addr].TBEState := state;
191 if (isCacheTagPresent(addr)) {
192 getCacheEntry(addr).CacheState := state;
195 if ((state == State:I) || (state == State:MI_A) || (state == State:II_A)) {
196 changePermission(addr, AccessPermission:Invalid);
197 } else if (state == State:S || state == State:O) {
198 changePermission(addr, AccessPermission:Read_Only);
199 } else if (state == State:M) {
200 changePermission(addr, AccessPermission:Read_Write);
202 changePermission(addr, AccessPermission:Busy);
207 Event mandatory_request_type_to_event(CacheRequestType type) {
208 if (type == CacheRequestType:LD) {
210 } else if (type == CacheRequestType:IFETCH) {
212 } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
215 error("Invalid CacheRequestType");
221 out_port(dataNetwork_out, DataMsg, dataFromCache);
222 out_port(addressNetwork_out, AddressMsg, addressFromCache);
227 in_port(dataNetwork_in, DataMsg, dataToCache) {
228 if (dataNetwork_in.isReady()) {
229 peek(dataNetwork_in, DataMsg) {
230 trigger(Event:Data, in_msg.Address);
236 in_port(addressNetwork_in, AddressMsg, addressToCache) {
237 if (addressNetwork_in.isReady()) {
238 peek(addressNetwork_in, AddressMsg) {
239 if (in_msg.Type == CoherenceRequestType:GETS) {
240 if (in_msg.Requestor == machineID) {
241 trigger(Event:Own_GETS, in_msg.Address);
243 trigger(Event:Other_GETS, in_msg.Address);
245 } else if (in_msg.Type == CoherenceRequestType:GETX) {
246 if (in_msg.Requestor == machineID) {
247 trigger(Event:Own_GETX, in_msg.Address);
249 trigger(Event:Other_GETX, in_msg.Address);
251 } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
252 if (in_msg.Requestor == machineID) {
253 trigger(Event:Own_GET_INSTR, in_msg.Address);
255 trigger(Event:Other_GET_INSTR, in_msg.Address);
257 } else if (in_msg.Type == CoherenceRequestType:PUTX) {
258 if (in_msg.Requestor == machineID) {
259 trigger(Event:Own_PUTX, in_msg.Address);
261 trigger(Event:Other_PUTX, in_msg.Address);
264 error("Unexpected message");
271 in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
272 if (mandatoryQueue_in.isReady()) {
273 peek(mandatoryQueue_in, CacheMsg) {
275 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
277 if (in_msg.Type == CacheRequestType:IFETCH) {
278 // ** INSTRUCTION ACCESS ***
280 // Check to see if it is in the OTHER L1
281 if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
282 // The block is in the wrong L1, try to write it to the L2
283 if (L2cacheMemory.cacheAvail(in_msg.Address)) {
284 trigger(Event:L1_to_L2, in_msg.Address);
286 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
288 } else if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
289 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
290 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
293 if (L1IcacheMemory.cacheAvail(in_msg.Address)) {
294 // L1 does't have the line, but we have space for it in the L1
295 if (L2cacheMemory.isTagPresent(in_msg.Address)) {
296 // L2 has it (maybe not with the right permissions)
297 trigger(Event:L2_to_L1I, in_msg.Address);
299 // We have room, the L2 doesn't have it, so the L1 fetches the line
300 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
303 // No room in the L1, so we need to make room
304 if (L2cacheMemory.cacheAvail(L1IcacheMemory.cacheProbe(in_msg.Address))) {
305 // The L2 has room, so we move the line from the L1 to the L2
306 trigger(Event:L1_to_L2, L1IcacheMemory.cacheProbe(in_msg.Address));
308 // The L2 does not have room, so we replace a line from the L2
309 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.Address)));
314 // *** DATA ACCESS ***
316 // Check to see if it is in the OTHER L1
317 if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
318 // The block is in the wrong L1, try to write it to the L2
319 if (L2cacheMemory.cacheAvail(in_msg.Address)) {
320 trigger(Event:L1_to_L2, in_msg.Address);
322 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
324 } else if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
325 // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
326 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
329 if (L1DcacheMemory.cacheAvail(in_msg.Address)) {
330 // L1 does't have the line, but we have space for it in the L1
331 if (L2cacheMemory.isTagPresent(in_msg.Address)) {
332 // L2 has it (maybe not with the right permissions)
333 trigger(Event:L2_to_L1D, in_msg.Address);
335 // We have room, the L2 doesn't have it, so the L1 fetches the line
336 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
339 // No room in the L1, so we need to make room
340 if (L2cacheMemory.cacheAvail(L1DcacheMemory.cacheProbe(in_msg.Address))) {
341 // The L2 has room, so we move the line from the L1 to the L2
342 trigger(Event:L1_to_L2, L1DcacheMemory.cacheProbe(in_msg.Address));
344 // The L2 does not have room, so we replace a line from the L2
345 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.Address)));
355 action(a_allocateTBE, "a", desc="Allocate TBE with Address=B, ForwardID=null, RetryCount=zero, ForwardIDRetryCount=zero, ForwardProgressBit=unset.") {
356 check_allocate(TBEs);
357 TBEs.allocate(address);
358 TBEs[address].ForwardIDs.clear();
360 // Keep the TBE state consistent with the cache state
361 if (isCacheTagPresent(address)) {
362 TBEs[address].TBEState := getCacheEntry(address).CacheState;
366 action(c_allocateL1DCacheBlock, "c", desc="Set L1 D-cache tag equal to tag of block B.") {
367 if (L1DcacheMemory.isTagPresent(address) == false) {
368 L1DcacheMemory.allocate(address);
372 action(c_allocateL1ICacheBlock, "c'", desc="Set L1 I-cache tag equal to tag of block B.") {
373 if (L1IcacheMemory.isTagPresent(address) == false) {
374 L1IcacheMemory.allocate(address);
378 action(cc_allocateL2CacheBlock, "\c", desc="Set L2 cache tag equal to tag of block B.") {
379 if (L2cacheMemory.isTagPresent(address) == false) {
380 L2cacheMemory.allocate(address);
384 action(d_deallocateTBE, "d", desc="Deallocate TBE.") {
385 TBEs.deallocate(address);
388 action(e_recordForwardingInfo, "e", desc="Record ID of other processor in ForwardID.") {
389 peek(addressNetwork_in, AddressMsg){
390 TBEs[address].ForwardIDs.add(in_msg.Requestor);
391 TBEs[address].ForwardAddress := in_msg.Address;
395 action(f_issueGETS, "f", desc="Issue GETS.") {
396 enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
397 out_msg.Address := address;
398 out_msg.Type := CoherenceRequestType:GETS;
399 out_msg.CacheState := cache_state_to_int(getState(address));
400 out_msg.Requestor := machineID;
401 out_msg.Destination.broadcast(MachineType:L1Cache);
402 out_msg.Destination.add(map_Address_to_Directory(address));
403 out_msg.MessageSize := MessageSizeType:Control;
407 action(g_issueGETX, "g", desc="Issue GETX.") {
408 enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
409 out_msg.Address := address;
410 out_msg.Type := CoherenceRequestType:GETX;
411 out_msg.CacheState := cache_state_to_int(getState(address));
412 out_msg.Requestor := machineID;
413 out_msg.Destination.broadcast(MachineType:L1Cache);
414 out_msg.Destination.add(map_Address_to_Directory(address));
415 out_msg.MessageSize := MessageSizeType:Control;
419 action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
420 DEBUG_EXPR(getCacheEntry(address).DataBlk);
421 sequencer.readCallback(address, getCacheEntry(address).DataBlk);
424 action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
425 DEBUG_EXPR(getCacheEntry(address).DataBlk);
426 sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
429 action(i_popAddressQueue, "i", desc="Pop incoming address queue.") {
430 addressNetwork_in.dequeue();
433 action(j_popDataQueue, "j", desc="Pop incoming data queue.") {
434 dataNetwork_in.dequeue();
437 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
438 mandatoryQueue_in.dequeue();
441 action(m_deallocateL1CacheBlock, "m", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
442 if (L1DcacheMemory.isTagPresent(address)) {
443 L1DcacheMemory.deallocate(address);
445 L1IcacheMemory.deallocate(address);
449 action(mm_deallocateL2CacheBlock, "\m", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
450 L2cacheMemory.deallocate(address);
453 action(n_copyFromL1toL2, "n", desc="Copy data block from L1 (I or D) to L2") {
454 if (L1DcacheMemory.isTagPresent(address)) {
455 L2cacheMemory[address].DataBlk := L1DcacheMemory[address].DataBlk;
457 L2cacheMemory[address].DataBlk := L1IcacheMemory[address].DataBlk;
461 action(nn_copyFromL2toL1, "\n", desc="Copy data block from L2 to L1 (I or D)") {
462 if (L1DcacheMemory.isTagPresent(address)) {
463 L1DcacheMemory[address].DataBlk := L2cacheMemory[address].DataBlk;
465 L1IcacheMemory[address].DataBlk := L2cacheMemory[address].DataBlk;
469 action(o_cacheToForward, "o", desc="Send data from the cache to the processor indicated by ForwardIDs.") {
470 peek(dataNetwork_in, DataMsg){
471 // This has a CACHE_RESPONSE_LATENCY latency because we want to avoid the
472 // timing strangeness that can occur if requests that source the
473 // data from the TBE are faster than data sourced from the cache
474 enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY"){
475 out_msg.Address := TBEs[address].ForwardAddress;
476 out_msg.Sender := machineID;
477 out_msg.DataBlk := getCacheEntry(address).DataBlk;
478 out_msg.Destination := TBEs[address].ForwardIDs;
479 out_msg.DestMachine := MachineType:L1Cache;
480 out_msg.MessageSize := MessageSizeType:Data;
485 action(p_issuePUTX, "p", desc="Issue PUTX.") {
486 enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
487 out_msg.Address := address;
488 out_msg.Type := CoherenceRequestType:PUTX;
489 out_msg.CacheState := cache_state_to_int(getState(address));
490 out_msg.Requestor := machineID;
491 out_msg.Destination.add(map_Address_to_Directory(address)); // To memory
492 out_msg.Destination.add(machineID); // Back to us
493 out_msg.DataBlk := getCacheEntry(address).DataBlk;
494 out_msg.MessageSize := MessageSizeType:Data;
498 action(q_writeDataFromCacheToTBE, "q", desc="Write data from the cache into the TBE.") {
499 TBEs[address].DataBlk := getCacheEntry(address).DataBlk;
500 DEBUG_EXPR(TBEs[address].DataBlk);
503 action(r_cacheToRequestor, "r", desc="Send data from the cache to the requestor") {
504 peek(addressNetwork_in, AddressMsg) {
505 enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") {
506 out_msg.Address := address;
507 out_msg.Sender := machineID;
508 out_msg.Destination.add(in_msg.Requestor);
509 out_msg.DestMachine := MachineType:L1Cache;
510 out_msg.DataBlk := getCacheEntry(address).DataBlk;
511 out_msg.MessageSize := MessageSizeType:Data;
513 DEBUG_EXPR(getCacheEntry(address).DataBlk);
517 action(s_saveDataInTBE, "s", desc="Save data in data field of TBE.") {
518 peek(dataNetwork_in, DataMsg) {
519 TBEs[address].DataBlk := in_msg.DataBlk;
520 DEBUG_EXPR(TBEs[address].DataBlk);
524 action(t_issueGET_INSTR, "t", desc="Issue GETInstr.") {
525 enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
526 out_msg.Address := address;
527 out_msg.Type := CoherenceRequestType:GET_INSTR;
528 out_msg.CacheState := cache_state_to_int(getState(address));
529 out_msg.Requestor := machineID;
530 out_msg.Destination.broadcast(MachineType:L1Cache);
531 out_msg.Destination.add(map_Address_to_Directory(address));
532 out_msg.MessageSize := MessageSizeType:Control;
536 action(w_writeDataFromTBEToCache, "w", desc="Write data from the TBE into the cache.") {
537 getCacheEntry(address).DataBlk := TBEs[address].DataBlk;
538 DEBUG_EXPR(getCacheEntry(address).DataBlk);
541 action(x_profileMiss, "x", desc="Profile the demand miss") {
542 peek(mandatoryQueue_in, CacheMsg) {
543 profile_miss(in_msg, id);
547 action(y_tbeToReq, "y", desc="Send data from the TBE to the requestor.") {
548 peek(addressNetwork_in, AddressMsg) {
549 enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") { // Either this or the PutX should have a real latency
550 out_msg.Address := address;
551 out_msg.Sender := machineID;
552 out_msg.Destination.add(in_msg.Requestor);
553 out_msg.DestMachine := MachineType:L1Cache;
554 out_msg.DataBlk := TBEs[address].DataBlk;
555 out_msg.MessageSize := MessageSizeType:Data;
560 // action(z_stall, "z", desc="Cannot be handled right now.") {
561 // Special name recognized as do nothing case
564 action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
565 mandatoryQueue_in.recycle();
570 // Transitions from Idle
571 transition({NP, I}, Load, IS_AD) {
573 c_allocateL1DCacheBlock;
579 transition({NP, I}, Ifetch, IS_AD) {
581 c_allocateL1ICacheBlock;
587 transition({NP, I}, Store, IM_AD) {
589 c_allocateL1DCacheBlock;
595 transition(I, L2_Replacement) {
596 mm_deallocateL2CacheBlock;
599 transition({NP, I}, { Other_GETS, Other_GET_INSTR, Other_GETX } ) {
603 // Transitions from Shared
604 transition(S, {Load,Ifetch}) {
609 transition(S, Store, SM_AD) {
616 transition(S, L2_Replacement, I) {
617 mm_deallocateL2CacheBlock;
620 transition(S, {Other_GETS, Other_GET_INSTR}) {
624 transition(S, Other_GETX, I) {
628 // Transitions from Owned
629 transition(O, {Load,Ifetch}) {
634 transition(O, Store, OM_A){
641 transition(O, L2_Replacement, OI_A) {
644 q_writeDataFromCacheToTBE;// the cache line is now empty
645 mm_deallocateL2CacheBlock;
648 transition(O, {Other_GETS,Other_GET_INSTR}) {
653 transition(O, Other_GETX, I) {
658 // Transitions from Modified
659 transition(M, {Load,Ifetch}) {
664 transition(M, Store) {
669 transition(M, L2_Replacement, MI_A) {
672 q_writeDataFromCacheToTBE;// the cache line is now empty
673 mm_deallocateL2CacheBlock;
676 transition(M, {Other_GETS,Other_GET_INSTR}, O) {
681 transition(M, Other_GETX, I) {
686 // Transitions moving data between the L1 and L2 caches
688 transition({I, S, O, M}, L1_to_L2) {
689 cc_allocateL2CacheBlock;
690 n_copyFromL1toL2; // Not really needed for state I
691 m_deallocateL1CacheBlock;
694 transition({I, S, O, M}, L2_to_L1D) {
695 c_allocateL1DCacheBlock;
696 nn_copyFromL2toL1; // Not really needed for state I
697 mm_deallocateL2CacheBlock;
700 transition({I, S, O, M}, L2_to_L1I) {
701 c_allocateL1ICacheBlock;
702 nn_copyFromL2toL1; // Not really needed for state I
703 mm_deallocateL2CacheBlock;
706 // Transitions for Load/Store/Replacement from transient states
708 transition({IS_AD, IM_AD, IS_A, IM_A, SM_AD, OM_A, SM_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O}, {Load, Ifetch, Store, L2_Replacement, L1_to_L2, L2_to_L1D, L2_to_L1I}) {
709 zz_recycleMandatoryQueue;
712 transition({MI_A, OI_A, II_A}, {Load, Ifetch, Store, L2_Replacement, L1_to_L2, L2_to_L1D, L2_to_L1I}) {
713 zz_recycleMandatoryQueue;
716 // Always ignore PUTXs which we are not the owner of
717 transition({NP, I, S, O, M, IS_AD, IM_AD, SM_AD, OM_A, IS_A, IM_A, SM_A, MI_A, OI_A, II_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O }, Other_PUTX) {
721 // transitions from IS_AD
723 transition(IS_AD, {Own_GETS,Own_GET_INSTR}, IS_D) {
726 transition(IS_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
729 transition(IS_AD, Data, IS_A) {
735 // Transitions from IM_AD
737 transition(IM_AD, Own_GETX, IM_D) {
740 transition(IM_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
743 transition(IM_AD, Data, IM_A) {
748 // Transitions from OM_A
750 transition(OM_A, Own_GETX, M){
756 transition(OM_A, {Other_GETS, Other_GET_INSTR}){
761 transition(OM_A, Other_GETX, IM_AD){
766 transition(OM_A, Data, IM_A) { // if we get data, we know we're going to lose block before we see own GETX
771 // Transitions from SM_AD
773 transition(SM_AD, Own_GETX, SM_D) {
776 transition(SM_AD, {Other_GETS,Other_GET_INSTR}) {
779 transition(SM_AD, Other_GETX, IM_AD) {
782 transition(SM_AD, Data, SM_A) {
788 // Transitions from IS_A
790 transition(IS_A, {Own_GETS,Own_GET_INSTR}, S) {
791 w_writeDataFromTBEToCache;
796 transition(IS_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
800 // Transitions from IM_A
802 transition(IM_A, Own_GETX, M) {
803 w_writeDataFromTBEToCache;
808 transition(IM_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
812 // Transitions from SM_A
814 transition(SM_A, Own_GETX, M) {
815 w_writeDataFromTBEToCache;
820 transition(SM_A, {Other_GETS,Other_GET_INSTR}) {
823 transition(SM_A, Other_GETX, IM_A) {
828 // Transitions from MI_A
830 transition(MI_A, Own_PUTX, I) {
835 transition(MI_A, {Other_GETS, Other_GET_INSTR}) {
840 transition(MI_A, Other_GETX, II_A) {
845 // Transitions from OI_A
847 transition(OI_A, Own_PUTX, I) {
852 transition(OI_A, {Other_GETS, Other_GET_INSTR}) {
857 transition(OI_A, Other_GETX, II_A) {
863 // Transitions from II_A
865 transition(II_A, Own_PUTX, I) {
870 transition(II_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
874 // Transitions from IS_D, IS_D_I
876 transition({IS_D, IS_D_I}, {Other_GETS,Other_GET_INSTR}) {
879 transition(IS_D, Other_GETX, IS_D_I) {
882 transition(IS_D_I, Other_GETX) {
885 transition(IS_D, Data, S) {
887 w_writeDataFromTBEToCache;
893 transition(IS_D_I, Data, I) {
895 w_writeDataFromTBEToCache;
901 // Transitions from IM_D, IM_D_O, IM_D_I, IM_D_OI
903 transition( IM_D, {Other_GETS,Other_GET_INSTR}, IM_D_O ) {
904 e_recordForwardingInfo;
908 transition( IM_D, Other_GETX, IM_D_I ) {
909 e_recordForwardingInfo;
913 transition(IM_D_O, {Other_GETS,Other_GET_INSTR} ) {
914 e_recordForwardingInfo;
918 transition(IM_D_O, Other_GETX, IM_D_OI) {
919 e_recordForwardingInfo;
923 transition( {IM_D_I, IM_D_OI}, {Other_GETS, Other_GET_INSTR, Other_GETX} ) {
927 transition(IM_D, Data, M) {
929 w_writeDataFromTBEToCache;
935 transition(IM_D_O, Data, O) {
937 w_writeDataFromTBEToCache;
944 transition(IM_D_I, Data, I) {
946 w_writeDataFromTBEToCache;
953 transition(IM_D_OI, Data, I) {
955 w_writeDataFromTBEToCache;
962 // Transitions for SM_D, SM_D_O
964 transition(SM_D, {Other_GETS,Other_GET_INSTR}, SM_D_O) {
965 e_recordForwardingInfo;
969 transition(SM_D, Other_GETX, IM_D_I) {
970 e_recordForwardingInfo;
974 transition(SM_D_O, {Other_GETS,Other_GET_INSTR}) {
975 e_recordForwardingInfo;
979 transition(SM_D_O, Other_GETX, IM_D_OI) {
980 e_recordForwardingInfo;
984 transition(SM_D, Data, M) {
986 w_writeDataFromTBEToCache;
992 transition(SM_D_O, Data, O) {
994 w_writeDataFromTBEToCache;