src/mem/protocol/MOSI_SMP_bcast-cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  */
  33
  34 machine(L1Cache, "MOSI Broadcast Optimized") {
  35
  36   MessageBuffer addressFromCache, network="To", virtual_network="0", ordered="true";
  37   MessageBuffer dataFromCache, network="To", virtual_network="1", ordered="false";
  38
  39   MessageBuffer addressToCache, network="From", virtual_network="0", ordered="true";
  40   MessageBuffer dataToCache, network="From", virtual_network="1", ordered="false";
  41
  42   // STATES
  43
  44   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  45     NP, desc="Not Present";
  46     I, desc="Idle";
  47     S, desc="Shared";
  48     O, desc="Owned";
  49     M, desc="Modified", format="!b";
  50     IS_AD, "IS^AD", desc="idle, issued GETS, have not seen GETS or data yet";
  51     IM_AD, "IM^AD", desc="idle, issued GETX, have not seen GETX or data yet";
  52     SM_AD, "SM^AD",desc="shared, issued GETX, have not seen GETX or data yet";
  53     OM_A, "OM^A",desc="owned, issued GETX, have not seen GETX yet", format="!b";
  54
  55     IS_A,  "IS^A",desc="idle, issued GETS, have not seen GETS, have seen data";
  56     IM_A,  "IM^A",desc="idle, issued GETX, have not seen GETX, have seen data";
  57     SM_A,  "SM^A",desc="shared, issued GETX, have not seen GETX, have seen data", format="!b";
  58
  59     MI_A,  "MI^A", desc="modified, issued PUTX, have not seen PUTX yet";
  60     OI_A,  "OI^A", desc="owned, issued PUTX, have not seen PUTX yet";
  61     II_A,  "II^A", desc="modified, issued PUTX, have not seen PUTX, then saw other GETX", format="!b";
  62
  63     IS_D,  "IS^D",  desc="idle, issued GETS, have seen GETS, have not seen data yet";
  64     IS_D_I,  "IS^D^I",  desc="idle, issued GETS, have seen GETS, have not seen data, then saw other GETX";
  65     IM_D,  "IM^D",  desc="idle, issued GETX, have seen GETX, have not seen data yet";
  66     IM_D_O,  "IM^D^O",  desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
  67     IM_D_I,  "IM^D^I",  desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETX";
  68     IM_D_OI,  "IM^D^OI",  desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS, then saw other GETX";
  69     SM_D,  "SM^D",  desc="shared, issued GETX, have seen GETX, have not seen data yet";
  70     SM_D_O,  "SM^D^O",  desc="shared, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
  71   }
  72
  73   // ** EVENTS **
  74
  75   enumeration(Event, desc="Cache events") {
  76     // From processor
  77     Load,            desc="Load request from the processor";
  78     Ifetch,          desc="I-fetch request from the processor";
  79     Store,           desc="Store request from the processor";
  80     L1_to_L2,        desc="L1 to L2 transfer";
  81     L2_to_L1D,       desc="L2 to L1-Data transfer";
  82     L2_to_L1I,       desc="L2 to L1-Instruction transfer";
  83     L2_Replacement,  desc="L2 Replacement";
  84
  85     // From Address network
  86     Own_GETS,        desc="Occurs when we observe our own GETS request in the global order";
  87     Own_GET_INSTR,   desc="Occurs when we observe our own GETInstr request in the global order";
  88     Own_GETX,        desc="Occurs when we observe our own GETX request in the global order";
  89     Own_PUTX,        desc="Occurs when we observe our own PUTX request in the global order", format="!r";
  90     Other_GETS,      desc="Occurs when we observe a GETS request from another processor";
  91     Other_GET_INSTR, desc="Occurs when we observe a GETInstr request from another processor";
  92     Other_GETX,      desc="Occurs when we observe a GETX request from another processor";
  93     Other_PUTX,      desc="Occurs when we observe a PUTX request from another processor", format="!r";
  94
  95     // From Data network
  96     Data,            desc="Data for this block from the data network";
  97   }
  98
  99   // TYPES
 100
 101   // CacheEntry
 102   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 103     State CacheState,       desc="cache state";
 104     DataBlock DataBlk,       desc="data for the block";
 105   }
 106
 107   // TBE fields
 108   structure(TBE, desc="...") {
 109     Address Address,                  desc="Physical address for this TBE";
 110     State TBEState,                   desc="Transient state";
 111     DataBlock DataBlk,                desc="Buffer for the data block";
 112     NetDest ForwardIDs,                   desc="IDs of the processors to forward the block";
 113     Address ForwardAddress,           desc="Address of request for forwarding";
 114   }
 115
 116
 117   external_type(CacheMemory) {
 118     bool cacheAvail(Address);
 119     Address cacheProbe(Address);
 120     void allocate(Address);
 121     void deallocate(Address);
 122     Entry lookup(Address);
 123     void changePermission(Address, AccessPermission);
 124     bool isTagPresent(Address);
 125   }
 126
 127   external_type(TBETable) {
 128     TBE lookup(Address);
 129     void allocate(Address);
 130     void deallocate(Address);
 131     bool isPresent(Address);
 132   }
 133
 134   TBETable TBEs, template_hack="<L1Cache_TBE>";
 135   CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
 136   CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
 137   CacheMemory L2cacheMemory,  template_hack="<L1Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L2"', abstract_chip_ptr="true";
 138
 139   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 140   Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
 141   StoreBuffer storeBuffer, abstract_chip_ptr="true", constructor_hack="i";
 142
 143   int cache_state_to_int(State state);
 144
 145   Entry getCacheEntry(Address addr), return_by_ref="yes" {
 146     if (L2cacheMemory.isTagPresent(addr)) {
 147       return L2cacheMemory[addr];
 148     } else if (L1DcacheMemory.isTagPresent(addr)) {
 149       return L1DcacheMemory[addr];
 150     } else {
 151       return L1IcacheMemory[addr];
 152     }
 153   }
 154
 155   void changePermission(Address addr, AccessPermission permission) {
 156     if (L2cacheMemory.isTagPresent(addr)) {
 157       return L2cacheMemory.changePermission(addr, permission);
 158     } else if (L1DcacheMemory.isTagPresent(addr)) {
 159       return L1DcacheMemory.changePermission(addr, permission);
 160     } else {
 161       return L1IcacheMemory.changePermission(addr, permission);
 162     }
 163   }
 164
 165   bool isCacheTagPresent(Address addr) {
 166     return (L2cacheMemory.isTagPresent(addr) || L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
 167   }
 168
 169   State getState(Address addr) {
 170     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 171     assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 172     assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 173
 174     if(TBEs.isPresent(addr)) {
 175       return TBEs[addr].TBEState;
 176     } else if (isCacheTagPresent(addr)) {
 177       return getCacheEntry(addr).CacheState;
 178     }
 179     return State:NP;
 180   }
 181
 182   void setState(Address addr, State state) {
 183     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 184     assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 185     assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
 186
 187     if (TBEs.isPresent(addr)) {
 188       TBEs[addr].TBEState := state;
 189     }
 190
 191     if (isCacheTagPresent(addr)) {
 192       getCacheEntry(addr).CacheState := state;
 193
 194       // Set permission
 195       if ((state == State:I) || (state == State:MI_A) || (state == State:II_A)) {
 196         changePermission(addr, AccessPermission:Invalid);
 197       } else if (state == State:S || state == State:O) {
 198         changePermission(addr, AccessPermission:Read_Only);
 199       } else if (state == State:M) {
 200         changePermission(addr, AccessPermission:Read_Write);
 201       } else {
 202         changePermission(addr, AccessPermission:Busy);
 203       }
 204     }
 205   }
 206
 207   Event mandatory_request_type_to_event(CacheRequestType type) {
 208     if (type == CacheRequestType:LD) {
 209       return Event:Load;
 210     } else if (type == CacheRequestType:IFETCH) {
 211       return Event:Ifetch;
 212     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 213       return Event:Store;
 214     } else {
 215       error("Invalid CacheRequestType");
 216     }
 217   }
 218
 219   // ** OUT_PORTS **
 220
 221   out_port(dataNetwork_out, DataMsg, dataFromCache);
 222   out_port(addressNetwork_out, AddressMsg, addressFromCache);
 223
 224   // ** IN_PORTS **
 225
 226   // Data Network
 227   in_port(dataNetwork_in, DataMsg, dataToCache) {
 228     if (dataNetwork_in.isReady()) {
 229       peek(dataNetwork_in, DataMsg) {
 230         trigger(Event:Data, in_msg.Address);
 231       }
 232     }
 233   }
 234
 235   // Address Network
 236   in_port(addressNetwork_in, AddressMsg, addressToCache) {
 237     if (addressNetwork_in.isReady()) {
 238       peek(addressNetwork_in, AddressMsg) {
 239         if (in_msg.Type == CoherenceRequestType:GETS) {
 240           if (in_msg.Requestor == machineID) {
 241             trigger(Event:Own_GETS, in_msg.Address);
 242           } else {
 243             trigger(Event:Other_GETS, in_msg.Address);
 244           }
 245         } else if (in_msg.Type == CoherenceRequestType:GETX) {
 246           if (in_msg.Requestor == machineID) {
 247             trigger(Event:Own_GETX, in_msg.Address);
 248           } else {
 249             trigger(Event:Other_GETX, in_msg.Address);
 250           }
 251         } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
 252           if (in_msg.Requestor == machineID) {
 253             trigger(Event:Own_GET_INSTR, in_msg.Address);
 254           } else {
 255             trigger(Event:Other_GET_INSTR, in_msg.Address);
 256           }
 257         } else if (in_msg.Type == CoherenceRequestType:PUTX) {
 258           if (in_msg.Requestor == machineID) {
 259             trigger(Event:Own_PUTX, in_msg.Address);
 260           } else {
 261             trigger(Event:Other_PUTX, in_msg.Address);
 262           }
 263         } else {
 264           error("Unexpected message");
 265         }
 266       }
 267     }
 268   }
 269
 270   // Mandatory Queue
 271   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 272     if (mandatoryQueue_in.isReady()) {
 273       peek(mandatoryQueue_in, CacheMsg) {
 274
 275         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 276
 277         if (in_msg.Type == CacheRequestType:IFETCH) {
 278           // ** INSTRUCTION ACCESS ***
 279
 280           // Check to see if it is in the OTHER L1
 281           if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
 282             // The block is in the wrong L1, try to write it to the L2
 283             if (L2cacheMemory.cacheAvail(in_msg.Address)) {
 284               trigger(Event:L1_to_L2, in_msg.Address);
 285             } else {
 286               trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
 287             }
 288           } else if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
 289             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 290             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
 291           } else {
 292             // not in any L1
 293             if (L1IcacheMemory.cacheAvail(in_msg.Address)) {
 294               // L1 does't have the line, but we have space for it in the L1
 295               if (L2cacheMemory.isTagPresent(in_msg.Address)) {
 296                 // L2 has it (maybe not with the right permissions)
 297                 trigger(Event:L2_to_L1I, in_msg.Address);
 298               } else {
 299                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 300                 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
 301               }
 302             } else {
 303               // No room in the L1, so we need to make room
 304               if (L2cacheMemory.cacheAvail(L1IcacheMemory.cacheProbe(in_msg.Address))) {
 305                 // The L2 has room, so we move the line from the L1 to the L2
 306                 trigger(Event:L1_to_L2, L1IcacheMemory.cacheProbe(in_msg.Address));
 307               } else {
 308                 // The L2 does not have room, so we replace a line from the L2
 309                 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.Address)));
 310               }
 311             }
 312           }
 313         } else {
 314           // *** DATA ACCESS ***
 315
 316           // Check to see if it is in the OTHER L1
 317           if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
 318             // The block is in the wrong L1, try to write it to the L2
 319             if (L2cacheMemory.cacheAvail(in_msg.Address)) {
 320               trigger(Event:L1_to_L2, in_msg.Address);
 321             } else {
 322               trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
 323             }
 324           } else if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
 325             // The tag matches for the L1, so the L1 fetches the line.  We know it can't be in the L2 due to exclusion
 326             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
 327           } else {
 328             // not in any L1
 329             if (L1DcacheMemory.cacheAvail(in_msg.Address)) {
 330               // L1 does't have the line, but we have space for it in the L1
 331               if (L2cacheMemory.isTagPresent(in_msg.Address)) {
 332                 // L2 has it (maybe not with the right permissions)
 333                 trigger(Event:L2_to_L1D, in_msg.Address);
 334               } else {
 335                 // We have room, the L2 doesn't have it, so the L1 fetches the line
 336                 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
 337               }
 338             } else {
 339               // No room in the L1, so we need to make room
 340               if (L2cacheMemory.cacheAvail(L1DcacheMemory.cacheProbe(in_msg.Address))) {
 341                 // The L2 has room, so we move the line from the L1 to the L2
 342                 trigger(Event:L1_to_L2, L1DcacheMemory.cacheProbe(in_msg.Address));
 343               } else {
 344                 // The L2 does not have room, so we replace a line from the L2
 345                 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.Address)));
 346               }
 347             }
 348           }
 349         }
 350       }
 351     }
 352   }
 353
 354   // ACTIONS
 355   action(a_allocateTBE, "a", desc="Allocate TBE with Address=B, ForwardID=null, RetryCount=zero, ForwardIDRetryCount=zero, ForwardProgressBit=unset.") {
 356     check_allocate(TBEs);
 357     TBEs.allocate(address);
 358     TBEs[address].ForwardIDs.clear();
 359
 360     // Keep the TBE state consistent with the cache state
 361     if (isCacheTagPresent(address)) {
 362       TBEs[address].TBEState := getCacheEntry(address).CacheState;
 363     }
 364   }
 365
 366   action(c_allocateL1DCacheBlock, "c", desc="Set L1 D-cache tag equal to tag of block B.") {
 367     if (L1DcacheMemory.isTagPresent(address) == false) {
 368       L1DcacheMemory.allocate(address);
 369     }
 370   }
 371
 372   action(c_allocateL1ICacheBlock, "c'", desc="Set L1 I-cache tag equal to tag of block B.") {
 373     if (L1IcacheMemory.isTagPresent(address) == false) {
 374       L1IcacheMemory.allocate(address);
 375     }
 376   }
 377
 378   action(cc_allocateL2CacheBlock, "\c", desc="Set L2 cache tag equal to tag of block B.") {
 379     if (L2cacheMemory.isTagPresent(address) == false) {
 380       L2cacheMemory.allocate(address);
 381     }
 382   }
 383
 384   action(d_deallocateTBE, "d", desc="Deallocate TBE.") {
 385     TBEs.deallocate(address);
 386   }
 387
 388   action(e_recordForwardingInfo, "e", desc="Record ID of other processor in ForwardID.") {
 389     peek(addressNetwork_in, AddressMsg){
 390       TBEs[address].ForwardIDs.add(in_msg.Requestor);
 391       TBEs[address].ForwardAddress := in_msg.Address;
 392     }
 393   }
 394
 395   action(f_issueGETS, "f", desc="Issue GETS.") {
 396     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 397       out_msg.Address := address;
 398       out_msg.Type := CoherenceRequestType:GETS;
 399       out_msg.CacheState := cache_state_to_int(getState(address));
 400       out_msg.Requestor := machineID;
 401       out_msg.Destination.broadcast(MachineType:L1Cache);
 402       out_msg.Destination.add(map_Address_to_Directory(address));
 403       out_msg.MessageSize := MessageSizeType:Control;
 404     }
 405   }
 406
 407   action(g_issueGETX, "g", desc="Issue GETX.") {
 408     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 409       out_msg.Address := address;
 410       out_msg.Type := CoherenceRequestType:GETX;
 411       out_msg.CacheState := cache_state_to_int(getState(address));
 412       out_msg.Requestor := machineID;
 413       out_msg.Destination.broadcast(MachineType:L1Cache);
 414       out_msg.Destination.add(map_Address_to_Directory(address));
 415       out_msg.MessageSize := MessageSizeType:Control;
 416     }
 417   }
 418
 419   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 420     DEBUG_EXPR(getCacheEntry(address).DataBlk);
 421     sequencer.readCallback(address, getCacheEntry(address).DataBlk);
 422   }
 423
 424   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 425     DEBUG_EXPR(getCacheEntry(address).DataBlk);
 426     sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
 427   }
 428
 429   action(i_popAddressQueue, "i", desc="Pop incoming address queue.") {
 430     addressNetwork_in.dequeue();
 431   }
 432
 433   action(j_popDataQueue, "j", desc="Pop incoming data queue.") {
 434     dataNetwork_in.dequeue();
 435   }
 436
 437   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 438     mandatoryQueue_in.dequeue();
 439   }
 440
 441   action(m_deallocateL1CacheBlock, "m", desc="Deallocate L1 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 442     if (L1DcacheMemory.isTagPresent(address)) {
 443       L1DcacheMemory.deallocate(address);
 444     } else {
 445       L1IcacheMemory.deallocate(address);
 446     }
 447   }
 448
 449   action(mm_deallocateL2CacheBlock, "\m", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 450     L2cacheMemory.deallocate(address);
 451   }
 452
 453   action(n_copyFromL1toL2, "n", desc="Copy data block from L1 (I or D) to L2") {
 454     if (L1DcacheMemory.isTagPresent(address)) {
 455       L2cacheMemory[address].DataBlk := L1DcacheMemory[address].DataBlk;
 456     } else {
 457       L2cacheMemory[address].DataBlk := L1IcacheMemory[address].DataBlk;
 458     }
 459   }
 460
 461   action(nn_copyFromL2toL1, "\n", desc="Copy data block from L2 to L1 (I or D)") {
 462     if (L1DcacheMemory.isTagPresent(address)) {
 463       L1DcacheMemory[address].DataBlk := L2cacheMemory[address].DataBlk;
 464     } else {
 465       L1IcacheMemory[address].DataBlk := L2cacheMemory[address].DataBlk;
 466     }
 467   }
 468
 469   action(o_cacheToForward, "o", desc="Send data from the cache to the processor indicated by ForwardIDs.") {
 470     peek(dataNetwork_in, DataMsg){
 471       // This has a CACHE_RESPONSE_LATENCY latency because we want to avoid the
 472       // timing strangeness that can occur if requests that source the
 473       // data from the TBE are faster than data sourced from the cache
 474       enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY"){
 475         out_msg.Address := TBEs[address].ForwardAddress;
 476         out_msg.Sender := machineID;
 477         out_msg.DataBlk := getCacheEntry(address).DataBlk;
 478         out_msg.Destination := TBEs[address].ForwardIDs;
 479         out_msg.DestMachine := MachineType:L1Cache;
 480         out_msg.MessageSize := MessageSizeType:Data;
 481       }
 482     }
 483   }
 484
 485   action(p_issuePUTX, "p", desc="Issue PUTX.") {
 486     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 487       out_msg.Address := address;
 488       out_msg.Type := CoherenceRequestType:PUTX;
 489       out_msg.CacheState := cache_state_to_int(getState(address));
 490       out_msg.Requestor := machineID;
 491       out_msg.Destination.add(map_Address_to_Directory(address));  // To memory
 492       out_msg.Destination.add(machineID);  // Back to us
 493       out_msg.DataBlk := getCacheEntry(address).DataBlk;
 494       out_msg.MessageSize := MessageSizeType:Data;
 495     }
 496   }
 497
 498   action(q_writeDataFromCacheToTBE, "q", desc="Write data from the cache into the TBE.") {
 499     TBEs[address].DataBlk := getCacheEntry(address).DataBlk;
 500     DEBUG_EXPR(TBEs[address].DataBlk);
 501   }
 502
 503   action(r_cacheToRequestor, "r", desc="Send data from the cache to the requestor") {
 504     peek(addressNetwork_in, AddressMsg) {
 505       enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") {
 506         out_msg.Address := address;
 507         out_msg.Sender := machineID;
 508         out_msg.Destination.add(in_msg.Requestor);
 509         out_msg.DestMachine := MachineType:L1Cache;
 510         out_msg.DataBlk := getCacheEntry(address).DataBlk;
 511         out_msg.MessageSize := MessageSizeType:Data;
 512       }
 513       DEBUG_EXPR(getCacheEntry(address).DataBlk);
 514     }
 515   }
 516
 517   action(s_saveDataInTBE, "s", desc="Save data in data field of TBE.") {
 518     peek(dataNetwork_in, DataMsg) {
 519       TBEs[address].DataBlk := in_msg.DataBlk;
 520       DEBUG_EXPR(TBEs[address].DataBlk);
 521     }
 522   }
 523
 524   action(t_issueGET_INSTR, "t", desc="Issue GETInstr.") {
 525     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 526       out_msg.Address := address;
 527       out_msg.Type := CoherenceRequestType:GET_INSTR;
 528       out_msg.CacheState := cache_state_to_int(getState(address));
 529       out_msg.Requestor := machineID;
 530       out_msg.Destination.broadcast(MachineType:L1Cache);
 531       out_msg.Destination.add(map_Address_to_Directory(address));
 532       out_msg.MessageSize := MessageSizeType:Control;
 533     }
 534   }
 535
 536   action(w_writeDataFromTBEToCache, "w", desc="Write data from the TBE into the cache.") {
 537     getCacheEntry(address).DataBlk := TBEs[address].DataBlk;
 538     DEBUG_EXPR(getCacheEntry(address).DataBlk);
 539   }
 540
 541   action(x_profileMiss, "x", desc="Profile the demand miss") {
 542     peek(mandatoryQueue_in, CacheMsg) {
 543       profile_miss(in_msg, id);
 544     }
 545   }
 546
 547   action(y_tbeToReq, "y", desc="Send data from the TBE to the requestor.") {
 548     peek(addressNetwork_in, AddressMsg) {
 549       enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") {  // Either this or the PutX should have a real latency
 550         out_msg.Address := address;
 551         out_msg.Sender := machineID;
 552         out_msg.Destination.add(in_msg.Requestor);
 553         out_msg.DestMachine := MachineType:L1Cache;
 554         out_msg.DataBlk := TBEs[address].DataBlk;
 555         out_msg.MessageSize := MessageSizeType:Data;
 556       }
 557     }
 558   }
 559
 560   //  action(z_stall, "z", desc="Cannot be handled right now.") {
 561     // Special name recognized as do nothing case
 562   //  }
 563
 564   action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
 565     mandatoryQueue_in.recycle();
 566   }
 567
 568   // TRANSITIONS
 569
 570   // Transitions from Idle
 571   transition({NP, I}, Load, IS_AD) {
 572     f_issueGETS;
 573     c_allocateL1DCacheBlock;
 574     a_allocateTBE;
 575     x_profileMiss;
 576     k_popMandatoryQueue;
 577   }
 578
 579   transition({NP, I}, Ifetch, IS_AD) {
 580     t_issueGET_INSTR;
 581     c_allocateL1ICacheBlock;
 582     a_allocateTBE;
 583     x_profileMiss;
 584     k_popMandatoryQueue;
 585   }
 586
 587   transition({NP, I}, Store, IM_AD) {
 588     g_issueGETX;
 589     c_allocateL1DCacheBlock;
 590     a_allocateTBE;
 591     x_profileMiss;
 592     k_popMandatoryQueue;
 593   }
 594
 595   transition(I, L2_Replacement) {
 596     mm_deallocateL2CacheBlock;
 597   }
 598
 599   transition({NP, I}, { Other_GETS, Other_GET_INSTR, Other_GETX } ) {
 600     i_popAddressQueue;
 601   }
 602
 603   // Transitions from Shared
 604   transition(S, {Load,Ifetch}) {
 605     h_load_hit;
 606     k_popMandatoryQueue;
 607   }
 608
 609   transition(S, Store, SM_AD) {
 610     g_issueGETX;
 611     a_allocateTBE;
 612     x_profileMiss;
 613     k_popMandatoryQueue;
 614   }
 615
 616   transition(S, L2_Replacement, I) {
 617     mm_deallocateL2CacheBlock;
 618   }
 619
 620   transition(S, {Other_GETS, Other_GET_INSTR}) {
 621     i_popAddressQueue;
 622   }
 623
 624   transition(S, Other_GETX, I) {
 625     i_popAddressQueue;
 626   }
 627
 628   // Transitions from Owned
 629   transition(O, {Load,Ifetch}) {
 630     h_load_hit;
 631     k_popMandatoryQueue;
 632   }
 633
 634   transition(O, Store, OM_A){
 635     g_issueGETX;
 636     a_allocateTBE;
 637     x_profileMiss;
 638     k_popMandatoryQueue;
 639   }
 640
 641   transition(O, L2_Replacement, OI_A) {
 642     p_issuePUTX;
 643     a_allocateTBE;
 644     q_writeDataFromCacheToTBE;// the cache line is now empty
 645     mm_deallocateL2CacheBlock;
 646   }
 647
 648   transition(O, {Other_GETS,Other_GET_INSTR}) {
 649     r_cacheToRequestor;
 650     i_popAddressQueue;
 651   }
 652
 653   transition(O, Other_GETX, I) {
 654     r_cacheToRequestor;
 655     i_popAddressQueue;
 656   }
 657
 658   // Transitions from Modified
 659   transition(M, {Load,Ifetch}) {
 660     h_load_hit;
 661     k_popMandatoryQueue;
 662   }
 663
 664   transition(M, Store) {
 665     hh_store_hit;
 666     k_popMandatoryQueue;
 667   }
 668
 669   transition(M, L2_Replacement, MI_A) {
 670     p_issuePUTX;
 671     a_allocateTBE;
 672     q_writeDataFromCacheToTBE;// the cache line is now empty
 673     mm_deallocateL2CacheBlock;
 674   }
 675
 676   transition(M, {Other_GETS,Other_GET_INSTR}, O) {
 677     r_cacheToRequestor;
 678     i_popAddressQueue;
 679   }
 680
 681   transition(M, Other_GETX, I) {
 682     r_cacheToRequestor;
 683     i_popAddressQueue;
 684   }
 685
 686   // Transitions moving data between the L1 and L2 caches
 687
 688   transition({I, S, O, M}, L1_to_L2) {
 689     cc_allocateL2CacheBlock;
 690     n_copyFromL1toL2; // Not really needed for state I
 691     m_deallocateL1CacheBlock;
 692   }
 693
 694   transition({I, S, O, M}, L2_to_L1D) {
 695     c_allocateL1DCacheBlock;
 696     nn_copyFromL2toL1; // Not really needed for state I
 697     mm_deallocateL2CacheBlock;
 698   }
 699
 700   transition({I, S, O, M}, L2_to_L1I) {
 701     c_allocateL1ICacheBlock;
 702     nn_copyFromL2toL1; // Not really needed for state I
 703     mm_deallocateL2CacheBlock;
 704   }
 705
 706   // Transitions for Load/Store/Replacement from transient states
 707
 708   transition({IS_AD, IM_AD, IS_A, IM_A, SM_AD, OM_A, SM_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O}, {Load, Ifetch, Store, L2_Replacement, L1_to_L2, L2_to_L1D, L2_to_L1I}) {
 709     zz_recycleMandatoryQueue;
 710   }
 711
 712   transition({MI_A, OI_A, II_A}, {Load, Ifetch, Store, L2_Replacement, L1_to_L2, L2_to_L1D, L2_to_L1I}) {
 713     zz_recycleMandatoryQueue;
 714   }
 715
 716   // Always ignore PUTXs which we are not the owner of
 717   transition({NP, I, S, O, M, IS_AD, IM_AD, SM_AD, OM_A, IS_A, IM_A, SM_A, MI_A, OI_A, II_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O }, Other_PUTX) {
 718     i_popAddressQueue;
 719   }
 720
 721   // transitions from IS_AD
 722
 723   transition(IS_AD, {Own_GETS,Own_GET_INSTR}, IS_D) {
 724     i_popAddressQueue;
 725   }
 726   transition(IS_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 727     i_popAddressQueue;
 728   }
 729   transition(IS_AD, Data, IS_A) {
 730     s_saveDataInTBE;
 731     j_popDataQueue;
 732   }
 733
 734
 735   // Transitions from IM_AD
 736
 737   transition(IM_AD, Own_GETX, IM_D) {
 738     i_popAddressQueue;
 739   }
 740   transition(IM_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 741     i_popAddressQueue;
 742   }
 743   transition(IM_AD, Data, IM_A) {
 744     s_saveDataInTBE;
 745     j_popDataQueue;
 746   }
 747
 748   // Transitions from OM_A
 749
 750   transition(OM_A, Own_GETX, M){
 751     hh_store_hit;
 752     d_deallocateTBE;
 753     i_popAddressQueue;
 754   }
 755
 756   transition(OM_A, {Other_GETS, Other_GET_INSTR}){
 757     r_cacheToRequestor;
 758     i_popAddressQueue;
 759   }
 760
 761   transition(OM_A, Other_GETX, IM_AD){
 762     r_cacheToRequestor;
 763     i_popAddressQueue;
 764   }
 765
 766   transition(OM_A, Data, IM_A) {  // if we get data, we know we're going to lose block before we see own GETX
 767     s_saveDataInTBE;
 768     j_popDataQueue;
 769   }
 770
 771   // Transitions from SM_AD
 772
 773   transition(SM_AD, Own_GETX, SM_D) {
 774     i_popAddressQueue;
 775   }
 776   transition(SM_AD, {Other_GETS,Other_GET_INSTR}) {
 777     i_popAddressQueue;
 778   }
 779   transition(SM_AD, Other_GETX, IM_AD) {
 780     i_popAddressQueue;
 781   }
 782   transition(SM_AD, Data, SM_A) {
 783     s_saveDataInTBE;
 784     j_popDataQueue;
 785   }
 786
 787
 788   // Transitions from IS_A
 789
 790   transition(IS_A, {Own_GETS,Own_GET_INSTR}, S) {
 791     w_writeDataFromTBEToCache;
 792     h_load_hit;
 793     d_deallocateTBE;
 794     i_popAddressQueue;
 795   }
 796   transition(IS_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 797     i_popAddressQueue;
 798   }
 799
 800   // Transitions from IM_A
 801
 802   transition(IM_A, Own_GETX, M) {
 803     w_writeDataFromTBEToCache;
 804     hh_store_hit;
 805     d_deallocateTBE;
 806     i_popAddressQueue;
 807   }
 808   transition(IM_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 809     i_popAddressQueue;
 810   }
 811
 812   // Transitions from SM_A
 813
 814   transition(SM_A, Own_GETX, M) {
 815     w_writeDataFromTBEToCache;
 816     hh_store_hit;
 817     d_deallocateTBE;
 818     i_popAddressQueue;
 819   }
 820   transition(SM_A, {Other_GETS,Other_GET_INSTR}) {
 821     i_popAddressQueue;
 822   }
 823   transition(SM_A, Other_GETX, IM_A) {
 824     i_popAddressQueue;
 825   }
 826
 827
 828   // Transitions from MI_A
 829
 830   transition(MI_A, Own_PUTX, I) {
 831     d_deallocateTBE;
 832     i_popAddressQueue;
 833   }
 834
 835   transition(MI_A, {Other_GETS, Other_GET_INSTR}) {
 836     y_tbeToReq;
 837     i_popAddressQueue;
 838   }
 839
 840   transition(MI_A, Other_GETX, II_A) {
 841     y_tbeToReq;
 842     i_popAddressQueue;
 843   }
 844
 845   // Transitions from OI_A
 846
 847   transition(OI_A, Own_PUTX, I) {
 848     d_deallocateTBE;
 849     i_popAddressQueue;
 850   }
 851
 852   transition(OI_A, {Other_GETS, Other_GET_INSTR}) {
 853     y_tbeToReq;
 854     i_popAddressQueue;
 855   }
 856
 857   transition(OI_A, Other_GETX, II_A) {
 858     y_tbeToReq;
 859     i_popAddressQueue;
 860   }
 861
 862
 863   // Transitions from II_A
 864
 865   transition(II_A, Own_PUTX, I) {
 866     d_deallocateTBE;
 867     i_popAddressQueue;
 868   }
 869
 870   transition(II_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 871     i_popAddressQueue;
 872   }
 873
 874   // Transitions from IS_D, IS_D_I
 875
 876   transition({IS_D, IS_D_I}, {Other_GETS,Other_GET_INSTR}) {
 877     i_popAddressQueue;
 878   }
 879   transition(IS_D, Other_GETX, IS_D_I) {
 880     i_popAddressQueue;
 881   }
 882   transition(IS_D_I, Other_GETX) {
 883     i_popAddressQueue;
 884   }
 885   transition(IS_D, Data, S) {
 886     s_saveDataInTBE;
 887     w_writeDataFromTBEToCache;
 888     h_load_hit;
 889     d_deallocateTBE;
 890     j_popDataQueue;
 891   }
 892
 893   transition(IS_D_I, Data, I) {
 894     s_saveDataInTBE;
 895     w_writeDataFromTBEToCache;
 896     h_load_hit;
 897     d_deallocateTBE;
 898     j_popDataQueue;
 899   }
 900
 901   // Transitions from IM_D, IM_D_O, IM_D_I, IM_D_OI
 902
 903   transition( IM_D, {Other_GETS,Other_GET_INSTR}, IM_D_O ) {
 904     e_recordForwardingInfo;
 905     i_popAddressQueue;
 906   }
 907
 908   transition( IM_D, Other_GETX, IM_D_I ) {
 909     e_recordForwardingInfo;
 910     i_popAddressQueue;
 911   }
 912
 913   transition(IM_D_O, {Other_GETS,Other_GET_INSTR} ) {
 914     e_recordForwardingInfo;
 915     i_popAddressQueue;
 916   }
 917
 918   transition(IM_D_O, Other_GETX, IM_D_OI) {
 919     e_recordForwardingInfo;
 920     i_popAddressQueue;
 921   }
 922
 923   transition( {IM_D_I, IM_D_OI}, {Other_GETS, Other_GET_INSTR, Other_GETX} ) {
 924     i_popAddressQueue;
 925   }
 926
 927   transition(IM_D, Data, M) {
 928     s_saveDataInTBE;
 929     w_writeDataFromTBEToCache;
 930     hh_store_hit;
 931     d_deallocateTBE;
 932     j_popDataQueue;
 933   }
 934
 935   transition(IM_D_O, Data, O) {
 936     s_saveDataInTBE;
 937     w_writeDataFromTBEToCache;
 938     hh_store_hit;
 939     o_cacheToForward;
 940     d_deallocateTBE;
 941     j_popDataQueue;
 942    }
 943
 944   transition(IM_D_I, Data, I) {
 945     s_saveDataInTBE;
 946     w_writeDataFromTBEToCache;
 947     hh_store_hit;
 948     o_cacheToForward;
 949     d_deallocateTBE;
 950     j_popDataQueue;
 951   }
 952
 953   transition(IM_D_OI, Data, I) {
 954     s_saveDataInTBE;
 955     w_writeDataFromTBEToCache;
 956     hh_store_hit;
 957     o_cacheToForward;
 958     d_deallocateTBE;
 959     j_popDataQueue;
 960   }
 961
 962   // Transitions for SM_D, SM_D_O
 963
 964   transition(SM_D, {Other_GETS,Other_GET_INSTR}, SM_D_O) {
 965     e_recordForwardingInfo;
 966     i_popAddressQueue;
 967   }
 968
 969   transition(SM_D, Other_GETX, IM_D_I) {
 970     e_recordForwardingInfo;
 971     i_popAddressQueue;
 972   }
 973
 974   transition(SM_D_O, {Other_GETS,Other_GET_INSTR}) {
 975     e_recordForwardingInfo;
 976     i_popAddressQueue;
 977   }
 978
 979   transition(SM_D_O, Other_GETX, IM_D_OI) {
 980     e_recordForwardingInfo;
 981     i_popAddressQueue;
 982   }
 983
 984   transition(SM_D, Data, M) {
 985     s_saveDataInTBE;
 986     w_writeDataFromTBEToCache;
 987     hh_store_hit;
 988     d_deallocateTBE;
 989     j_popDataQueue;
 990   }
 991
 992   transition(SM_D_O, Data, O) {
 993     s_saveDataInTBE;
 994     w_writeDataFromTBEToCache;
 995     hh_store_hit;
 996     o_cacheToForward;
 997     d_deallocateTBE;
 998     j_popDataQueue;
 999   }
1000 }