src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  */
  33
  34 machine(L1Cache, "MOSI Broadcast Optimized") {
  35
  36   MessageBuffer addressFromCache, network="To", virtual_network="0", ordered="true";
  37   MessageBuffer dataFromCache, network="To", virtual_network="1", ordered="false";
  38
  39   MessageBuffer addressToCache, network="From", virtual_network="0", ordered="true";
  40   MessageBuffer dataToCache, network="From", virtual_network="1", ordered="false";
  41
  42   // STATES
  43
  44   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  45     NP, desc="Not Present";
  46     I, desc="Idle";
  47     S, desc="Shared";
  48     O, desc="Owned";
  49     M, desc="Modified", format="!b";
  50     IS_AD, "IS^AD", desc="idle, issued GETS, have not seen GETS or data yet";
  51     IM_AD, "IM^AD", desc="idle, issued GETX, have not seen GETX or data yet";
  52     SM_AD, "SM^AD",desc="shared, issued GETX, have not seen GETX or data yet";
  53     OM_A, "OM^A",desc="owned, issued GETX, have not seen GETX yet", format="!b";
  54
  55     IS_A,  "IS^A",desc="idle, issued GETS, have not seen GETS, have seen data";
  56     IM_A,  "IM^A",desc="idle, issued GETX, have not seen GETX, have seen data";
  57     SM_A,  "SM^A",desc="shared, issued GETX, have not seen GETX, have seen data", format="!b";
  58
  59     MI_A,  "MI^A", desc="modified, issued PUTX, have not seen PUTX yet";
  60     OI_A,  "OI^A", desc="owned, issued PUTX, have not seen PUTX yet";
  61     II_A,  "II^A", desc="modified, issued PUTX, have not seen PUTX, then saw other GETX", format="!b";
  62
  63     IS_D,  "IS^D",  desc="idle, issued GETS, have seen GETS, have not seen data yet";
  64     IS_D_I,  "IS^D^I",  desc="idle, issued GETS, have seen GETS, have not seen data, then saw other GETX";
  65     IM_D,  "IM^D",  desc="idle, issued GETX, have seen GETX, have not seen data yet";
  66     IM_D_O,  "IM^D^O",  desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
  67     IM_D_I,  "IM^D^I",  desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETX";
  68     IM_D_OI,  "IM^D^OI",  desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS, then saw other GETX";
  69     SM_D,  "SM^D",  desc="shared, issued GETX, have seen GETX, have not seen data yet";
  70     SM_D_O,  "SM^D^O",  desc="shared, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
  71   }
  72
  73   // ** EVENTS **
  74
  75   enumeration(Event, desc="Cache events") {
  76     // From processor
  77     Load,            desc="Load request from the processor";
  78     Ifetch,          desc="I-fetch request from the processor";
  79     Store,           desc="Store request from the processor";
  80     Replacement,     desc="Replacement";
  81     Load_prefetch,   desc="Read only prefetch";
  82     Store_prefetch,  desc="Read write prefetch", format="!r";
  83
  84     // From Address network
  85     Own_GETS,        desc="Occurs when we observe our own GETS request in the global order";
  86     Own_GET_INSTR,   desc="Occurs when we observe our own GETInstr request in the global order";
  87     Own_GETX,        desc="Occurs when we observe our own GETX request in the global order";
  88     Own_PUTX,        desc="Occurs when we observe our own PUTX request in the global order", format="!r";
  89     Other_GETS,      desc="Occurs when we observe a GETS request from another processor";
  90     Other_GET_INSTR, desc="Occurs when we observe a GETInstr request from another processor";
  91     Other_GETX,      desc="Occurs when we observe a GETX request from another processor";
  92     Other_PUTX,      desc="Occurs when we observe a PUTX request from another processor", format="!r";
  93
  94     // From Data network
  95     Data,            desc="Data for this block from the data network";
  96   }
  97
  98   // TYPES
  99
 100   // CacheEntry
 101   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 102     State CacheState,       desc="cache state";
 103     DataBlock DataBlk,       desc="data for the block";
 104   }
 105
 106   // TBE fields
 107   structure(TBE, desc="...") {
 108     Address Address,                  desc="Physical address for this TBE";
 109     State TBEState,                   desc="Transient state";
 110     DataBlock DataBlk,                desc="Buffer for the data block";
 111     NetDest ForwardIDs,                   desc="IDs of the processors to forward the block";
 112     Address ForwardAddress,           desc="Address of request for forwarding";
 113     bool isPrefetch,                  desc="Set if this request is a prefetch";
 114   }
 115
 116   external_type(CacheMemory) {
 117     bool cacheAvail(Address);
 118     Address cacheProbe(Address);
 119     void allocate(Address);
 120     void deallocate(Address);
 121     Entry lookup(Address);
 122     void changePermission(Address, AccessPermission);
 123     bool isTagPresent(Address);
 124   }
 125
 126   external_type(TBETable) {
 127     TBE lookup(Address);
 128     void allocate(Address);
 129     void deallocate(Address);
 130     bool isPresent(Address);
 131   }
 132
 133   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 134   MessageBuffer optionalQueue, ordered="true", abstract_chip_ptr="true";
 135   Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
 136   StoreBuffer storeBuffer, abstract_chip_ptr="true", constructor_hack="i";
 137
 138
 139   TBETable TBEs, template_hack="<L1Cache_TBE>";
 140   CacheMemory cacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_unified"', abstract_chip_ptr="true";
 141
 142   int cache_state_to_int(State state);
 143
 144   State getState(Address addr) {
 145     if(TBEs.isPresent(addr)) {
 146       return TBEs[addr].TBEState;
 147     } else if (cacheMemory.isTagPresent(addr)) {
 148       return cacheMemory[addr].CacheState;
 149     }
 150     return State:NP;
 151   }
 152
 153   void setState(Address addr, State state) {
 154     if (TBEs.isPresent(addr)) {
 155       TBEs[addr].TBEState := state;
 156     }
 157     if (cacheMemory.isTagPresent(addr)) {
 158       cacheMemory[addr].CacheState := state;
 159
 160       // Set permission
 161       if ((state == State:I) || (state == State:MI_A) || (state == State:II_A)) {
 162         cacheMemory.changePermission(addr, AccessPermission:Invalid);
 163       } else if (state == State:S || state == State:O) {
 164         cacheMemory.changePermission(addr, AccessPermission:Read_Only);
 165       } else if (state == State:M) {
 166         cacheMemory.changePermission(addr, AccessPermission:Read_Write);
 167       } else {
 168         cacheMemory.changePermission(addr, AccessPermission:Busy);
 169       }
 170     }
 171   }
 172
 173   // ** OUT_PORTS **
 174
 175   out_port(dataNetwork_out, DataMsg, dataFromCache);
 176   out_port(addressNetwork_out, AddressMsg, addressFromCache);
 177
 178   // ** IN_PORTS **
 179
 180   // Data Network
 181   in_port(dataNetwork_in, DataMsg, dataToCache) {
 182     if (dataNetwork_in.isReady()) {
 183       peek(dataNetwork_in, DataMsg) {
 184         trigger(Event:Data, in_msg.Address);
 185       }
 186     }
 187   }
 188
 189   // Address Network
 190   in_port(addressNetwork_in, AddressMsg, addressToCache) {
 191     if (addressNetwork_in.isReady()) {
 192       peek(addressNetwork_in, AddressMsg) {
 193         if (in_msg.Type == CoherenceRequestType:GETS) {
 194           if (in_msg.Requestor == machineID) {
 195             trigger(Event:Own_GETS, in_msg.Address);
 196           } else {
 197             trigger(Event:Other_GETS, in_msg.Address);
 198           }
 199         } else if (in_msg.Type == CoherenceRequestType:GETX) {
 200           if (in_msg.Requestor == machineID) {
 201             trigger(Event:Own_GETX, in_msg.Address);
 202           } else {
 203             trigger(Event:Other_GETX, in_msg.Address);
 204           }
 205         } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
 206           if (in_msg.Requestor == machineID) {
 207             trigger(Event:Own_GET_INSTR, in_msg.Address);
 208           } else {
 209             trigger(Event:Other_GET_INSTR, in_msg.Address);
 210           }
 211         } else if (in_msg.Type == CoherenceRequestType:PUTX) {
 212           if (in_msg.Requestor == machineID) {
 213             trigger(Event:Own_PUTX, in_msg.Address);
 214           } else {
 215             trigger(Event:Other_PUTX, in_msg.Address);
 216           }
 217         } else {
 218           error("Unexpected message");
 219         }
 220       }
 221     }
 222   }
 223
 224   // Mandatory Queue
 225   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 226     if (mandatoryQueue_in.isReady()) {
 227       peek(mandatoryQueue_in, CacheMsg) {
 228         if (cacheMemory.cacheAvail(in_msg.Address) == false) {
 229           trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.Address));
 230         } else {
 231           if (in_msg.Type == CacheRequestType:LD) {
 232             trigger(Event:Load, in_msg.Address);
 233           } else if (in_msg.Type == CacheRequestType:IFETCH) {
 234             trigger(Event:Ifetch, in_msg.Address);
 235           } else if ((in_msg.Type == CacheRequestType:ST) || (in_msg.Type == CacheRequestType:ATOMIC)) {
 236             trigger(Event:Store, in_msg.Address);
 237           } else {
 238             error("Invalid CacheRequestType");
 239           }
 240         }
 241       }
 242     }
 243   }
 244
 245   // Optional Queue
 246   in_port(optionalQueue_in, CacheMsg, optionalQueue, desc="...") {
 247     if (optionalQueue_in.isReady()) {
 248       peek(optionalQueue_in, CacheMsg) {
 249         if (cacheMemory.cacheAvail(in_msg.Address) == false) {
 250           trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.Address));
 251         } else {
 252           if ((in_msg.Type == CacheRequestType:LD) || (in_msg.Type == CacheRequestType:IFETCH)) {
 253             trigger(Event:Load_prefetch, in_msg.Address);
 254           } else if ((in_msg.Type == CacheRequestType:ST) || (in_msg.Type == CacheRequestType:ATOMIC)) {
 255             trigger(Event:Store_prefetch, in_msg.Address);
 256           } else {
 257             error("Invalid CacheRequestType");
 258           }
 259         }
 260       }
 261     }
 262   }
 263
 264   // ACTIONS
 265   action(a_allocateTBE, "a", desc="Allocate TBE with Address=B, ForwardID=null, RetryCount=zero, ForwardIDRetryCount=zero, ForwardProgressBit=unset.") {
 266     check_allocate(TBEs);
 267     TBEs.allocate(address);
 268     TBEs[address].isPrefetch := false;
 269     TBEs[address].ForwardIDs.clear();
 270
 271     // Keep the TBE state consistent with the cache state
 272     if (cacheMemory.isTagPresent(address)) {
 273       TBEs[address].TBEState := cacheMemory[address].CacheState;
 274     }
 275   }
 276
 277
 278   action(b_setPrefetchBit, "b", desc="Set prefetch bit in TBE.") {
 279     TBEs[address].isPrefetch := true;
 280   }
 281
 282   action(c_allocateCacheBlock, "c", desc="Set cache tag equal to tag of block B.") {
 283     if (cacheMemory.isTagPresent(address) == false) {
 284       cacheMemory.allocate(address);
 285     }
 286   }
 287
 288   action(d_deallocateTBE, "d", desc="Deallocate TBE.") {
 289     TBEs.deallocate(address);
 290   }
 291
 292   action(e_recordForwardingInfo, "e", desc="Record ID of other processor in ForwardID.") {
 293     peek(addressNetwork_in, AddressMsg){
 294       TBEs[address].ForwardIDs.add(in_msg.Requestor);
 295       TBEs[address].ForwardAddress := in_msg.Address;
 296     }
 297   }
 298
 299   action(f_issueGETS, "f", desc="Issue GETS.") {
 300     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 301       out_msg.Address := address;
 302       out_msg.Type := CoherenceRequestType:GETS;
 303       out_msg.CacheState := cache_state_to_int(getState(address));
 304       out_msg.Requestor := machineID;
 305       out_msg.Destination.broadcast(MachineType:L1Cache);
 306       out_msg.Destination.add(map_Address_to_Directory(address));  // To memory
 307       out_msg.MessageSize := MessageSizeType:Control;
 308     }
 309   }
 310
 311   action(g_issueGETX, "g", desc="Issue GETX.") {
 312     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 313       out_msg.Address := address;
 314       out_msg.Type := CoherenceRequestType:GETX;
 315       out_msg.CacheState := cache_state_to_int(getState(address));
 316       out_msg.Requestor := machineID;
 317       out_msg.Destination.broadcast(MachineType:L1Cache);
 318       out_msg.Destination.add(map_Address_to_Directory(address));  // To memory
 319       out_msg.MessageSize := MessageSizeType:Control;
 320     }
 321   }
 322
 323   action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
 324     DEBUG_EXPR(cacheMemory[address].DataBlk);
 325     if((TBEs.isPresent(address) == false) || (TBEs[address].isPrefetch == false)) {
 326       // Non-prefetch
 327       sequencer.readCallback(address, cacheMemory[address].DataBlk);
 328     } else {
 329       // Prefetch - don't call back
 330     }
 331   }
 332
 333   action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
 334     DEBUG_EXPR(cacheMemory[address].DataBlk);
 335     if((TBEs.isPresent(address) == false) || (TBEs[address].isPrefetch == false)) {
 336       // Non-prefetch
 337       sequencer.writeCallback(address, cacheMemory[address].DataBlk);
 338     } else {
 339       // Prefetch - don't call back
 340     }
 341   }
 342
 343   action(i_popAddressQueue, "i", desc="Pop incoming address queue.") {
 344     addressNetwork_in.dequeue();
 345   }
 346
 347   action(j_popDataQueue, "j", desc="Pop incoming data queue.") {
 348     dataNetwork_in.dequeue();
 349   }
 350
 351   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 352     mandatoryQueue_in.dequeue();
 353   }
 354
 355   action(l_popOptionalQueue, "l", desc="Pop optional queue.") {
 356     optionalQueue_in.dequeue();
 357   }
 358
 359
 360   action(o_cacheToForward, "o", desc="Send data from the cache to the processor indicated by ForwardIDs.") {
 361     peek(dataNetwork_in, DataMsg){
 362       // This has a CACHE_RESPONSE_LATENCY latency because we want to avoid the
 363       // timing strangeness that can occur if requests that source the
 364       // data from the TBE are faster than data sourced from the cache
 365       enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY"){
 366         out_msg.Address := TBEs[address].ForwardAddress;
 367         out_msg.Sender := machineID;
 368         out_msg.DataBlk := cacheMemory[address].DataBlk;
 369         out_msg.Destination := TBEs[address].ForwardIDs;
 370         out_msg.DestMachine := MachineType:L1Cache;
 371         out_msg.MessageSize := MessageSizeType:Data;
 372       }
 373     }
 374   }
 375
 376   action(p_issuePUTX, "p", desc="Issue PUTX.") {
 377     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 378       out_msg.Address := address;
 379       out_msg.Type := CoherenceRequestType:PUTX;
 380       out_msg.CacheState := cache_state_to_int(getState(address));
 381       out_msg.Requestor := machineID;
 382       out_msg.Destination.add(map_Address_to_Directory(address));  // To memory
 383       out_msg.Destination.add(machineID);  // Back to us
 384       out_msg.DataBlk := cacheMemory[address].DataBlk;
 385       out_msg.MessageSize := MessageSizeType:Data;
 386     }
 387   }
 388
 389   action(q_writeDataFromCacheToTBE, "q", desc="Write data from the cache into the TBE.") {
 390     TBEs[address].DataBlk := cacheMemory[address].DataBlk;
 391     DEBUG_EXPR(TBEs[address].DataBlk);
 392   }
 393
 394   action(r_cacheToRequestor, "r", desc="Send data from the cache to the requestor") {
 395     peek(addressNetwork_in, AddressMsg) {
 396       enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") {
 397         out_msg.Address := address;
 398         out_msg.Sender := machineID;
 399         out_msg.Destination.add(in_msg.Requestor);
 400         out_msg.DestMachine := MachineType:L1Cache;
 401         out_msg.DataBlk := cacheMemory[address].DataBlk;
 402         out_msg.MessageSize := MessageSizeType:Data;
 403       }
 404       DEBUG_EXPR(cacheMemory[address].DataBlk);
 405     }
 406   }
 407
 408
 409   action(s_saveDataInTBE, "s", desc="Save data in data field of TBE.") {
 410     peek(dataNetwork_in, DataMsg) {
 411       TBEs[address].DataBlk := in_msg.DataBlk;
 412       DEBUG_EXPR(TBEs[address].DataBlk);
 413     }
 414   }
 415
 416   action(t_issueGET_INSTR, "t", desc="Issue GETInstr.") {
 417     enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
 418       out_msg.Address := address;
 419       out_msg.Type := CoherenceRequestType:GET_INSTR;
 420       out_msg.CacheState := cache_state_to_int(getState(address));
 421       out_msg.Requestor := machineID;
 422       out_msg.Destination.broadcast(MachineType:L1Cache);
 423       out_msg.Destination.add(map_Address_to_Directory(address));  // To memory
 424       out_msg.MessageSize := MessageSizeType:Control;
 425     }
 426   }
 427
 428   action(w_writeDataFromTBEToCache, "w", desc="Write data from the TBE into the cache.") {
 429     cacheMemory[address].DataBlk := TBEs[address].DataBlk;
 430     DEBUG_EXPR(cacheMemory[address].DataBlk);
 431   }
 432
 433   action(y_tbeToReq, "y", desc="Send data from the TBE to the requestor.") {
 434     peek(addressNetwork_in, AddressMsg) {
 435       enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") {  // Either this or the PutX should have a real latency
 436         out_msg.Address := address;
 437         out_msg.Sender := machineID;
 438         out_msg.Destination.add(in_msg.Requestor);
 439         out_msg.DestMachine := MachineType:L1Cache;
 440         out_msg.DataBlk := TBEs[address].DataBlk;
 441         out_msg.MessageSize := MessageSizeType:Data;
 442       }
 443     }
 444   }
 445
 446   action(ff_deallocateCacheBlock, "\f", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 447     cacheMemory.deallocate(address);
 448   }
 449
 450   action(z_stall, "z", desc="Cannot be handled right now.") {
 451     // Special name recognized as do nothing case
 452   }
 453
 454   // TRANSITIONS
 455
 456   // Transitions from Idle
 457   transition({NP, I}, Load, IS_AD) {
 458     f_issueGETS;
 459     c_allocateCacheBlock;
 460     a_allocateTBE;
 461     k_popMandatoryQueue;
 462   }
 463
 464   transition({NP, I}, Ifetch, IS_AD) {
 465     t_issueGET_INSTR;
 466     c_allocateCacheBlock;
 467     a_allocateTBE;
 468     k_popMandatoryQueue;
 469   }
 470
 471  transition({NP, I}, Load_prefetch, IS_AD) {
 472     f_issueGETS;
 473     c_allocateCacheBlock;
 474     a_allocateTBE;
 475     b_setPrefetchBit;
 476     l_popOptionalQueue;
 477   }
 478
 479   transition({NP, I}, Store, IM_AD) {
 480     g_issueGETX;
 481     c_allocateCacheBlock;
 482     a_allocateTBE;
 483     k_popMandatoryQueue;
 484   }
 485
 486   transition({NP, I}, Store_prefetch, IM_AD) {
 487     g_issueGETX;
 488     c_allocateCacheBlock;
 489     a_allocateTBE;
 490     b_setPrefetchBit;
 491     l_popOptionalQueue;
 492   }
 493
 494   transition(I, Replacement) {
 495     ff_deallocateCacheBlock;       // the cache line is now in NotPresent
 496   }
 497
 498   transition({NP, I}, { Other_GETS, Other_GET_INSTR, Other_GETX } ) {
 499     i_popAddressQueue;
 500   }
 501
 502   // Transitions from Shared
 503   transition(S, {Load,Ifetch}) {
 504     h_load_hit;
 505     k_popMandatoryQueue;
 506   }
 507
 508   transition(S, Load_prefetch) {
 509     l_popOptionalQueue;
 510   }
 511
 512   transition(S, Store, SM_AD) {
 513     g_issueGETX;
 514     a_allocateTBE;
 515     k_popMandatoryQueue;
 516   }
 517
 518   transition(S, Store_prefetch, IM_AD) {
 519     g_issueGETX;
 520     a_allocateTBE;
 521     b_setPrefetchBit; // Must be after allocate TBE
 522     l_popOptionalQueue;
 523   }
 524
 525   transition(S, Replacement, I) {
 526     ff_deallocateCacheBlock;       // the cache line is now in NotPresent
 527   }
 528
 529   transition(S, {Other_GETS, Other_GET_INSTR}) {
 530     i_popAddressQueue;
 531   }
 532
 533   transition(S, Other_GETX, I) {
 534     i_popAddressQueue;
 535   }
 536
 537   // Transitions from Owned
 538   transition(O, {Load,Ifetch}) {
 539     h_load_hit;
 540     k_popMandatoryQueue;
 541   }
 542
 543   transition(O, Store, OM_A){
 544     g_issueGETX;
 545     a_allocateTBE;
 546     k_popMandatoryQueue;
 547   }
 548
 549   transition(O, Load_prefetch) {
 550     l_popOptionalQueue;
 551   }
 552
 553   transition(O, Store_prefetch, OM_A) {
 554     g_issueGETX;
 555     a_allocateTBE;
 556     b_setPrefetchBit;
 557     l_popOptionalQueue;
 558   }
 559
 560   transition(O, Replacement, OI_A) {
 561     p_issuePUTX;
 562     a_allocateTBE;
 563     q_writeDataFromCacheToTBE;// the cache line is now empty
 564     ff_deallocateCacheBlock;       // the cache line is now in NotPresent
 565   }
 566
 567   transition(O, {Other_GETS,Other_GET_INSTR}) {
 568     r_cacheToRequestor;
 569     i_popAddressQueue;
 570   }
 571
 572   transition(O, Other_GETX, I) {
 573     r_cacheToRequestor;
 574     i_popAddressQueue;
 575   }
 576
 577   // Transitions from Modified
 578   transition(M, {Load,Ifetch}) {
 579     h_load_hit;
 580     k_popMandatoryQueue;
 581   }
 582
 583   transition(M, Store) {
 584     hh_store_hit;
 585     k_popMandatoryQueue;
 586   }
 587
 588   transition(M, {Load_prefetch,Store_prefetch}) {
 589     l_popOptionalQueue;
 590   }
 591
 592   transition(M, Replacement, MI_A) {
 593     p_issuePUTX;
 594     a_allocateTBE;
 595     q_writeDataFromCacheToTBE;// the cache line is now empty
 596     ff_deallocateCacheBlock;       // the cache line is now in NotPresent
 597   }
 598
 599   transition(M, {Other_GETS,Other_GET_INSTR}, O) {
 600     r_cacheToRequestor;
 601     i_popAddressQueue;
 602   }
 603
 604   transition(M, Other_GETX, I) {
 605     r_cacheToRequestor;
 606     i_popAddressQueue;
 607   }
 608
 609
 610   // Transitions for Load/Store/Replacement from transient states
 611
 612   transition({IS_AD, IM_AD, IS_A, IM_A, SM_AD, OM_A, SM_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O}, {Load, Ifetch, Store, Replacement}) {
 613     z_stall;
 614   }
 615
 616   transition({IS_AD, IM_AD, IS_A, IM_A, SM_AD, OM_A, SM_A, IS_D, IM_D, IM_D_O, SM_D, SM_D_O}, Load_prefetch) {
 617     l_popOptionalQueue;
 618   }
 619
 620   transition({IS_D_I, IM_D_I, IM_D_OI}, Load_prefetch) {
 621     z_stall;
 622   }
 623
 624   transition({IM_AD, SM_AD, OM_A, IM_A, SM_A, IM_D, SM_D}, Store_prefetch) {
 625     l_popOptionalQueue;
 626   }
 627
 628   transition({IS_AD, IS_A, IS_D, IS_D_I, IM_D_O, IM_D_I, IM_D_OI, SM_D_O}, Store_prefetch) {
 629     z_stall;
 630   }
 631
 632   transition({MI_A, OI_A, II_A}, {Load, Ifetch, Store, Load_prefetch, Store_prefetch, Replacement}) {
 633     z_stall;
 634   }
 635
 636   // Always ignore PUTXs which we are not the owner of
 637   transition({NP, I, S, O, M, IS_AD, IM_AD, SM_AD, OM_A, IS_A, IM_A, SM_A, MI_A, OI_A, II_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O }, Other_PUTX) {
 638     i_popAddressQueue;
 639   }
 640
 641   // transitions from IS_AD
 642
 643   transition(IS_AD, {Own_GETS,Own_GET_INSTR}, IS_D) {
 644     i_popAddressQueue;
 645   }
 646   transition(IS_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 647     i_popAddressQueue;
 648   }
 649   transition(IS_AD, Data, IS_A) {
 650     s_saveDataInTBE;
 651     j_popDataQueue;
 652   }
 653
 654
 655   // Transitions from IM_AD
 656
 657   transition(IM_AD, Own_GETX, IM_D) {
 658     i_popAddressQueue;
 659   }
 660   transition(IM_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 661     i_popAddressQueue;
 662   }
 663   transition(IM_AD, Data, IM_A) {
 664     s_saveDataInTBE;
 665     j_popDataQueue;
 666   }
 667
 668   // Transitions from OM_A
 669
 670   transition(OM_A, Own_GETX, M){
 671     hh_store_hit;
 672     d_deallocateTBE;
 673     i_popAddressQueue;
 674   }
 675
 676   transition(OM_A, {Other_GETS, Other_GET_INSTR}){
 677     r_cacheToRequestor;
 678     i_popAddressQueue;
 679   }
 680
 681   transition(OM_A, Other_GETX, IM_AD){
 682     r_cacheToRequestor;
 683     i_popAddressQueue;
 684   }
 685
 686   transition(OM_A, Data, IM_A) {  // if we get data, we know we're going to lose block before we see own GETX
 687     s_saveDataInTBE;
 688     j_popDataQueue;
 689   }
 690
 691   // Transitions from SM_AD
 692
 693   transition(SM_AD, Own_GETX, SM_D) {
 694     i_popAddressQueue;
 695   }
 696   transition(SM_AD, {Other_GETS,Other_GET_INSTR}) {
 697     i_popAddressQueue;
 698   }
 699   transition(SM_AD, Other_GETX, IM_AD) {
 700     i_popAddressQueue;
 701   }
 702   transition(SM_AD, Data, SM_A) {
 703     s_saveDataInTBE;
 704     j_popDataQueue;
 705   }
 706
 707
 708   // Transitions from IS_A
 709
 710   transition(IS_A, {Own_GETS,Own_GET_INSTR}, S) {
 711     w_writeDataFromTBEToCache;
 712     h_load_hit;
 713     d_deallocateTBE;
 714     i_popAddressQueue;
 715   }
 716   transition(IS_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 717     i_popAddressQueue;
 718   }
 719
 720   // Transitions from IM_A
 721
 722   transition(IM_A, Own_GETX, M) {
 723     w_writeDataFromTBEToCache;
 724     hh_store_hit;
 725     d_deallocateTBE;
 726     i_popAddressQueue;
 727   }
 728   transition(IM_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 729     i_popAddressQueue;
 730   }
 731
 732   // Transitions from SM_A
 733
 734   transition(SM_A, Own_GETX, M) {
 735     w_writeDataFromTBEToCache;
 736     hh_store_hit;
 737     d_deallocateTBE;
 738     i_popAddressQueue;
 739   }
 740   transition(SM_A, {Other_GETS,Other_GET_INSTR}) {
 741     i_popAddressQueue;
 742   }
 743   transition(SM_A, Other_GETX, IM_A) {
 744     i_popAddressQueue;
 745   }
 746
 747
 748   // Transitions from MI_A
 749
 750   transition(MI_A, Own_PUTX, I) {
 751     d_deallocateTBE;
 752     i_popAddressQueue;
 753   }
 754
 755   transition(MI_A, {Other_GETS, Other_GET_INSTR}) {
 756     y_tbeToReq;
 757     i_popAddressQueue;
 758   }
 759
 760   transition(MI_A, Other_GETX, II_A) {
 761     y_tbeToReq;
 762     i_popAddressQueue;
 763   }
 764
 765   // Transitions from OI_A
 766
 767   transition(OI_A, Own_PUTX, I) {
 768     d_deallocateTBE;
 769     i_popAddressQueue;
 770   }
 771
 772   transition(OI_A, {Other_GETS, Other_GET_INSTR}) {
 773     y_tbeToReq;
 774     i_popAddressQueue;
 775   }
 776
 777   transition(OI_A, Other_GETX, II_A) {
 778     y_tbeToReq;
 779     i_popAddressQueue;
 780   }
 781
 782
 783   // Transitions from II_A
 784
 785   transition(II_A, Own_PUTX, I) {
 786     d_deallocateTBE;
 787     i_popAddressQueue;
 788   }
 789
 790   transition(II_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
 791     i_popAddressQueue;
 792   }
 793
 794   // Transitions from IS_D, IS_D_I
 795
 796   transition({IS_D, IS_D_I}, {Other_GETS,Other_GET_INSTR}) {
 797     i_popAddressQueue;
 798   }
 799   transition(IS_D, Other_GETX, IS_D_I) {
 800     i_popAddressQueue;
 801   }
 802   transition(IS_D_I, Other_GETX) {
 803     i_popAddressQueue;
 804   }
 805   transition(IS_D, Data, S) {
 806     s_saveDataInTBE;
 807     w_writeDataFromTBEToCache;
 808     h_load_hit;
 809     d_deallocateTBE;
 810     j_popDataQueue;
 811   }
 812
 813   transition(IS_D_I, Data, I) {
 814     s_saveDataInTBE;
 815     w_writeDataFromTBEToCache;
 816     h_load_hit;
 817     d_deallocateTBE;
 818     j_popDataQueue;
 819   }
 820
 821   // Transitions from IM_D, IM_D_O, IM_D_I, IM_D_OI
 822
 823   transition( IM_D, {Other_GETS,Other_GET_INSTR}, IM_D_O ) {
 824     e_recordForwardingInfo;
 825     i_popAddressQueue;
 826   }
 827
 828   transition( IM_D, Other_GETX, IM_D_I ) {
 829     e_recordForwardingInfo;
 830     i_popAddressQueue;
 831   }
 832
 833   transition(IM_D_O, {Other_GETS,Other_GET_INSTR} ) {
 834     e_recordForwardingInfo;
 835     i_popAddressQueue;
 836   }
 837
 838   transition(IM_D_O, Other_GETX, IM_D_OI) {
 839     e_recordForwardingInfo;
 840     i_popAddressQueue;
 841   }
 842
 843   transition( {IM_D_I, IM_D_OI}, {Other_GETS, Other_GET_INSTR, Other_GETX} ) {
 844     i_popAddressQueue;
 845   }
 846
 847   transition(IM_D, Data, M) {
 848     s_saveDataInTBE;
 849     w_writeDataFromTBEToCache;
 850     hh_store_hit;
 851     d_deallocateTBE;
 852     j_popDataQueue;
 853   }
 854
 855   transition(IM_D_O, Data, O) {
 856     s_saveDataInTBE;
 857     w_writeDataFromTBEToCache;
 858     hh_store_hit;
 859     o_cacheToForward;
 860     d_deallocateTBE;
 861     j_popDataQueue;
 862    }
 863
 864   transition(IM_D_I, Data, I) {
 865     s_saveDataInTBE;
 866     w_writeDataFromTBEToCache;
 867     hh_store_hit;
 868     o_cacheToForward;
 869     d_deallocateTBE;
 870     j_popDataQueue;
 871   }
 872
 873   transition(IM_D_OI, Data, I) {
 874     s_saveDataInTBE;
 875     w_writeDataFromTBEToCache;
 876     hh_store_hit;
 877     o_cacheToForward;
 878     d_deallocateTBE;
 879     j_popDataQueue;
 880   }
 881
 882   // Transitions for SM_D, SM_D_O
 883
 884   transition(SM_D, {Other_GETS,Other_GET_INSTR}, SM_D_O) {
 885     e_recordForwardingInfo;
 886     i_popAddressQueue;
 887   }
 888
 889   transition(SM_D, Other_GETX, IM_D_I) {
 890     e_recordForwardingInfo;
 891     i_popAddressQueue;
 892   }
 893
 894   transition(SM_D_O, {Other_GETS,Other_GET_INSTR}) {
 895     e_recordForwardingInfo;
 896     i_popAddressQueue;
 897   }
 898
 899   transition(SM_D_O, Other_GETX, IM_D_OI) {
 900     e_recordForwardingInfo;
 901     i_popAddressQueue;
 902   }
 903
 904   transition(SM_D, Data, M) {
 905     s_saveDataInTBE;
 906     w_writeDataFromTBEToCache;
 907     hh_store_hit;
 908     d_deallocateTBE;
 909     j_popDataQueue;
 910   }
 911
 912   transition(SM_D_O, Data, O) {
 913     s_saveDataInTBE;
 914     w_writeDataFromTBEToCache;
 915     hh_store_hit;
 916     o_cacheToForward;
 917     d_deallocateTBE;
 918     j_popDataQueue;
 919   }
 920
 921 }