3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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35 machine(Directory, "MOSI Broadcast Optimized") {
38 MessageBuffer addressFromDir, network="To", virtual_network="0", ordered="true";
39 MessageBuffer dataFromDir, network="To", virtual_network="1", ordered="false";
41 MessageBuffer addressToDir, network="From", virtual_network="0", ordered="true";
42 MessageBuffer dataToDir, network="From", virtual_network="1", ordered="false";
45 enumeration(State, desc="Directory states", default="Directory_State_C") {
46 C, desc="Cold - no processor has requested this line";
49 SS, desc="Shared, 2 or more shares";
50 OS, desc="Owned by a cache";
51 OSS, desc="Owned by a cache, present in at least 3 caches";
52 M, desc="Modified", format="!b";
57 enumeration(Event, desc="Directory events") {
58 // From Address network
59 OtherAddress, desc="We saw an address msg to someone else";
60 GETS, desc="A GETS arrives";
61 GET_INSTR, desc="A GETInstr arrives";
62 GETX, desc="A GETX arrives", format="!r";
63 PUTX_Owner, desc="A PUTX arrives, requestor is owner";
64 PUTX_NotOwner, desc="A PUTX arrives, requestor is not owner", format="!r";
65 Memory_Data, desc="Fetched data from memory arrives";
66 Memory_Ack, desc="Writeback Ack from memory arrives";
72 structure(Entry, desc="...") {
73 State DirectoryState, desc="Directory state";
74 bool DirOwner, default="true", desc="Is dir owner?";
75 MachineID ProcOwner, desc="Processor Owner";
76 DataBlock DataBlk, desc="data for the block";
79 external_type(DirectoryMemory) {
80 Entry lookup(Address);
81 bool isPresent(Address);
84 // to simulate detailed DRAM
85 external_type(MemoryControl, inport="yes", outport="yes") {
91 DirectoryMemory directory, constructor_hack="i";
92 MemoryControl memBuffer, constructor_hack="i";
94 void profile_request(int cache_state, State directory_state, GenericRequestType request_type);
96 State getState(Address addr) {
97 if (directory.isPresent(addr)) {
98 return directory[addr].DirectoryState;
103 void setState(Address addr, State state) {
104 if (directory.isPresent(addr)) {
105 directory[addr].DirectoryState := state;
111 out_port(dataNetwork_out, DataMsg, dataFromDir);
112 out_port(addressNetwork_out, AddressMsg, addressFromDir);
113 out_port(memQueue_out, MemoryMsg, memBuffer);
119 in_port(addressNetwork_in, AddressMsg, addressToDir) {
120 if (addressNetwork_in.isReady()) {
121 peek(addressNetwork_in, AddressMsg) {
122 if(map_Address_to_Directory(in_msg.Address) != machineID) {
123 trigger(Event:OtherAddress, in_msg.Address);
124 } else if (in_msg.Type == CoherenceRequestType:GETS) {
125 trigger(Event:GETS, in_msg.Address);
126 } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
127 trigger(Event:GET_INSTR, in_msg.Address);
128 } else if (in_msg.Type == CoherenceRequestType:GETX) {
129 trigger(Event:GETX, in_msg.Address);
130 } else if (in_msg.Type == CoherenceRequestType:PUTX) {
131 if (in_msg.Requestor == directory[in_msg.Address].ProcOwner && directory[in_msg.Address].DirOwner == false) {
132 trigger(Event:PUTX_Owner, in_msg.Address);
134 trigger(Event:PUTX_NotOwner, in_msg.Address);
137 error("unexpected message");
143 // off-chip memory request/response is done
144 in_port(memQueue_in, MemoryMsg, memBuffer) {
145 if (memQueue_in.isReady()) {
146 peek(memQueue_in, MemoryMsg) {
147 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
148 trigger(Event:Memory_Data, in_msg.Address);
149 } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
150 trigger(Event:Memory_Ack, in_msg.Address);
152 DEBUG_EXPR(in_msg.Type);
153 error("Invalid message");
161 action(d_sendDataMsg, "d", desc="Send data message to requestor") {
162 peek(memQueue_in, MemoryMsg) {
163 enqueue(dataNetwork_out, DataMsg, latency="1") {
164 out_msg.Address := in_msg.Address;
165 out_msg.Sender := machineID;
166 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
167 out_msg.DestMachine := MachineType:L1Cache;
168 //out_msg.DataBlk := directory[in_msg.Address].DataBlk;
169 out_msg.DataBlk := in_msg.DataBlk;
170 out_msg.MessageSize := MessageSizeType:Data;
171 DEBUG_EXPR(in_msg.OriginalRequestorMachId);
172 DEBUG_EXPR(out_msg.DataBlk);
177 action(j_popAddressQueue, "j", desc="Pop address queue.") {
178 addressNetwork_in.dequeue();
181 action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
182 memQueue_in.dequeue();
185 action(p_profile, "p", desc="Profile this transition.") {
186 peek(addressNetwork_in, AddressMsg) {
187 profile_request(in_msg.CacheState, getState(address), convertToGenericType(in_msg.Type));
191 action(m_setOwnerRequestor, "m", desc="Set owner = requestor") {
192 peek(addressNetwork_in, AddressMsg) {
193 directory[in_msg.Address].ProcOwner := in_msg.Requestor;
194 directory[in_msg.Address].DirOwner := false;
198 action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
199 peek(addressNetwork_in, AddressMsg) {
200 enqueue(memQueue_out, MemoryMsg, latency="1") {
201 out_msg.Address := address;
202 out_msg.Type := MemoryRequestType:MEMORY_READ;
203 out_msg.Sender := machineID;
204 out_msg.OriginalRequestorMachId := in_msg.Requestor;
205 out_msg.DataBlk := directory[in_msg.Address].DataBlk;
206 out_msg.MessageSize := in_msg.MessageSize;
207 //out_msg.Prefetch := in_msg.Prefetch;
213 action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
214 peek(addressNetwork_in, AddressMsg) {
215 enqueue(memQueue_out, MemoryMsg, latency="1") {
216 out_msg.Address := address;
217 out_msg.Type := MemoryRequestType:MEMORY_WB;
218 out_msg.Sender := machineID;
219 out_msg.OriginalRequestorMachId := in_msg.Requestor;
220 out_msg.DataBlk := in_msg.DataBlk;
221 out_msg.MessageSize := in_msg.MessageSize;
222 //out_msg.Prefetch := in_msg.Prefetch;
228 action(r_writeDataFromRequest, "r", desc="Write request data to memory") {
229 peek(addressNetwork_in, AddressMsg) {
230 directory[in_msg.Address].DataBlk := in_msg.DataBlk;
231 DEBUG_EXPR(in_msg.Address);
232 DEBUG_EXPR(in_msg.DataBlk);
236 action(x_setOwnerToDirectory, "x", desc="Set owner equal to the directory"){
237 peek(addressNetwork_in, AddressMsg) {
238 directory[in_msg.Address].DirOwner := true;
244 // Ignore all address and data messages not bound for us
245 transition(C, OtherAddress) {
249 // PUTX_NotOwner Transitions
250 transition({I, S, SS, OS, OSS, M}, PUTX_NotOwner) {
255 // Transitions from Idle
256 transition({C, I}, {GETS,GET_INSTR}, S) {
258 qf_queueMemoryFetchRequest;
263 transition({C, I}, GETX, M) {
265 qf_queueMemoryFetchRequest;
271 // Transitions from Shared
272 transition({S, SS}, {GETS,GET_INSTR}, SS) {
274 qf_queueMemoryFetchRequest;
279 transition({S, SS}, GETX, M) {
281 qf_queueMemoryFetchRequest;
287 // Transitions from Owned
288 transition({OS, OSS}, {GETS,GET_INSTR}, OSS) {
293 transition({OS, OSS}, GETX, M) {
299 transition(OS, PUTX_Owner, S) {
300 x_setOwnerToDirectory;
301 r_writeDataFromRequest;
302 qw_queueMemoryWBRequest;
307 transition(OSS, PUTX_Owner, SS) {
308 x_setOwnerToDirectory;
309 r_writeDataFromRequest;
310 qw_queueMemoryWBRequest;
315 // Transitions from Modified
316 transition(M, {GETS,GET_INSTR}, OS) {
321 transition(M, GETX) {
327 transition(M, PUTX_Owner, I) {
328 x_setOwnerToDirectory;
329 r_writeDataFromRequest;
330 qw_queueMemoryWBRequest;
335 transition({C, I, S, SS, OS, OSS, M}, Memory_Data) {
340 transition({C, I, S, SS, OS, OSS, M}, Memory_Ack) {