Cache: Remove dangling doWriteback declaration
[gem5.git] / src / mem / protocol / Network_test-cache.sm
1 /*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 *
29 * Authors: Brad Beckmann
30 * Tushar Krishna
31 */
32
33
34 machine(L1Cache, "Network_test L1 Cache")
35 : Sequencer * sequencer,
36 int issue_latency = 2
37 {
38
39 // NETWORK BUFFERS
40 MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false", vnet_type = "request";
41 MessageBuffer forwardFromCache, network="To", virtual_network="1", ordered="false", vnet_type = "forward";
42 MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false", vnet_type = "response";
43
44 // STATES
45 state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
46 I, AccessPermission:Invalid, desc="Not Present/Invalid";
47 }
48
49 // EVENTS
50 enumeration(Event, desc="Cache events") {
51 // From processor
52 Request, desc="Request from Network_test";
53 Forward, desc="Forward from Network_test";
54 Response, desc="Response from Network_test";
55 }
56
57 // STRUCTURE DEFINITIONS
58
59 MessageBuffer mandatoryQueue, ordered="false";
60 DataBlock dummyData;
61
62
63 // CacheEntry
64 structure(Entry, desc="...", interface="AbstractCacheEntry") {
65 State CacheState, desc="cache state";
66 DataBlock DataBlk, desc="Data in the block";
67 }
68
69 // TBE fields
70 structure(TBE, desc="...") {
71 State TBEState, desc="Transient state";
72 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
73 }
74
75 structure(TBETable, external="yes") {
76 TBE lookup(Address);
77 void allocate(Address);
78 void deallocate(Address);
79 bool isPresent(Address);
80 }
81
82
83 // STRUCTURES
84
85 TBETable TBEs, template_hack="<L1Cache_TBE>";
86
87
88 // FUNCTIONS
89
90 // cpu/testers/networktest/networktest.cc generates packets of the type
91 // ReadReq, INST_FETCH, and WriteReq.
92 // These are converted to LD, IFETCH and ST by mem/ruby/system/RubyPort.cc.
93 // These are then sent to the sequencer, which sends them here.
94 // Network_test-cache.sm tags LD, IFETCH and ST as Request, Forward,
95 // and Response Events respectively, which are then injected into
96 // virtual networks 0, 1 and 2 respectively.
97 // This models traffic of different types within the network.
98 //
99 // Note that requests and forwards are MessageSizeType:Control,
100 // while responses are MessageSizeType:Data.
101 //
102 Event mandatory_request_type_to_event(RubyRequestType type) {
103 if (type == RubyRequestType:LD) {
104 return Event:Request;
105 } else if (type == RubyRequestType:IFETCH) {
106 return Event:Forward;
107 } else if (type == RubyRequestType:ST) {
108 return Event:Response;
109 } else {
110 error("Invalid RubyRequestType");
111 }
112 }
113
114
115 State getState(TBE tbe, Entry cache_entry, Address addr) {
116 return State:I;
117 }
118
119 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
120
121 }
122
123 AccessPermission getAccessPermission(Address addr) {
124 return AccessPermission:NotPresent;
125 }
126
127 void setAccessPermission(Entry cache_entry, Address addr, State state) {
128 }
129
130 Entry getCacheEntry(Address address), return_by_pointer="yes" {
131 return OOD;
132 }
133
134 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
135 error("Network Test does not support get data block.");
136 }
137
138 // NETWORK PORTS
139
140 out_port(requestNetwork_out, RequestMsg, requestFromCache);
141 out_port(forwardNetwork_out, RequestMsg, forwardFromCache);
142 out_port(responseNetwork_out, RequestMsg, responseFromCache);
143
144 // Mandatory Queue
145 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
146 if (mandatoryQueue_in.isReady()) {
147 peek(mandatoryQueue_in, RubyRequest) {
148 trigger(mandatory_request_type_to_event(in_msg.Type),
149 in_msg.LineAddress,
150 getCacheEntry(in_msg.LineAddress),
151 TBEs[in_msg.LineAddress]);
152 }
153 }
154 }
155
156 // ACTIONS
157
158 // The destination directory of the packets is embedded in the address
159 // map_Address_to_Directory is used to retrieve it.
160
161 action(a_issueRequest, "a", desc="Issue a request") {
162 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
163 out_msg.Address := address;
164 out_msg.Type := CoherenceRequestType:MSG;
165 out_msg.Requestor := machineID;
166 out_msg.Destination.add(map_Address_to_Directory(address));
167 //out_msg.Destination := broadcast(MachineType:Directory);
168 out_msg.MessageSize := MessageSizeType:Control;
169 }
170 }
171
172 action(b_issueForward, "b", desc="Issue a forward") {
173 enqueue(forwardNetwork_out, RequestMsg, latency=issue_latency) {
174 out_msg.Address := address;
175 out_msg.Type := CoherenceRequestType:MSG;
176 out_msg.Requestor := machineID;
177 out_msg.Destination.add(map_Address_to_Directory(address));
178 out_msg.MessageSize := MessageSizeType:Control;
179 }
180 }
181
182 action(c_issueResponse, "c", desc="Issue a response") {
183 enqueue(responseNetwork_out, RequestMsg, latency=issue_latency) {
184 out_msg.Address := address;
185 out_msg.Type := CoherenceRequestType:MSG;
186 out_msg.Requestor := machineID;
187 out_msg.Destination.add(map_Address_to_Directory(address));
188 out_msg.MessageSize := MessageSizeType:Data;
189 }
190 }
191
192 action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
193 mandatoryQueue_in.dequeue();
194 }
195
196 action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
197 sequencer.readCallback(address, dummyData);
198 }
199
200 action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
201 sequencer.writeCallback(address, dummyData);
202 }
203
204
205 // TRANSITIONS
206
207 // sequencer hit call back is performed after injecting the packets.
208 // The goal of the Network_test protocol is only to inject packets into
209 // the network, not to keep track of them via TBEs.
210
211 transition(I, Response) {
212 s_store_hit;
213 c_issueResponse;
214 m_popMandatoryQueue;
215 }
216
217 transition(I, Request) {
218 r_load_hit;
219 a_issueRequest;
220 m_popMandatoryQueue;
221 }
222 transition(I, Forward) {
223 r_load_hit;
224 b_issueForward;
225 m_popMandatoryQueue;
226 }
227
228 }