2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Brad Beckmann
34 machine(L1Cache, "Network_test L1 Cache")
35 : Sequencer * sequencer,
40 MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false";
41 MessageBuffer forwardFromCache, network="To", virtual_network="1", ordered="false";
42 MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false";
45 state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
46 I, AccessPermission:Invalid, desc="Not Present/Invalid";
50 enumeration(Event, desc="Cache events") {
52 Request, desc="Request from Network_test";
53 Forward, desc="Forward from Network_test";
54 Response, desc="Response from Network_test";
57 // STRUCTURE DEFINITIONS
59 MessageBuffer mandatoryQueue, ordered="false";
64 structure(Entry, desc="...", interface="AbstractCacheEntry") {
65 State CacheState, desc="cache state";
66 DataBlock DataBlk, desc="Data in the block";
70 structure(TBE, desc="...") {
71 State TBEState, desc="Transient state";
72 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
75 structure(TBETable, external="yes") {
77 void allocate(Address);
78 void deallocate(Address);
79 bool isPresent(Address);
85 TBETable TBEs, template_hack="<L1Cache_TBE>";
90 // cpu/testers/networktest/networktest.cc generates packets of the type
91 // ReadReq, INST_FETCH, and WriteReq.
92 // These are converted to LD, IFETCH and ST by mem/ruby/system/RubyPort.cc.
93 // These are then sent to the sequencer, which sends them here.
94 // Network_test-cache.sm tags LD, IFETCH and ST as Request, Forward,
95 // and Response Events respectively, which are then injected into
96 // virtual networks 0, 1 and 2 respectively.
97 // This models traffic of different types within the network.
99 // Note that requests and forwards are MessageSizeType:Control,
100 // while responses are MessageSizeType:Data.
102 Event mandatory_request_type_to_event(RubyRequestType type) {
103 if (type == RubyRequestType:LD) {
104 return Event:Request;
105 } else if (type == RubyRequestType:IFETCH) {
106 return Event:Forward;
107 } else if (type == RubyRequestType:ST) {
108 return Event:Response;
110 error("Invalid RubyRequestType");
115 State getState(TBE tbe, Entry cache_entry, Address addr) {
119 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
123 Entry getCacheEntry(Address address), return_by_pointer="yes" {
130 out_port(requestNetwork_out, RequestMsg, requestFromCache);
131 out_port(forwardNetwork_out, RequestMsg, forwardFromCache);
132 out_port(responseNetwork_out, RequestMsg, responseFromCache);
135 in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
136 if (mandatoryQueue_in.isReady()) {
137 peek(mandatoryQueue_in, CacheMsg) {
138 trigger(mandatory_request_type_to_event(in_msg.Type),
140 getCacheEntry(in_msg.LineAddress),
141 TBEs[in_msg.LineAddress]);
148 // The destination directory of the packets is embedded in the address
149 // map_Address_to_Directory is used to retrieve it.
151 action(a_issueRequest, "a", desc="Issue a request") {
152 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
153 out_msg.Address := address;
154 out_msg.Type := CoherenceRequestType:MSG;
155 out_msg.Requestor := machineID;
156 out_msg.Destination.add(map_Address_to_Directory(address));
157 //out_msg.Destination := broadcast(MachineType:Directory);
158 out_msg.MessageSize := MessageSizeType:Control;
162 action(b_issueForward, "b", desc="Issue a forward") {
163 enqueue(forwardNetwork_out, RequestMsg, latency=issue_latency) {
164 out_msg.Address := address;
165 out_msg.Type := CoherenceRequestType:MSG;
166 out_msg.Requestor := machineID;
167 out_msg.Destination.add(map_Address_to_Directory(address));
168 out_msg.MessageSize := MessageSizeType:Control;
172 action(c_issueResponse, "c", desc="Issue a response") {
173 enqueue(responseNetwork_out, RequestMsg, latency=issue_latency) {
174 out_msg.Address := address;
175 out_msg.Type := CoherenceRequestType:MSG;
176 out_msg.Requestor := machineID;
177 out_msg.Destination.add(map_Address_to_Directory(address));
178 out_msg.MessageSize := MessageSizeType:Data;
182 action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
183 mandatoryQueue_in.dequeue();
186 action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
187 sequencer.readCallback(address, dummyData);
190 action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
191 sequencer.writeCallback(address, dummyData);
197 // sequencer hit call back is performed after injecting the packets.
198 // The goal of the Network_test protocol is only to inject packets into
199 // the network, not to keep track of them via TBEs.
201 transition(I, Response) {
207 transition(I, Request) {
212 transition(I, Forward) {