src/mem/protocol/Network_test-cache.sm

   1 /*
   2  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *
  29  * Authors: Brad Beckmann
  30  *          Tushar Krishna
  31  */
  32
  33
  34 machine(L1Cache, "Network_test L1 Cache")
  35     : Sequencer * sequencer;
  36       Cycles issue_latency := 2;
  37
  38       // NETWORK BUFFERS
  39       MessageBuffer * requestFromCache, network="To", virtual_network="0",
  40             ordered="false", vnet_type = "request";
  41       MessageBuffer * forwardFromCache, network="To", virtual_network="1",
  42             ordered="false", vnet_type = "forward";
  43       MessageBuffer * responseFromCache, network="To", virtual_network="2",
  44             ordered="false", vnet_type = "response";
  45 {
  46   // STATES
  47   state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
  48     I,  AccessPermission:Invalid, desc="Not Present/Invalid";
  49   }
  50
  51   // EVENTS
  52   enumeration(Event, desc="Cache events") {
  53     // From processor
  54     Request,    desc="Request from Network_test";
  55     Forward,    desc="Forward from Network_test";
  56     Response,   desc="Response from Network_test";
  57   }
  58
  59   // STRUCTURE DEFINITIONS
  60
  61   MessageBuffer mandatoryQueue, ordered="false";
  62   DataBlock dummyData;
  63
  64
  65   // CacheEntry
  66   structure(Entry, desc="...", interface="AbstractCacheEntry") {
  67     State CacheState,        desc="cache state";
  68     DataBlock DataBlk,       desc="Data in the block";
  69   }
  70
  71   // FUNCTIONS
  72
  73   // cpu/testers/networktest/networktest.cc generates packets of the type
  74   // ReadReq, INST_FETCH, and WriteReq.
  75   // These are converted to LD, IFETCH and ST by mem/ruby/system/RubyPort.cc.
  76   // These are then sent to the sequencer, which sends them here.
  77   // Network_test-cache.sm tags LD, IFETCH and ST as Request, Forward,
  78   // and Response Events respectively, which are then injected into
  79   // virtual networks 0, 1 and 2 respectively.
  80   // This models traffic of different types within the network.
  81   //
  82   // Note that requests and forwards are MessageSizeType:Control,
  83   // while responses are MessageSizeType:Data.
  84   //
  85   Event mandatory_request_type_to_event(RubyRequestType type) {
  86     if (type == RubyRequestType:LD) {
  87       return Event:Request;
  88     } else if (type == RubyRequestType:IFETCH) {
  89       return Event:Forward;
  90     } else if (type == RubyRequestType:ST) {
  91       return Event:Response;
  92     } else {
  93       error("Invalid RubyRequestType");
  94     }
  95   }
  96
  97
  98   State getState(Entry cache_entry, Address addr) {
  99     return State:I;
 100   }
 101
 102   void setState(Entry cache_entry, Address addr, State state) {
 103
 104   }
 105
 106   AccessPermission getAccessPermission(Address addr) {
 107     return AccessPermission:NotPresent;
 108   }
 109
 110   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 111   }
 112
 113   Entry getCacheEntry(Address address), return_by_pointer="yes" {
 114     return OOD;
 115   }
 116
 117   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 118     error("Network Test does not support get data block.");
 119   }
 120
 121   // NETWORK PORTS
 122
 123   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 124   out_port(forwardNetwork_out, RequestMsg, forwardFromCache);
 125   out_port(responseNetwork_out, RequestMsg, responseFromCache);
 126
 127   // Mandatory Queue
 128   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 129     if (mandatoryQueue_in.isReady()) {
 130       peek(mandatoryQueue_in, RubyRequest) {
 131         trigger(mandatory_request_type_to_event(in_msg.Type),
 132                 in_msg.LineAddress, getCacheEntry(in_msg.LineAddress));
 133       }
 134     }
 135   }
 136
 137   // ACTIONS
 138
 139   // The destination directory of the packets is embedded in the address
 140   // map_Address_to_Directory is used to retrieve it.
 141
 142   action(a_issueRequest, "a", desc="Issue a request") {
 143     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 144       out_msg.Addr := address;
 145       out_msg.Type := CoherenceRequestType:MSG;
 146       out_msg.Requestor := machineID;
 147       out_msg.Destination.add(map_Address_to_Directory(address));
 148       //out_msg.Destination := broadcast(MachineType:Directory);
 149       out_msg.MessageSize := MessageSizeType:Control;
 150     }
 151   }
 152
 153   action(b_issueForward, "b", desc="Issue a forward") {
 154     enqueue(forwardNetwork_out, RequestMsg, issue_latency) {
 155       out_msg.Addr := address;
 156       out_msg.Type := CoherenceRequestType:MSG;
 157       out_msg.Requestor := machineID;
 158       out_msg.Destination.add(map_Address_to_Directory(address));
 159       out_msg.MessageSize := MessageSizeType:Control;
 160     }
 161   }
 162
 163   action(c_issueResponse, "c", desc="Issue a response") {
 164     enqueue(responseNetwork_out, RequestMsg, issue_latency) {
 165       out_msg.Addr := address;
 166       out_msg.Type := CoherenceRequestType:MSG;
 167       out_msg.Requestor := machineID;
 168       out_msg.Destination.add(map_Address_to_Directory(address));
 169       out_msg.MessageSize := MessageSizeType:Data;
 170     }
 171   }
 172
 173   action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
 174     mandatoryQueue_in.dequeue();
 175   }
 176
 177   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
 178     sequencer.readCallback(address, dummyData);
 179   }
 180
 181   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
 182     sequencer.writeCallback(address, dummyData);
 183   }
 184
 185
 186   // TRANSITIONS
 187
 188   // sequencer hit call back is performed after injecting the packets.
 189   // The goal of the Network_test protocol is only to inject packets into
 190   // the network, not to keep track of them via TBEs.
 191
 192   transition(I, Response) {
 193     s_store_hit;
 194     c_issueResponse;
 195     m_popMandatoryQueue;
 196   }
 197
 198   transition(I, Request) {
 199     r_load_hit;
 200     a_issueRequest;
 201     m_popMandatoryQueue;
 202   }
 203   transition(I, Forward) {
 204     r_load_hit;
 205     b_issueForward;
 206     m_popMandatoryQueue;
 207   }
 208
 209 }