src/mem/protocol/Network_test-cache.sm

   1 /*
   2  * Copyright (c) 2009 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *
  29  * Authors: Brad Beckmann
  30  *          Tushar Krishna
  31  */
  32
  33
  34 machine(L1Cache, "Network_test L1 Cache")
  35 : Sequencer * sequencer,
  36   Cycles issue_latency = 2
  37 {
  38
  39   // NETWORK BUFFERS
  40   MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false", vnet_type = "request";
  41   MessageBuffer forwardFromCache, network="To", virtual_network="1", ordered="false", vnet_type = "forward";
  42   MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false", vnet_type = "response";
  43
  44   // STATES
  45   state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
  46     I,  AccessPermission:Invalid, desc="Not Present/Invalid";
  47   }
  48
  49   // EVENTS
  50   enumeration(Event, desc="Cache events") {
  51     // From processor
  52     Request,    desc="Request from Network_test";
  53     Forward,    desc="Forward from Network_test";
  54     Response,   desc="Response from Network_test";
  55   }
  56
  57   // STRUCTURE DEFINITIONS
  58
  59   MessageBuffer mandatoryQueue, ordered="false";
  60   DataBlock dummyData;
  61
  62
  63   // CacheEntry
  64   structure(Entry, desc="...", interface="AbstractCacheEntry") {
  65     State CacheState,        desc="cache state";
  66     DataBlock DataBlk,       desc="Data in the block";
  67   }
  68
  69   // FUNCTIONS
  70
  71   // cpu/testers/networktest/networktest.cc generates packets of the type
  72   // ReadReq, INST_FETCH, and WriteReq.
  73   // These are converted to LD, IFETCH and ST by mem/ruby/system/RubyPort.cc.
  74   // These are then sent to the sequencer, which sends them here.
  75   // Network_test-cache.sm tags LD, IFETCH and ST as Request, Forward,
  76   // and Response Events respectively, which are then injected into
  77   // virtual networks 0, 1 and 2 respectively.
  78   // This models traffic of different types within the network.
  79   //
  80   // Note that requests and forwards are MessageSizeType:Control,
  81   // while responses are MessageSizeType:Data.
  82   //
  83   Event mandatory_request_type_to_event(RubyRequestType type) {
  84     if (type == RubyRequestType:LD) {
  85       return Event:Request;
  86     } else if (type == RubyRequestType:IFETCH) {
  87       return Event:Forward;
  88     } else if (type == RubyRequestType:ST) {
  89       return Event:Response;
  90     } else {
  91       error("Invalid RubyRequestType");
  92     }
  93   }
  94
  95
  96   State getState(Entry cache_entry, Address addr) {
  97     return State:I;
  98   }
  99
 100   void setState(Entry cache_entry, Address addr, State state) {
 101
 102   }
 103
 104   AccessPermission getAccessPermission(Address addr) {
 105     return AccessPermission:NotPresent;
 106   }
 107
 108   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 109   }
 110
 111   Entry getCacheEntry(Address address), return_by_pointer="yes" {
 112     return OOD;
 113   }
 114
 115   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 116     error("Network Test does not support get data block.");
 117   }
 118
 119   // NETWORK PORTS
 120
 121   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 122   out_port(forwardNetwork_out, RequestMsg, forwardFromCache);
 123   out_port(responseNetwork_out, RequestMsg, responseFromCache);
 124
 125   // Mandatory Queue
 126   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 127     if (mandatoryQueue_in.isReady()) {
 128       peek(mandatoryQueue_in, RubyRequest) {
 129         trigger(mandatory_request_type_to_event(in_msg.Type),
 130                 in_msg.LineAddress, getCacheEntry(in_msg.LineAddress));
 131       }
 132     }
 133   }
 134
 135   // ACTIONS
 136
 137   // The destination directory of the packets is embedded in the address
 138   // map_Address_to_Directory is used to retrieve it.
 139
 140   action(a_issueRequest, "a", desc="Issue a request") {
 141     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 142       out_msg.Addr := address;
 143       out_msg.Type := CoherenceRequestType:MSG;
 144       out_msg.Requestor := machineID;
 145       out_msg.Destination.add(map_Address_to_Directory(address));
 146       //out_msg.Destination := broadcast(MachineType:Directory);
 147       out_msg.MessageSize := MessageSizeType:Control;
 148     }
 149   }
 150
 151   action(b_issueForward, "b", desc="Issue a forward") {
 152     enqueue(forwardNetwork_out, RequestMsg, latency=issue_latency) {
 153       out_msg.Addr := address;
 154       out_msg.Type := CoherenceRequestType:MSG;
 155       out_msg.Requestor := machineID;
 156       out_msg.Destination.add(map_Address_to_Directory(address));
 157       out_msg.MessageSize := MessageSizeType:Control;
 158     }
 159   }
 160
 161   action(c_issueResponse, "c", desc="Issue a response") {
 162     enqueue(responseNetwork_out, RequestMsg, latency=issue_latency) {
 163       out_msg.Addr := address;
 164       out_msg.Type := CoherenceRequestType:MSG;
 165       out_msg.Requestor := machineID;
 166       out_msg.Destination.add(map_Address_to_Directory(address));
 167       out_msg.MessageSize := MessageSizeType:Data;
 168     }
 169   }
 170
 171   action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
 172     mandatoryQueue_in.dequeue();
 173   }
 174
 175   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
 176     sequencer.readCallback(address, dummyData);
 177   }
 178
 179   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
 180     sequencer.writeCallback(address, dummyData);
 181   }
 182
 183
 184   // TRANSITIONS
 185
 186   // sequencer hit call back is performed after injecting the packets.
 187   // The goal of the Network_test protocol is only to inject packets into
 188   // the network, not to keep track of them via TBEs.
 189
 190   transition(I, Response) {
 191     s_store_hit;
 192     c_issueResponse;
 193     m_popMandatoryQueue;
 194   }
 195
 196   transition(I, Request) {
 197     r_load_hit;
 198     a_issueRequest;
 199     m_popMandatoryQueue;
 200   }
 201   transition(I, Forward) {
 202     r_load_hit;
 203     b_issueForward;
 204     m_popMandatoryQueue;
 205   }
 206
 207 }