This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file...
[gem5.git] / src / mem / protocol / RubySlicc_Exports.sm
1
2 /*
3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * $Id$
32 *
33 */
34
35 // defines
36 external_type(int, primitive="yes", default="0");
37 external_type(bool, primitive="yes", default="false");
38 external_type(std::string, primitive="yes");
39 external_type(uint64, primitive="yes");
40 external_type(Time, primitive="yes", default="0");
41 external_type(Address);
42 external_type(DataBlock, desc="..."){
43 void clear();
44 void copyPartial(DataBlock, int, int);
45 }
46
47 // Declarations of external types that are common to all protocols
48
49 // AccessPermission
50 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
51 Busy, desc="No Read or Write";
52 Read_Only, desc="Read Only";
53 Read_Write, desc="Read/Write";
54 Invalid, desc="Invalid";
55 NotPresent, desc="NotPresent";
56 ReadUpgradingToWrite, desc="Read only, but trying to get Read/Write";
57 Stale, desc="local L1 has a modified copy, assume L2 copy is stale data";
58 }
59
60 // TesterStatus
61 enumeration(TesterStatus, desc="...") {
62 Idle, desc="Idle";
63 Action_Pending, desc="Action Pending";
64 Ready, desc="Ready";
65 Check_Pending, desc="Check Pending";
66 }
67
68 // InvalidateGeneratorStatus
69 enumeration(InvalidateGeneratorStatus, desc="...") {
70 Load_Waiting, desc="Load waiting to be issued";
71 Load_Pending, desc="Load issued";
72 Inv_Waiting, desc="Store (invalidate) waiting to be issued";
73 Inv_Pending, desc="Store (invalidate) issued";
74 }
75
76 // SeriesRequestGeneratorStatus
77 enumeration(SeriesRequestGeneratorStatus, desc="...") {
78 Thinking, desc="Doing work before next action";
79 Request_Pending, desc="Request pending";
80 }
81
82 // LockStatus
83 enumeration(LockStatus, desc="...") {
84 Unlocked, desc="Lock is not held";
85 Locked, desc="Lock is held";
86 }
87
88 // SequencerStatus
89 enumeration(SequencerStatus, desc="...") {
90 Idle, desc="Idle";
91 Pending, desc="Pending";
92 }
93
94 enumeration(TransitionResult, desc="...") {
95 Valid, desc="Valid transition";
96 ResourceStall, desc="Stalled due to insufficient resources";
97 ProtocolStall, desc="Protocol specified stall";
98 }
99
100 // CacheRequestType
101 enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
102 LD, desc="Load";
103 ST, desc="Store";
104 ATOMIC, desc="Atomic Load/Store";
105 IFETCH, desc="Instruction fetch";
106 IO, desc="I/O";
107 REPLACEMENT, desc="Replacement";
108 COMMIT, desc="Commit version";
109 NULL, desc="Invalid request type";
110 }
111
112 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
113 LD, desc="Load";
114 ST, desc="Store";
115 NULL, desc="Invalid request type";
116 }
117
118 enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
119 GETS, desc="gets request";
120 GET_INSTR, desc="get instr request";
121 GETX, desc="getx request";
122 UPGRADE, desc="upgrade request";
123 DOWNGRADE, desc="downgrade request";
124 INV, desc="invalidate request";
125 INV_S, desc="invalidate shared copy request";
126 PUTS, desc="puts request";
127 PUTO, desc="puto request";
128 PUTX, desc="putx request";
129 L2_PF, desc="L2 prefetch";
130 LD, desc="Load";
131 ST, desc="Store";
132 ATOMIC, desc="Atomic Load/Store";
133 IFETCH, desc="Instruction fetch";
134 IO, desc="I/O";
135 NACK, desc="Nack";
136 REPLACEMENT, desc="Replacement";
137 WB_ACK, desc="WriteBack ack";
138 EXE_ACK, desc="Execlusive ack";
139 COMMIT, desc="Commit version";
140 LD_XACT, desc="Transactional Load";
141 LDX_XACT, desc="Transactional Load-Intend-Modify";
142 ST_XACT, desc="Transactional Store";
143 BEGIN_XACT, desc="Begin Transaction";
144 COMMIT_XACT, desc="Commit Transaction";
145 ABORT_XACT, desc="Abort Transaction";
146 DMA_READ, desc="DMA READ";
147 DMA_WRITE, desc="DMA WRITE";
148 NULL, desc="null request type";
149 }
150
151 enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
152 L1Cache, desc="L1 Cache Mach";
153 L2Cache, desc="L2 Cache Mach";
154 L3Cache, desc="L3 Cache Mach";
155 Directory, desc="Directory Mach";
156 Collector, desc="Collector Mach";
157 L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
158 L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
159 NULL, desc="null mach type";
160 }
161
162 // MessageSizeType
163 enumeration(MessageSizeType, default="MessageSizeType_Undefined", desc="...") {
164 Undefined, desc="Undefined";
165 Control, desc="Control Message";
166 Data, desc="Data Message";
167 Request_Control, desc="Request";
168 Reissue_Control, desc="Reissued request";
169 Response_Data, desc="data response";
170 ResponseL2hit_Data, desc="data response";
171 ResponseLocal_Data, desc="data response";
172 Response_Control, desc="non-data response";
173 Writeback_Data, desc="Writeback data";
174 Writeback_Control, desc="Writeback control";
175 Broadcast_Control, desc="Broadcast control";
176 Forwarded_Control, desc="Forwarded control";
177 Invalidate_Control, desc="Invalidate control";
178 Unblock_Control, desc="Unblock control";
179 Persistent_Control, desc="Persistent request activation messages";
180 Completion_Control, desc="Completion messages";
181 }
182
183 // AccessType
184 enumeration(AccessType, desc="...") {
185 Read, desc="Reading from cache";
186 Write, desc="Writing to cache";
187 }
188
189 // AccessModeType
190 enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
191 SupervisorMode, desc="Supervisor mode";
192 UserMode, desc="User mode";
193 }
194
195 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
196 No, desc="No, not a prefetch";
197 Yes, desc="Yes, a prefetch";
198 L1_HW, desc="This is a L1 hardware prefetch";
199 L2_HW, desc="This is a L2 hardware prefetch";
200 }
201
202 // CacheMsg
203 structure(CacheMsg, desc="...", interface="Message") {
204 Address LineAddress, desc="Line address for this request";
205 Address PhysicalAddress, desc="Physical address for this request";
206 CacheRequestType Type, desc="Type of request (LD, ST, etc)";
207 Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
208 AccessModeType AccessMode, desc="user/supervisor access type";
209 int Size, desc="size in bytes of access";
210 PrefetchBit Prefetch, desc="Is this a prefetch request";
211 }
212
213 // CacheMsg
214 structure(SequencerMsg, desc="...", interface="Message") {
215 Address LineAddress, desc="Line address for this request";
216 Address PhysicalAddress, desc="Physical address for this request";
217 SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
218 Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
219 AccessModeType AccessMode, desc="user/supervisor access type";
220 DataBlock DataBlk, desc="Data";
221 int Len, desc="size in bytes of access";
222 PrefetchBit Prefetch, desc="Is this a prefetch request";
223 }
224
225 // MaskPredictorType
226 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
227 Undefined, desc="Undefined";
228 AlwaysUnicast, desc="AlwaysUnicast";
229 TokenD, desc="TokenD";
230 AlwaysBroadcast, desc="AlwaysBroadcast";
231 TokenB, desc="TokenB";
232 TokenNull, desc="TokenNull";
233 Random, desc="Random";
234 Pairwise, desc="Pairwise";
235 Owner, desc="Owner";
236 BroadcastIfShared, desc="Broadcast-If-Shared";
237 BroadcastCounter, desc="Broadcast Counter";
238 Group, desc="Group";
239 Counter, desc="Counter";
240 StickySpatial, desc="StickySpatial";
241 OwnerBroadcast, desc="Owner/Broadcast Hybrid";
242 OwnerGroup, desc="Owner/Group Hybrid";
243 OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
244 OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
245 LastNMasks, desc="Last N Masks";
246 BandwidthAdaptive, desc="Bandwidth Adaptive";
247 }
248
249 // MaskPredictorIndex
250 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
251 Undefined, desc="Undefined";
252 DataBlock, desc="Data Block";
253 PC, desc="Program Counter";
254 }
255
256 // MaskPredictorTraining
257 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
258 Undefined, desc="Undefined";
259 None, desc="None";
260 Implicit, desc="Implicit";
261 Explicit, desc="Explicit";
262 Both, desc="Both";
263 }
264
265 // Network Topologies
266 enumeration(TopologyType, desc="...") {
267 CROSSBAR, desc="One node per chip, single switch crossbar";
268 HIERARCHICAL_SWITCH, desc="One node per chip, totally ordered hierarchical tree switched network";
269 TORUS_2D, desc="One node per chip, 2D torus";
270 PT_TO_PT, desc="One node per chip, Point to Point Network";
271 FILE_SPECIFIED, desc="described by the file NETWORK_FILE";
272 }
273
274 // DNUCA AllocationStrategy
275 enumeration(AllocationStrategy, desc="...") {
276 InMiddle, desc="";
277 InInvCorners, desc="";
278 InSharedSides, desc="";
279 StaticDist, desc="";
280 RandomBank, desc="";
281 FrequencyBank, desc="";
282 FrequencyBlock, desc="";
283 LRUBlock, desc="";
284 }
285
286 // DNUCA SearchMechanism
287 enumeration(SearchMechanism, desc="...") {
288 Perfect, desc="";
289 PartialTag, desc="";
290 BloomFilter, desc="";
291 Random, desc="";
292 None, desc="";
293 }
294
295 // DNUCA link type
296 enumeration(LinkType, desc="...") {
297 RC_1500UM, desc="";
298 RC_2500UM, desc="";
299 TL_9000UM, desc="";
300 TL_11000UM, desc="";
301 TL_13000UM, desc="";
302 NO_ENERGY, desc="";
303 NULL, desc="";
304 }
305
306 // transient request type
307 enumeration(TransientRequestType, desc="...", default="TransientRequestType_Undefined") {
308 Undefined, desc="";
309 OffChip, desc="";
310 OnChip, desc="";
311 LocalTransient, desc="";
312 }
313
314 // Request Status
315 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL") {
316 Ready, desc="The sequencer is ready and the request does not alias";
317 Issued, desc="The sequencer successfully issued the request";
318 BufferFull, desc="Can not issue because the sequencer is full";
319 Aliased, desc="This request aliased with a currently outstanding request";
320 NULL, desc="";
321 }