src/mem/protocol/RubySlicc_Exports.sm

   1 /*
   2  * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2011 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 // Declarations of external types that are common to all protocols
  31 external_type(int, primitive="yes", default="0");
  32 external_type(bool, primitive="yes", default="false");
  33 external_type(std::string, primitive="yes");
  34 external_type(uint32_t, primitive="yes");
  35 external_type(uint64, primitive="yes");
  36 external_type(Time, primitive="yes", default="0");
  37 external_type(PacketPtr, primitive="yes");
  38 external_type(Packet, primitive="yes");
  39 external_type(Address);
  40
  41 structure(DataBlock, external = "yes", desc="..."){
  42   void clear();
  43   void copyPartial(DataBlock, int, int);
  44 }
  45
  46 bool testAndRead(Address addr, DataBlock datablk, Packet *pkt);
  47 bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt);
  48
  49 // AccessPermission
  50 // The following five states define the access permission of all memory blocks.
  51 // These permissions have multiple uses.  They coordinate locking and
  52 // synchronization primitives, as well as enable functional accesses.
  53 // One should not need to add any additional permission values and it is very
  54 // risky to do so.
  55 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  56   // Valid data
  57   Read_Only,  desc="block is Read Only (modulo functional writes)";
  58   Read_Write, desc="block is Read/Write";
  59
  60   // Possibly Invalid data
  61   // The maybe stale permission indicates that accordingly to the protocol,
  62   // there is no guarantee the block contains valid data.  However, functional
  63   // writes should update the block because a dataless PUT request may
  64   // revalidate the block's data.
  65   Maybe_Stale, desc="block can be stale or revalidated by a dataless PUT";
  66   // In Broadcast/Snoop protocols, memory has no idea if it is exclusive owner
  67   // or not of a block, making it hard to make the logic of having only one
  68   // read_write block in the system impossible. This is to allow the memory to
  69   // say, "I have the block" and for the RubyPort logic to know that this is a
  70   // last-resort block if there are no writable copies in the caching hierarchy.
  71   // This is not supposed to be used in directory or token protocols where
  72   // memory/NB has an idea of what is going on in the whole system.
  73   Backing_Store, desc="for memory in Broadcast/Snoop protocols";
  74
  75   // Invalid data
  76   Invalid,    desc="block is in an Invalid base state";
  77   NotPresent, desc="block is NotPresent";
  78   Busy,       desc="block is in a transient state, currently invalid";
  79 }
  80
  81 // TesterStatus
  82 enumeration(TesterStatus, desc="...") {
  83   Idle,            desc="Idle";
  84   Action_Pending,  desc="Action Pending";
  85   Ready,           desc="Ready";
  86   Check_Pending,   desc="Check Pending";
  87 }
  88
  89 // InvalidateGeneratorStatus
  90 enumeration(InvalidateGeneratorStatus, desc="...") {
  91   Load_Waiting,    desc="Load waiting to be issued";
  92   Load_Pending,    desc="Load issued";
  93   Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
  94   Inv_Pending,     desc="Store (invalidate) issued";
  95 }
  96
  97 // SeriesRequestGeneratorStatus
  98 enumeration(SeriesRequestGeneratorStatus, desc="...") {
  99   Thinking,        desc="Doing work before next action";
 100   Request_Pending, desc="Request pending";
 101 }
 102
 103 // LockStatus
 104 enumeration(LockStatus, desc="...") {
 105   Unlocked,        desc="Lock is not held";
 106   Locked,          desc="Lock is held";
 107 }
 108
 109 // SequencerStatus
 110 enumeration(SequencerStatus, desc="...") {
 111   Idle,            desc="Idle";
 112   Pending,         desc="Pending";
 113 }
 114
 115 enumeration(TransitionResult, desc="...") {
 116   Valid,         desc="Valid transition";
 117   ResourceStall, desc="Stalled due to insufficient resources";
 118   ProtocolStall, desc="Protocol specified stall";
 119 }
 120
 121 // RubyRequestType
 122 enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
 123   LD,                desc="Load";
 124   ST,                desc="Store";
 125   ATOMIC,            desc="Atomic Load/Store";
 126   IFETCH,            desc="Instruction fetch";
 127   IO,                desc="I/O";
 128   REPLACEMENT,       desc="Replacement";
 129   Load_Linked,       desc="";
 130   Store_Conditional, desc="";
 131   RMW_Read,          desc="";
 132   RMW_Write,         desc="";
 133   Locked_RMW_Read,   desc="";
 134   Locked_RMW_Write,  desc="";
 135   COMMIT,            desc="Commit version";
 136   NULL,              desc="Invalid request type";
 137   FLUSH,             desc="Flush request type";
 138 }
 139
 140 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
 141   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 142   LD,          desc="Load";
 143   ST,          desc="Store";
 144   NULL,        desc="Invalid request type";
 145 }
 146
 147 enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
 148   GETS,        desc="gets request";
 149   GET_INSTR,   desc="get instr request";
 150   GETX,        desc="getx request";
 151   UPGRADE,     desc="upgrade request";
 152   DOWNGRADE,   desc="downgrade request";
 153   INV,         desc="invalidate request";
 154   INV_S,       desc="invalidate shared copy request";
 155   PUTS,        desc="puts request";
 156   PUTO,        desc="puto request";
 157   PUTX,        desc="putx request";
 158   L2_PF,       desc="L2 prefetch";
 159   LD,          desc="Load";
 160   ST,          desc="Store";
 161   ATOMIC,      desc="Atomic Load/Store";
 162   IFETCH,      desc="Instruction fetch";
 163   IO,          desc="I/O";
 164   NACK,        desc="Nack";
 165   REPLACEMENT, desc="Replacement";
 166   WB_ACK,      desc="WriteBack ack";
 167   EXE_ACK,     desc="Execlusive ack";
 168   COMMIT,      desc="Commit version";
 169   LD_XACT,     desc="Transactional Load";
 170   LDX_XACT,     desc="Transactional Load-Intend-Modify";
 171   ST_XACT,     desc="Transactional Store";
 172   BEGIN_XACT,  desc="Begin Transaction";
 173   COMMIT_XACT, desc="Commit Transaction";
 174   ABORT_XACT,  desc="Abort Transaction";
 175   DMA_READ,    desc="DMA READ";
 176   DMA_WRITE,   desc="DMA WRITE";
 177   NULL,        desc="null request type";
 178 }
 179
 180 enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
 181   DataArrayRead,    desc="Read access to the cache's data array";
 182   DataArrayWrite,   desc="Write access to the cache's data array";
 183   TagArrayRead,     desc="Read access to the cache's tag array";
 184   TagArrayWrite,    desc="Write access to the cache's tag array";
 185 }
 186
 187 enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") {
 188   DataArray,    desc="Access to the cache's data array";
 189   TagArray,     desc="Access to the cache's tag array";
 190 }
 191
 192 enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
 193   Default,    desc="Replace this with access_types passed to the Directory Ruby object";
 194 }
 195
 196 enumeration(DMASequencerRequestType, desc="...", default="DMASequencerRequestType_NULL") {
 197   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 198 }
 199
 200 enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestType_NULL") {
 201   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 202 }
 203
 204 enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
 205   L1Cache,     desc="L1 Cache Mach";
 206   L2Cache,     desc="L2 Cache Mach";
 207   L3Cache,     desc="L3 Cache Mach";
 208   Directory,   desc="Directory Mach";
 209   DMA,         desc="DMA Mach";
 210   Collector,   desc="Collector Mach";
 211   L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 212   L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 213   NULL,        desc="null mach type";
 214 }
 215
 216 // MessageSizeType
 217 enumeration(MessageSizeType, default="MessageSizeType_Undefined", desc="...") {
 218   Undefined,  desc="Undefined";
 219   Control,    desc="Control Message";
 220   Data,       desc="Data Message";
 221   Request_Control, desc="Request";
 222   Reissue_Control, desc="Reissued request";
 223   Response_Data, desc="data response";
 224   ResponseL2hit_Data, desc="data response";
 225   ResponseLocal_Data, desc="data response";
 226   Response_Control, desc="non-data response";
 227   Writeback_Data, desc="Writeback data";
 228   Writeback_Control, desc="Writeback control";
 229   Broadcast_Control, desc="Broadcast control";
 230   Multicast_Control, desc="Multicast control";
 231   Forwarded_Control, desc="Forwarded control";
 232   Invalidate_Control, desc="Invalidate control";
 233   Unblock_Control, desc="Unblock control";
 234   Persistent_Control, desc="Persistent request activation messages";
 235   Completion_Control, desc="Completion messages";
 236 }
 237
 238 // AccessType
 239 enumeration(AccessType, desc="...") {
 240   Read, desc="Reading from cache";
 241   Write, desc="Writing to cache";
 242 }
 243
 244 // RubyAccessMode
 245 enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
 246   Supervisor, desc="Supervisor mode";
 247   User,       desc="User mode";
 248   Device, desc="Device mode";
 249 }
 250
 251 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
 252   No,    desc="No, not a prefetch";
 253   Yes,   desc="Yes, a prefetch";
 254   L1_HW, desc="This is a L1 hardware prefetch";
 255   L2_HW, desc="This is a L2 hardware prefetch";
 256 }
 257
 258 // CacheMsg
 259 structure(SequencerMsg, desc="...", interface="Message") {
 260   Address LineAddress,       desc="Line address for this request";
 261   Address PhysicalAddress,   desc="Physical address for this request";
 262   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
 263   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 264   RubyAccessMode AccessMode, desc="user/supervisor access type";
 265   DataBlock DataBlk,         desc="Data";
 266   int Len,                   desc="size in bytes of access";
 267   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 268
 269   bool functionalRead(Packet *pkt) {
 270     return testAndRead(PhysicalAddress, DataBlk, pkt);
 271   }
 272
 273   bool functionalWrite(Packet *pkt) {
 274     return testAndWrite(PhysicalAddress, DataBlk, pkt);
 275   }
 276 }
 277
 278 // MaskPredictorType
 279 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
 280   Undefined, desc="Undefined";
 281   AlwaysUnicast, desc="AlwaysUnicast";
 282   TokenD, desc="TokenD";
 283   AlwaysBroadcast, desc="AlwaysBroadcast";
 284   TokenB, desc="TokenB";
 285   TokenNull, desc="TokenNull";
 286   Random, desc="Random";
 287   Pairwise, desc="Pairwise";
 288   Owner, desc="Owner";
 289   BroadcastIfShared, desc="Broadcast-If-Shared";
 290   BroadcastCounter, desc="Broadcast Counter";
 291   Group, desc="Group";
 292   Counter, desc="Counter";
 293   StickySpatial, desc="StickySpatial";
 294   OwnerBroadcast, desc="Owner/Broadcast Hybrid";
 295   OwnerGroup, desc="Owner/Group Hybrid";
 296   OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
 297   OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
 298   LastNMasks, desc="Last N Masks";
 299   BandwidthAdaptive, desc="Bandwidth Adaptive";
 300 }
 301
 302 // MaskPredictorIndex
 303 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
 304   Undefined, desc="Undefined";
 305   DataBlock, desc="Data Block";
 306   PC, desc="Program Counter";
 307 }
 308
 309 // MaskPredictorTraining
 310 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
 311   Undefined, desc="Undefined";
 312   None, desc="None";
 313   Implicit, desc="Implicit";
 314   Explicit, desc="Explicit";
 315   Both, desc="Both";
 316 }
 317
 318 // Request Status
 319 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
 320   Ready, desc="The sequencer is ready and the request does not alias";
 321   Issued, desc="The sequencer successfully issued the request";
 322   BufferFull, desc="Can not issue because the sequencer is full";
 323   Aliased, desc="This request aliased with a currently outstanding request";
 324   NULL, desc="";
 325 }
 326
 327 // LinkDirection
 328 enumeration(LinkDirection, desc="...") {
 329   In, desc="Inward link direction";
 330   Out, desc="Outward link direction";
 331 }