src/mem/protocol/RubySlicc_Exports.sm

   1 /*
   2  * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2011 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 // Declarations of external types that are common to all protocols
  31 external_type(int, primitive="yes", default="0");
  32 external_type(bool, primitive="yes", default="false");
  33 external_type(std::string, primitive="yes");
  34 external_type(uint32_t, primitive="yes");
  35 external_type(uint64_t, primitive="yes");
  36 external_type(PacketPtr, primitive="yes");
  37 external_type(Packet, primitive="yes");
  38 external_type(Addr, primitive="yes");
  39 external_type(Cycles, primitive="yes", default="Cycles(0)");
  40 external_type(Tick, primitive="yes", default="0");
  41
  42 structure(DataBlock, external = "yes", desc="..."){
  43   void clear();
  44   void copyPartial(DataBlock, int, int);
  45 }
  46
  47 bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt);
  48 bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt);
  49
  50 // AccessPermission
  51 // The following five states define the access permission of all memory blocks.
  52 // These permissions have multiple uses.  They coordinate locking and
  53 // synchronization primitives, as well as enable functional accesses.
  54 // One should not need to add any additional permission values and it is very
  55 // risky to do so.
  56 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  57   // Valid data
  58   Read_Only,  desc="block is Read Only (modulo functional writes)";
  59   Read_Write, desc="block is Read/Write";
  60
  61   // Possibly Invalid data
  62   // The maybe stale permission indicates that accordingly to the protocol,
  63   // there is no guarantee the block contains valid data.  However, functional
  64   // writes should update the block because a dataless PUT request may
  65   // revalidate the block's data.
  66   Maybe_Stale, desc="block can be stale or revalidated by a dataless PUT";
  67   // In Broadcast/Snoop protocols, memory has no idea if it is exclusive owner
  68   // or not of a block, making it hard to make the logic of having only one
  69   // read_write block in the system impossible. This is to allow the memory to
  70   // say, "I have the block" and for the RubyPort logic to know that this is a
  71   // last-resort block if there are no writable copies in the caching hierarchy.
  72   // This is not supposed to be used in directory or token protocols where
  73   // memory/NB has an idea of what is going on in the whole system.
  74   Backing_Store, desc="for memory in Broadcast/Snoop protocols";
  75
  76   // Invalid data
  77   Invalid,    desc="block is in an Invalid base state";
  78   NotPresent, desc="block is NotPresent";
  79   Busy,       desc="block is in a transient state, currently invalid";
  80 }
  81
  82 // TesterStatus
  83 enumeration(TesterStatus, desc="...") {
  84   Idle,            desc="Idle";
  85   Action_Pending,  desc="Action Pending";
  86   Ready,           desc="Ready";
  87   Check_Pending,   desc="Check Pending";
  88 }
  89
  90 // InvalidateGeneratorStatus
  91 enumeration(InvalidateGeneratorStatus, desc="...") {
  92   Load_Waiting,    desc="Load waiting to be issued";
  93   Load_Pending,    desc="Load issued";
  94   Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
  95   Inv_Pending,     desc="Store (invalidate) issued";
  96 }
  97
  98 // SeriesRequestGeneratorStatus
  99 enumeration(SeriesRequestGeneratorStatus, desc="...") {
 100   Thinking,        desc="Doing work before next action";
 101   Request_Pending, desc="Request pending";
 102 }
 103
 104 // LockStatus
 105 enumeration(LockStatus, desc="...") {
 106   Unlocked,        desc="Lock is not held";
 107   Locked,          desc="Lock is held";
 108 }
 109
 110 // SequencerStatus
 111 enumeration(SequencerStatus, desc="...") {
 112   Idle,            desc="Idle";
 113   Pending,         desc="Pending";
 114 }
 115
 116 enumeration(TransitionResult, desc="...") {
 117   Valid,         desc="Valid transition";
 118   ResourceStall, desc="Stalled due to insufficient resources";
 119   ProtocolStall, desc="Protocol specified stall";
 120   Reject,        desc="Rejected because of a type mismatch";
 121 }
 122
 123 // RubyRequestType
 124 enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
 125   LD,                desc="Load";
 126   ST,                desc="Store";
 127   ATOMIC,            desc="Atomic Load/Store";
 128   IFETCH,            desc="Instruction fetch";
 129   IO,                desc="I/O";
 130   REPLACEMENT,       desc="Replacement";
 131   Load_Linked,       desc="";
 132   Store_Conditional, desc="";
 133   RMW_Read,          desc="";
 134   RMW_Write,         desc="";
 135   Locked_RMW_Read,   desc="";
 136   Locked_RMW_Write,  desc="";
 137   COMMIT,            desc="Commit version";
 138   NULL,              desc="Invalid request type";
 139   FLUSH,             desc="Flush request type";
 140   Release,           desc="Release operation";
 141   Acquire,           desc="Acquire opertion";
 142   AcquireRelease,    desc="Acquire and Release opertion";
 143 }
 144
 145 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
 146   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 147   LD,          desc="Load";
 148   ST,          desc="Store";
 149   NULL,        desc="Invalid request type";
 150 }
 151
 152 enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
 153   DataArrayRead,    desc="Read access to the cache's data array";
 154   DataArrayWrite,   desc="Write access to the cache's data array";
 155   TagArrayRead,     desc="Read access to the cache's tag array";
 156   TagArrayWrite,    desc="Write access to the cache's tag array";
 157 }
 158
 159 enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") {
 160   DataArray,    desc="Access to the cache's data array";
 161   TagArray,     desc="Access to the cache's tag array";
 162 }
 163
 164 enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
 165   Default,    desc="Replace this with access_types passed to the Directory Ruby object";
 166 }
 167
 168 enumeration(DMASequencerRequestType, desc="...", default="DMASequencerRequestType_NULL") {
 169   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 170 }
 171
 172 enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestType_NULL") {
 173   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 174 }
 175
 176 // MessageSizeType
 177 enumeration(MessageSizeType, desc="...") {
 178   Control,    desc="Control Message";
 179   Data,       desc="Data Message";
 180   Request_Control, desc="Request";
 181   Reissue_Control, desc="Reissued request";
 182   Response_Data, desc="data response";
 183   ResponseL2hit_Data, desc="data response";
 184   ResponseLocal_Data, desc="data response";
 185   Response_Control, desc="non-data response";
 186   Writeback_Data, desc="Writeback data";
 187   Writeback_Control, desc="Writeback control";
 188   Broadcast_Control, desc="Broadcast control";
 189   Multicast_Control, desc="Multicast control";
 190   Forwarded_Control, desc="Forwarded control";
 191   Invalidate_Control, desc="Invalidate control";
 192   Unblock_Control, desc="Unblock control";
 193   Persistent_Control, desc="Persistent request activation messages";
 194   Completion_Control, desc="Completion messages";
 195 }
 196
 197 // AccessType
 198 enumeration(AccessType, desc="...") {
 199   Read, desc="Reading from cache";
 200   Write, desc="Writing to cache";
 201 }
 202
 203 // RubyAccessMode
 204 enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
 205   Supervisor, desc="Supervisor mode";
 206   User,       desc="User mode";
 207   Device, desc="Device mode";
 208 }
 209
 210 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
 211   No,    desc="No, not a prefetch";
 212   Yes,   desc="Yes, a prefetch";
 213   L1_HW, desc="This is a L1 hardware prefetch";
 214   L2_HW, desc="This is a L2 hardware prefetch";
 215 }
 216
 217 // CacheMsg
 218 structure(SequencerMsg, desc="...", interface="Message") {
 219   Addr LineAddress,       desc="Line address for this request";
 220   Addr PhysicalAddress,   desc="Physical address for this request";
 221   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
 222   Addr ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 223   RubyAccessMode AccessMode, desc="user/supervisor access type";
 224   DataBlock DataBlk,         desc="Data";
 225   int Len,                   desc="size in bytes of access";
 226   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 227   MessageSizeType MessageSize;
 228
 229   bool functionalRead(Packet *pkt) {
 230     return testAndRead(PhysicalAddress, DataBlk, pkt);
 231   }
 232
 233   bool functionalWrite(Packet *pkt) {
 234     return testAndWrite(PhysicalAddress, DataBlk, pkt);
 235   }
 236 }
 237
 238 // MaskPredictorType
 239 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
 240   Undefined, desc="Undefined";
 241   AlwaysUnicast, desc="AlwaysUnicast";
 242   TokenD, desc="TokenD";
 243   AlwaysBroadcast, desc="AlwaysBroadcast";
 244   TokenB, desc="TokenB";
 245   TokenNull, desc="TokenNull";
 246   Random, desc="Random";
 247   Pairwise, desc="Pairwise";
 248   Owner, desc="Owner";
 249   BroadcastIfShared, desc="Broadcast-If-Shared";
 250   BroadcastCounter, desc="Broadcast Counter";
 251   Group, desc="Group";
 252   Counter, desc="Counter";
 253   StickySpatial, desc="StickySpatial";
 254   OwnerBroadcast, desc="Owner/Broadcast Hybrid";
 255   OwnerGroup, desc="Owner/Group Hybrid";
 256   OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
 257   OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
 258   LastNMasks, desc="Last N Masks";
 259   BandwidthAdaptive, desc="Bandwidth Adaptive";
 260 }
 261
 262 // MaskPredictorIndex
 263 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
 264   Undefined, desc="Undefined";
 265   DataBlock, desc="Data Block";
 266   PC, desc="Program Counter";
 267 }
 268
 269 // MaskPredictorTraining
 270 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
 271   Undefined, desc="Undefined";
 272   None, desc="None";
 273   Implicit, desc="Implicit";
 274   Explicit, desc="Explicit";
 275   Both, desc="Both";
 276 }
 277
 278 // Request Status
 279 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
 280   Ready, desc="The sequencer is ready and the request does not alias";
 281   Issued, desc="The sequencer successfully issued the request";
 282   BufferFull, desc="Can not issue because the sequencer is full";
 283   Aliased, desc="This request aliased with a currently outstanding request";
 284   NULL, desc="";
 285 }
 286
 287 // LinkDirection
 288 enumeration(LinkDirection, desc="...") {
 289   In, desc="Inward link direction";
 290   Out, desc="Outward link direction";
 291 }