src/mem/protocol/RubySlicc_Exports.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  *
  33  */
  34
  35 // defines
  36 external_type(int, primitive="yes", default="0");
  37 external_type(bool, primitive="yes", default="false");
  38 external_type(std::string, primitive="yes");
  39 external_type(uint64, primitive="yes");
  40 external_type(Time, primitive="yes", default="0");
  41 external_type(Address);
  42 external_type(DataBlock, desc="..."){
  43   void clear();
  44   void copyPartial(DataBlock, int, int);
  45 }
  46
  47 // Declarations of external types that are common to all protocols
  48
  49 // AccessPermission
  50 // The following five states define the access permission of all memory blocks.
  51 // These permissions have multiple uses.  They coordinate locking and
  52 // synchronization primitives, as well as enable functional accesses.
  53 // One should not need to add any additional permission values and it is very
  54 // risky to do so.
  55 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  56   // Valid data
  57   Read_Only,  desc="block is Read Only (modulo functional writes)";
  58   Read_Write, desc="block is Read/Write";
  59
  60   // Invalid data
  61   Invalid,    desc="block is in an Invalid base state";
  62   NotPresent, desc="block is NotPresent";
  63   Busy,       desc="block is in a transient state, currently invalid";
  64 }
  65
  66 // TesterStatus
  67 enumeration(TesterStatus, desc="...") {
  68   Idle,            desc="Idle";
  69   Action_Pending,  desc="Action Pending";
  70   Ready,           desc="Ready";
  71   Check_Pending,   desc="Check Pending";
  72 }
  73
  74 // InvalidateGeneratorStatus
  75 enumeration(InvalidateGeneratorStatus, desc="...") {
  76   Load_Waiting,    desc="Load waiting to be issued";
  77   Load_Pending,    desc="Load issued";
  78   Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
  79   Inv_Pending,     desc="Store (invalidate) issued";
  80 }
  81
  82 // SeriesRequestGeneratorStatus
  83 enumeration(SeriesRequestGeneratorStatus, desc="...") {
  84   Thinking,        desc="Doing work before next action";
  85   Request_Pending, desc="Request pending";
  86 }
  87
  88 // LockStatus
  89 enumeration(LockStatus, desc="...") {
  90   Unlocked,        desc="Lock is not held";
  91   Locked,          desc="Lock is held";
  92 }
  93
  94 // SequencerStatus
  95 enumeration(SequencerStatus, desc="...") {
  96   Idle,            desc="Idle";
  97   Pending,         desc="Pending";
  98 }
  99
 100 enumeration(TransitionResult, desc="...") {
 101   Valid,         desc="Valid transition";
 102   ResourceStall, desc="Stalled due to insufficient resources";
 103   ProtocolStall, desc="Protocol specified stall";
 104 }
 105
 106 // CacheRequestType
 107 enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
 108   LD,          desc="Load";
 109   ST,          desc="Store";
 110   ATOMIC,      desc="Atomic Load/Store";
 111   IFETCH,      desc="Instruction fetch";
 112   IO,          desc="I/O";
 113   REPLACEMENT, desc="Replacement";
 114   COMMIT,      desc="Commit version";
 115   NULL,        desc="Invalid request type";
 116 }
 117
 118 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
 119   LD,          desc="Load";
 120   ST,          desc="Store";
 121   NULL,        desc="Invalid request type";
 122 }
 123
 124 enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
 125   GETS,        desc="gets request";
 126   GET_INSTR,   desc="get instr request";
 127   GETX,        desc="getx request";
 128   UPGRADE,     desc="upgrade request";
 129   DOWNGRADE,   desc="downgrade request";
 130   INV,         desc="invalidate request";
 131   INV_S,       desc="invalidate shared copy request";
 132   PUTS,        desc="puts request";
 133   PUTO,        desc="puto request";
 134   PUTX,        desc="putx request";
 135   L2_PF,       desc="L2 prefetch";
 136   LD,          desc="Load";
 137   ST,          desc="Store";
 138   ATOMIC,      desc="Atomic Load/Store";
 139   IFETCH,      desc="Instruction fetch";
 140   IO,          desc="I/O";
 141   NACK,        desc="Nack";
 142   REPLACEMENT, desc="Replacement";
 143   WB_ACK,      desc="WriteBack ack";
 144   EXE_ACK,     desc="Execlusive ack";
 145   COMMIT,      desc="Commit version";
 146   LD_XACT,     desc="Transactional Load";
 147   LDX_XACT,     desc="Transactional Load-Intend-Modify";
 148   ST_XACT,     desc="Transactional Store";
 149   BEGIN_XACT,  desc="Begin Transaction";
 150   COMMIT_XACT, desc="Commit Transaction";
 151   ABORT_XACT,  desc="Abort Transaction";
 152   DMA_READ,    desc="DMA READ";
 153   DMA_WRITE,   desc="DMA WRITE";
 154   NULL,        desc="null request type";
 155 }
 156
 157 enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
 158   L1Cache,     desc="L1 Cache Mach";
 159   L2Cache,     desc="L2 Cache Mach";
 160   L3Cache,     desc="L3 Cache Mach";
 161   Directory,   desc="Directory Mach";
 162   Collector,   desc="Collector Mach";
 163   L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 164   L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 165   NULL,        desc="null mach type";
 166 }
 167
 168 // MessageSizeType
 169 enumeration(MessageSizeType, default="MessageSizeType_Undefined", desc="...") {
 170   Undefined,  desc="Undefined";
 171   Control,    desc="Control Message";
 172   Data,       desc="Data Message";
 173   Request_Control, desc="Request";
 174   Reissue_Control, desc="Reissued request";
 175   Response_Data, desc="data response";
 176   ResponseL2hit_Data, desc="data response";
 177   ResponseLocal_Data, desc="data response";
 178   Response_Control, desc="non-data response";
 179   Writeback_Data, desc="Writeback data";
 180   Writeback_Control, desc="Writeback control";
 181   Broadcast_Control, desc="Broadcast control";
 182   Multicast_Control, desc="Multicast control";
 183   Forwarded_Control, desc="Forwarded control";
 184   Invalidate_Control, desc="Invalidate control";
 185   Unblock_Control, desc="Unblock control";
 186   Persistent_Control, desc="Persistent request activation messages";
 187   Completion_Control, desc="Completion messages";
 188 }
 189
 190 // AccessType
 191 enumeration(AccessType, desc="...") {
 192   Read, desc="Reading from cache";
 193   Write, desc="Writing to cache";
 194 }
 195
 196 // AccessModeType
 197 enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
 198   SupervisorMode, desc="Supervisor mode";
 199   UserMode,       desc="User mode";
 200 }
 201
 202 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
 203   No,    desc="No, not a prefetch";
 204   Yes,   desc="Yes, a prefetch";
 205   L1_HW, desc="This is a L1 hardware prefetch";
 206   L2_HW, desc="This is a L2 hardware prefetch";
 207 }
 208
 209 // CacheMsg
 210 structure(CacheMsg, desc="...", interface="Message") {
 211   Address LineAddress,       desc="Line address for this request";
 212   Address PhysicalAddress,   desc="Physical address for this request";
 213   CacheRequestType Type,     desc="Type of request (LD, ST, etc)";
 214   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 215   AccessModeType AccessMode, desc="user/supervisor access type";
 216   int Size,                  desc="size in bytes of access";
 217   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 218 }
 219
 220 // CacheMsg
 221 structure(SequencerMsg, desc="...", interface="Message") {
 222   Address LineAddress,       desc="Line address for this request";
 223   Address PhysicalAddress,   desc="Physical address for this request";
 224   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
 225   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 226   AccessModeType AccessMode, desc="user/supervisor access type";
 227   DataBlock DataBlk,         desc="Data";
 228   int Len,                   desc="size in bytes of access";
 229   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 230 }
 231
 232 // MaskPredictorType
 233 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
 234   Undefined, desc="Undefined";
 235   AlwaysUnicast, desc="AlwaysUnicast";
 236   TokenD, desc="TokenD";
 237   AlwaysBroadcast, desc="AlwaysBroadcast";
 238   TokenB, desc="TokenB";
 239   TokenNull, desc="TokenNull";
 240   Random, desc="Random";
 241   Pairwise, desc="Pairwise";
 242   Owner, desc="Owner";
 243   BroadcastIfShared, desc="Broadcast-If-Shared";
 244   BroadcastCounter, desc="Broadcast Counter";
 245   Group, desc="Group";
 246   Counter, desc="Counter";
 247   StickySpatial, desc="StickySpatial";
 248   OwnerBroadcast, desc="Owner/Broadcast Hybrid";
 249   OwnerGroup, desc="Owner/Group Hybrid";
 250   OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
 251   OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
 252   LastNMasks, desc="Last N Masks";
 253   BandwidthAdaptive, desc="Bandwidth Adaptive";
 254 }
 255
 256 // MaskPredictorIndex
 257 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
 258   Undefined, desc="Undefined";
 259   DataBlock, desc="Data Block";
 260   PC, desc="Program Counter";
 261 }
 262
 263 // MaskPredictorTraining
 264 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
 265   Undefined, desc="Undefined";
 266   None, desc="None";
 267   Implicit, desc="Implicit";
 268   Explicit, desc="Explicit";
 269   Both, desc="Both";
 270 }
 271
 272 // Network Topologies
 273 enumeration(TopologyType, desc="...") {
 274   CROSSBAR, desc="One node per chip, single switch crossbar";
 275   HIERARCHICAL_SWITCH, desc="One node per chip, totally ordered hierarchical tree switched network";
 276   TORUS_2D, desc="One node per chip, 2D torus";
 277   PT_TO_PT, desc="One node per chip, Point to Point Network";
 278   FILE_SPECIFIED, desc="described by the file NETWORK_FILE";
 279 }
 280
 281 // DNUCA AllocationStrategy
 282 enumeration(AllocationStrategy, desc="...") {
 283   InMiddle, desc="";
 284   InInvCorners, desc="";
 285   InSharedSides, desc="";
 286   StaticDist, desc="";
 287   RandomBank, desc="";
 288   FrequencyBank, desc="";
 289   FrequencyBlock, desc="";
 290   LRUBlock, desc="";
 291 }
 292
 293 // DNUCA SearchMechanism
 294 enumeration(SearchMechanism, desc="...") {
 295   Perfect, desc="";
 296   PartialTag, desc="";
 297   BloomFilter, desc="";
 298   Random, desc="";
 299   None, desc="";
 300 }
 301
 302 // DNUCA link type
 303 enumeration(LinkType, desc="...") {
 304   RC_1500UM, desc="";
 305   RC_2500UM, desc="";
 306   TL_9000UM, desc="";
 307   TL_11000UM, desc="";
 308   TL_13000UM, desc="";
 309   NO_ENERGY, desc="";
 310   NULL, desc="";
 311 }
 312
 313 // transient request type
 314 enumeration(TransientRequestType, desc="...", default="TransientRequestType_Undefined") {
 315   Undefined, desc="";
 316   OffChip, desc="";
 317   OnChip, desc="";
 318   LocalTransient, desc="";
 319 }
 320
 321 // Request Status
 322 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
 323   Ready, desc="The sequencer is ready and the request does not alias";
 324   Issued, desc="The sequencer successfully issued the request";
 325   BufferFull, desc="Can not issue because the sequencer is full";
 326   Aliased, desc="This request aliased with a currently outstanding request";
 327   NULL, desc="";
 328 }