src/mem/protocol/RubySlicc_Exports.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  *
  33  */
  34
  35 // defines
  36 external_type(int, primitive="yes", default="0");
  37 external_type(bool, primitive="yes", default="false");
  38 external_type(std::string, primitive="yes");
  39 external_type(uint64, primitive="yes");
  40 external_type(Time, primitive="yes", default="0");
  41 external_type(Address);
  42 structure(DataBlock, external = "yes", desc="..."){
  43   void clear();
  44   void copyPartial(DataBlock, int, int);
  45 }
  46
  47 // Declarations of external types that are common to all protocols
  48
  49 // AccessPermission
  50 // The following five states define the access permission of all memory blocks.
  51 // These permissions have multiple uses.  They coordinate locking and
  52 // synchronization primitives, as well as enable functional accesses.
  53 // One should not need to add any additional permission values and it is very
  54 // risky to do so.
  55 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  56   // Valid data
  57   Read_Only,  desc="block is Read Only (modulo functional writes)";
  58   Read_Write, desc="block is Read/Write";
  59
  60   // Invalid data
  61   Invalid,    desc="block is in an Invalid base state";
  62   NotPresent, desc="block is NotPresent";
  63   Busy,       desc="block is in a transient state, currently invalid";
  64 }
  65
  66 // TesterStatus
  67 enumeration(TesterStatus, desc="...") {
  68   Idle,            desc="Idle";
  69   Action_Pending,  desc="Action Pending";
  70   Ready,           desc="Ready";
  71   Check_Pending,   desc="Check Pending";
  72 }
  73
  74 // InvalidateGeneratorStatus
  75 enumeration(InvalidateGeneratorStatus, desc="...") {
  76   Load_Waiting,    desc="Load waiting to be issued";
  77   Load_Pending,    desc="Load issued";
  78   Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
  79   Inv_Pending,     desc="Store (invalidate) issued";
  80 }
  81
  82 // SeriesRequestGeneratorStatus
  83 enumeration(SeriesRequestGeneratorStatus, desc="...") {
  84   Thinking,        desc="Doing work before next action";
  85   Request_Pending, desc="Request pending";
  86 }
  87
  88 // LockStatus
  89 enumeration(LockStatus, desc="...") {
  90   Unlocked,        desc="Lock is not held";
  91   Locked,          desc="Lock is held";
  92 }
  93
  94 // SequencerStatus
  95 enumeration(SequencerStatus, desc="...") {
  96   Idle,            desc="Idle";
  97   Pending,         desc="Pending";
  98 }
  99
 100 enumeration(TransitionResult, desc="...") {
 101   Valid,         desc="Valid transition";
 102   ResourceStall, desc="Stalled due to insufficient resources";
 103   ProtocolStall, desc="Protocol specified stall";
 104 }
 105
 106 // RubyRequestType
 107 enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
 108   LD,                desc="Load";
 109   ST,                desc="Store";
 110   ATOMIC,            desc="Atomic Load/Store";
 111   IFETCH,            desc="Instruction fetch";
 112   IO,                desc="I/O";
 113   REPLACEMENT,       desc="Replacement";
 114   Load_Linked,       desc="";
 115   Store_Conditional, desc="";
 116   RMW_Read,          desc="";
 117   RMW_Write,         desc="";
 118   Locked_RMW_Read,   desc="";
 119   Locked_RMW_Write,  desc="";
 120   COMMIT,            desc="Commit version";
 121   NULL,              desc="Invalid request type";
 122   FLUSH,             desc="Flush request type";
 123 }
 124
 125 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
 126   LD,          desc="Load";
 127   ST,          desc="Store";
 128   NULL,        desc="Invalid request type";
 129 }
 130
 131 enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
 132   GETS,        desc="gets request";
 133   GET_INSTR,   desc="get instr request";
 134   GETX,        desc="getx request";
 135   UPGRADE,     desc="upgrade request";
 136   DOWNGRADE,   desc="downgrade request";
 137   INV,         desc="invalidate request";
 138   INV_S,       desc="invalidate shared copy request";
 139   PUTS,        desc="puts request";
 140   PUTO,        desc="puto request";
 141   PUTX,        desc="putx request";
 142   L2_PF,       desc="L2 prefetch";
 143   LD,          desc="Load";
 144   ST,          desc="Store";
 145   ATOMIC,      desc="Atomic Load/Store";
 146   IFETCH,      desc="Instruction fetch";
 147   IO,          desc="I/O";
 148   NACK,        desc="Nack";
 149   REPLACEMENT, desc="Replacement";
 150   WB_ACK,      desc="WriteBack ack";
 151   EXE_ACK,     desc="Execlusive ack";
 152   COMMIT,      desc="Commit version";
 153   LD_XACT,     desc="Transactional Load";
 154   LDX_XACT,     desc="Transactional Load-Intend-Modify";
 155   ST_XACT,     desc="Transactional Store";
 156   BEGIN_XACT,  desc="Begin Transaction";
 157   COMMIT_XACT, desc="Commit Transaction";
 158   ABORT_XACT,  desc="Abort Transaction";
 159   DMA_READ,    desc="DMA READ";
 160   DMA_WRITE,   desc="DMA WRITE";
 161   NULL,        desc="null request type";
 162 }
 163
 164 enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
 165   L1Cache,     desc="L1 Cache Mach";
 166   L2Cache,     desc="L2 Cache Mach";
 167   L3Cache,     desc="L3 Cache Mach";
 168   Directory,   desc="Directory Mach";
 169   Collector,   desc="Collector Mach";
 170   L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 171   L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 172   NULL,        desc="null mach type";
 173 }
 174
 175 // MessageSizeType
 176 enumeration(MessageSizeType, default="MessageSizeType_Undefined", desc="...") {
 177   Undefined,  desc="Undefined";
 178   Control,    desc="Control Message";
 179   Data,       desc="Data Message";
 180   Request_Control, desc="Request";
 181   Reissue_Control, desc="Reissued request";
 182   Response_Data, desc="data response";
 183   ResponseL2hit_Data, desc="data response";
 184   ResponseLocal_Data, desc="data response";
 185   Response_Control, desc="non-data response";
 186   Writeback_Data, desc="Writeback data";
 187   Writeback_Control, desc="Writeback control";
 188   Broadcast_Control, desc="Broadcast control";
 189   Multicast_Control, desc="Multicast control";
 190   Forwarded_Control, desc="Forwarded control";
 191   Invalidate_Control, desc="Invalidate control";
 192   Unblock_Control, desc="Unblock control";
 193   Persistent_Control, desc="Persistent request activation messages";
 194   Completion_Control, desc="Completion messages";
 195 }
 196
 197 // AccessType
 198 enumeration(AccessType, desc="...") {
 199   Read, desc="Reading from cache";
 200   Write, desc="Writing to cache";
 201 }
 202
 203 // RubyAccessMode
 204 enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
 205   Supervisor, desc="Supervisor mode";
 206   User,       desc="User mode";
 207   Device, desc="Device mode";
 208 }
 209
 210 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
 211   No,    desc="No, not a prefetch";
 212   Yes,   desc="Yes, a prefetch";
 213   L1_HW, desc="This is a L1 hardware prefetch";
 214   L2_HW, desc="This is a L2 hardware prefetch";
 215 }
 216
 217 // CacheMsg
 218 structure(SequencerMsg, desc="...", interface="Message") {
 219   Address LineAddress,       desc="Line address for this request";
 220   Address PhysicalAddress,   desc="Physical address for this request";
 221   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
 222   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 223   RubyAccessMode AccessMode, desc="user/supervisor access type";
 224   DataBlock DataBlk,         desc="Data";
 225   int Len,                   desc="size in bytes of access";
 226   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 227 }
 228
 229 // MaskPredictorType
 230 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
 231   Undefined, desc="Undefined";
 232   AlwaysUnicast, desc="AlwaysUnicast";
 233   TokenD, desc="TokenD";
 234   AlwaysBroadcast, desc="AlwaysBroadcast";
 235   TokenB, desc="TokenB";
 236   TokenNull, desc="TokenNull";
 237   Random, desc="Random";
 238   Pairwise, desc="Pairwise";
 239   Owner, desc="Owner";
 240   BroadcastIfShared, desc="Broadcast-If-Shared";
 241   BroadcastCounter, desc="Broadcast Counter";
 242   Group, desc="Group";
 243   Counter, desc="Counter";
 244   StickySpatial, desc="StickySpatial";
 245   OwnerBroadcast, desc="Owner/Broadcast Hybrid";
 246   OwnerGroup, desc="Owner/Group Hybrid";
 247   OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
 248   OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
 249   LastNMasks, desc="Last N Masks";
 250   BandwidthAdaptive, desc="Bandwidth Adaptive";
 251 }
 252
 253 // MaskPredictorIndex
 254 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
 255   Undefined, desc="Undefined";
 256   DataBlock, desc="Data Block";
 257   PC, desc="Program Counter";
 258 }
 259
 260 // MaskPredictorTraining
 261 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
 262   Undefined, desc="Undefined";
 263   None, desc="None";
 264   Implicit, desc="Implicit";
 265   Explicit, desc="Explicit";
 266   Both, desc="Both";
 267 }
 268
 269 // Network Topologies
 270 enumeration(TopologyType, desc="...") {
 271   CROSSBAR, desc="One node per chip, single switch crossbar";
 272   HIERARCHICAL_SWITCH, desc="One node per chip, totally ordered hierarchical tree switched network";
 273   TORUS_2D, desc="One node per chip, 2D torus";
 274   PT_TO_PT, desc="One node per chip, Point to Point Network";
 275   FILE_SPECIFIED, desc="described by the file NETWORK_FILE";
 276 }
 277
 278 // DNUCA AllocationStrategy
 279 enumeration(AllocationStrategy, desc="...") {
 280   InMiddle, desc="";
 281   InInvCorners, desc="";
 282   InSharedSides, desc="";
 283   StaticDist, desc="";
 284   RandomBank, desc="";
 285   FrequencyBank, desc="";
 286   FrequencyBlock, desc="";
 287   LRUBlock, desc="";
 288 }
 289
 290 // DNUCA SearchMechanism
 291 enumeration(SearchMechanism, desc="...") {
 292   Perfect, desc="";
 293   PartialTag, desc="";
 294   BloomFilter, desc="";
 295   Random, desc="";
 296   None, desc="";
 297 }
 298
 299 // DNUCA link type
 300 enumeration(LinkType, desc="...") {
 301   RC_1500UM, desc="";
 302   RC_2500UM, desc="";
 303   TL_9000UM, desc="";
 304   TL_11000UM, desc="";
 305   TL_13000UM, desc="";
 306   NO_ENERGY, desc="";
 307   NULL, desc="";
 308 }
 309
 310 // transient request type
 311 enumeration(TransientRequestType, desc="...", default="TransientRequestType_Undefined") {
 312   Undefined, desc="";
 313   OffChip, desc="";
 314   OnChip, desc="";
 315   LocalTransient, desc="";
 316 }
 317
 318 // Request Status
 319 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
 320   Ready, desc="The sequencer is ready and the request does not alias";
 321   Issued, desc="The sequencer successfully issued the request";
 322   BufferFull, desc="Can not issue because the sequencer is full";
 323   Aliased, desc="This request aliased with a currently outstanding request";
 324   NULL, desc="";
 325 }
 326
 327 // LinkDirection
 328 enumeration(LinkDirection, desc="...") {
 329   In, desc="Inward link direction";
 330   Out, desc="Outward link direction";
 331 }