src/mem/protocol/RubySlicc_Exports.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  *
  33  */
  34
  35 // defines
  36 external_type(int, primitive="yes", default="0");
  37 external_type(bool, primitive="yes", default="false");
  38 external_type(std::string, primitive="yes");
  39 external_type(uint64, primitive="yes");
  40 external_type(Time, primitive="yes", default="0");
  41 external_type(Address);
  42 structure(DataBlock, external = "yes", desc="..."){
  43   void clear();
  44   void copyPartial(DataBlock, int, int);
  45 }
  46
  47 // Declarations of external types that are common to all protocols
  48
  49 // AccessPermission
  50 // The following five states define the access permission of all memory blocks.
  51 // These permissions have multiple uses.  They coordinate locking and
  52 // synchronization primitives, as well as enable functional accesses.
  53 // One should not need to add any additional permission values and it is very
  54 // risky to do so.
  55 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  56   // Valid data
  57   Read_Only,  desc="block is Read Only (modulo functional writes)";
  58   Read_Write, desc="block is Read/Write";
  59
  60   // Possibly Invalid data
  61   // The maybe stale permission indicates that accordingly to the protocol,
  62   // there is no guarantee the block contains valid data.  However, functional
  63   // writes should update the block because a dataless PUT request may
  64   // revalidate the block's data.
  65   Maybe_Stale, desc="block can be stale or revalidated by a dataless PUT";
  66
  67   // Invalid data
  68   Invalid,    desc="block is in an Invalid base state";
  69   NotPresent, desc="block is NotPresent";
  70   Busy,       desc="block is in a transient state, currently invalid";
  71 }
  72
  73 // TesterStatus
  74 enumeration(TesterStatus, desc="...") {
  75   Idle,            desc="Idle";
  76   Action_Pending,  desc="Action Pending";
  77   Ready,           desc="Ready";
  78   Check_Pending,   desc="Check Pending";
  79 }
  80
  81 // InvalidateGeneratorStatus
  82 enumeration(InvalidateGeneratorStatus, desc="...") {
  83   Load_Waiting,    desc="Load waiting to be issued";
  84   Load_Pending,    desc="Load issued";
  85   Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
  86   Inv_Pending,     desc="Store (invalidate) issued";
  87 }
  88
  89 // SeriesRequestGeneratorStatus
  90 enumeration(SeriesRequestGeneratorStatus, desc="...") {
  91   Thinking,        desc="Doing work before next action";
  92   Request_Pending, desc="Request pending";
  93 }
  94
  95 // LockStatus
  96 enumeration(LockStatus, desc="...") {
  97   Unlocked,        desc="Lock is not held";
  98   Locked,          desc="Lock is held";
  99 }
 100
 101 // SequencerStatus
 102 enumeration(SequencerStatus, desc="...") {
 103   Idle,            desc="Idle";
 104   Pending,         desc="Pending";
 105 }
 106
 107 enumeration(TransitionResult, desc="...") {
 108   Valid,         desc="Valid transition";
 109   ResourceStall, desc="Stalled due to insufficient resources";
 110   ProtocolStall, desc="Protocol specified stall";
 111 }
 112
 113 // RubyRequestType
 114 enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
 115   LD,                desc="Load";
 116   ST,                desc="Store";
 117   ATOMIC,            desc="Atomic Load/Store";
 118   IFETCH,            desc="Instruction fetch";
 119   IO,                desc="I/O";
 120   REPLACEMENT,       desc="Replacement";
 121   Load_Linked,       desc="";
 122   Store_Conditional, desc="";
 123   RMW_Read,          desc="";
 124   RMW_Write,         desc="";
 125   Locked_RMW_Read,   desc="";
 126   Locked_RMW_Write,  desc="";
 127   COMMIT,            desc="Commit version";
 128   NULL,              desc="Invalid request type";
 129   FLUSH,             desc="Flush request type";
 130 }
 131
 132 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
 133   LD,          desc="Load";
 134   ST,          desc="Store";
 135   NULL,        desc="Invalid request type";
 136 }
 137
 138 enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") {
 139   GETS,        desc="gets request";
 140   GET_INSTR,   desc="get instr request";
 141   GETX,        desc="getx request";
 142   UPGRADE,     desc="upgrade request";
 143   DOWNGRADE,   desc="downgrade request";
 144   INV,         desc="invalidate request";
 145   INV_S,       desc="invalidate shared copy request";
 146   PUTS,        desc="puts request";
 147   PUTO,        desc="puto request";
 148   PUTX,        desc="putx request";
 149   L2_PF,       desc="L2 prefetch";
 150   LD,          desc="Load";
 151   ST,          desc="Store";
 152   ATOMIC,      desc="Atomic Load/Store";
 153   IFETCH,      desc="Instruction fetch";
 154   IO,          desc="I/O";
 155   NACK,        desc="Nack";
 156   REPLACEMENT, desc="Replacement";
 157   WB_ACK,      desc="WriteBack ack";
 158   EXE_ACK,     desc="Execlusive ack";
 159   COMMIT,      desc="Commit version";
 160   LD_XACT,     desc="Transactional Load";
 161   LDX_XACT,     desc="Transactional Load-Intend-Modify";
 162   ST_XACT,     desc="Transactional Store";
 163   BEGIN_XACT,  desc="Begin Transaction";
 164   COMMIT_XACT, desc="Commit Transaction";
 165   ABORT_XACT,  desc="Abort Transaction";
 166   DMA_READ,    desc="DMA READ";
 167   DMA_WRITE,   desc="DMA WRITE";
 168   NULL,        desc="null request type";
 169 }
 170
 171 enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") {
 172   L1Cache,     desc="L1 Cache Mach";
 173   L2Cache,     desc="L2 Cache Mach";
 174   L3Cache,     desc="L3 Cache Mach";
 175   Directory,   desc="Directory Mach";
 176   Collector,   desc="Collector Mach";
 177   L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 178   L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)";
 179   NULL,        desc="null mach type";
 180 }
 181
 182 // MessageSizeType
 183 enumeration(MessageSizeType, default="MessageSizeType_Undefined", desc="...") {
 184   Undefined,  desc="Undefined";
 185   Control,    desc="Control Message";
 186   Data,       desc="Data Message";
 187   Request_Control, desc="Request";
 188   Reissue_Control, desc="Reissued request";
 189   Response_Data, desc="data response";
 190   ResponseL2hit_Data, desc="data response";
 191   ResponseLocal_Data, desc="data response";
 192   Response_Control, desc="non-data response";
 193   Writeback_Data, desc="Writeback data";
 194   Writeback_Control, desc="Writeback control";
 195   Broadcast_Control, desc="Broadcast control";
 196   Multicast_Control, desc="Multicast control";
 197   Forwarded_Control, desc="Forwarded control";
 198   Invalidate_Control, desc="Invalidate control";
 199   Unblock_Control, desc="Unblock control";
 200   Persistent_Control, desc="Persistent request activation messages";
 201   Completion_Control, desc="Completion messages";
 202 }
 203
 204 // AccessType
 205 enumeration(AccessType, desc="...") {
 206   Read, desc="Reading from cache";
 207   Write, desc="Writing to cache";
 208 }
 209
 210 // RubyAccessMode
 211 enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
 212   Supervisor, desc="Supervisor mode";
 213   User,       desc="User mode";
 214   Device, desc="Device mode";
 215 }
 216
 217 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
 218   No,    desc="No, not a prefetch";
 219   Yes,   desc="Yes, a prefetch";
 220   L1_HW, desc="This is a L1 hardware prefetch";
 221   L2_HW, desc="This is a L2 hardware prefetch";
 222 }
 223
 224 // CacheMsg
 225 structure(SequencerMsg, desc="...", interface="Message") {
 226   Address LineAddress,       desc="Line address for this request";
 227   Address PhysicalAddress,   desc="Physical address for this request";
 228   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
 229   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 230   RubyAccessMode AccessMode, desc="user/supervisor access type";
 231   DataBlock DataBlk,         desc="Data";
 232   int Len,                   desc="size in bytes of access";
 233   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 234 }
 235
 236 // MaskPredictorType
 237 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
 238   Undefined, desc="Undefined";
 239   AlwaysUnicast, desc="AlwaysUnicast";
 240   TokenD, desc="TokenD";
 241   AlwaysBroadcast, desc="AlwaysBroadcast";
 242   TokenB, desc="TokenB";
 243   TokenNull, desc="TokenNull";
 244   Random, desc="Random";
 245   Pairwise, desc="Pairwise";
 246   Owner, desc="Owner";
 247   BroadcastIfShared, desc="Broadcast-If-Shared";
 248   BroadcastCounter, desc="Broadcast Counter";
 249   Group, desc="Group";
 250   Counter, desc="Counter";
 251   StickySpatial, desc="StickySpatial";
 252   OwnerBroadcast, desc="Owner/Broadcast Hybrid";
 253   OwnerGroup, desc="Owner/Group Hybrid";
 254   OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
 255   OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
 256   LastNMasks, desc="Last N Masks";
 257   BandwidthAdaptive, desc="Bandwidth Adaptive";
 258 }
 259
 260 // MaskPredictorIndex
 261 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
 262   Undefined, desc="Undefined";
 263   DataBlock, desc="Data Block";
 264   PC, desc="Program Counter";
 265 }
 266
 267 // MaskPredictorTraining
 268 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
 269   Undefined, desc="Undefined";
 270   None, desc="None";
 271   Implicit, desc="Implicit";
 272   Explicit, desc="Explicit";
 273   Both, desc="Both";
 274 }
 275
 276 // Network Topologies
 277 enumeration(TopologyType, desc="...") {
 278   CROSSBAR, desc="One node per chip, single switch crossbar";
 279   HIERARCHICAL_SWITCH, desc="One node per chip, totally ordered hierarchical tree switched network";
 280   TORUS_2D, desc="One node per chip, 2D torus";
 281   PT_TO_PT, desc="One node per chip, Point to Point Network";
 282   FILE_SPECIFIED, desc="described by the file NETWORK_FILE";
 283 }
 284
 285 // DNUCA AllocationStrategy
 286 enumeration(AllocationStrategy, desc="...") {
 287   InMiddle, desc="";
 288   InInvCorners, desc="";
 289   InSharedSides, desc="";
 290   StaticDist, desc="";
 291   RandomBank, desc="";
 292   FrequencyBank, desc="";
 293   FrequencyBlock, desc="";
 294   LRUBlock, desc="";
 295 }
 296
 297 // DNUCA SearchMechanism
 298 enumeration(SearchMechanism, desc="...") {
 299   Perfect, desc="";
 300   PartialTag, desc="";
 301   BloomFilter, desc="";
 302   Random, desc="";
 303   None, desc="";
 304 }
 305
 306 // DNUCA link type
 307 enumeration(LinkType, desc="...") {
 308   RC_1500UM, desc="";
 309   RC_2500UM, desc="";
 310   TL_9000UM, desc="";
 311   TL_11000UM, desc="";
 312   TL_13000UM, desc="";
 313   NO_ENERGY, desc="";
 314   NULL, desc="";
 315 }
 316
 317 // transient request type
 318 enumeration(TransientRequestType, desc="...", default="TransientRequestType_Undefined") {
 319   Undefined, desc="";
 320   OffChip, desc="";
 321   OnChip, desc="";
 322   LocalTransient, desc="";
 323 }
 324
 325 // Request Status
 326 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
 327   Ready, desc="The sequencer is ready and the request does not alias";
 328   Issued, desc="The sequencer successfully issued the request";
 329   BufferFull, desc="Can not issue because the sequencer is full";
 330   Aliased, desc="This request aliased with a currently outstanding request";
 331   NULL, desc="";
 332 }
 333
 334 // LinkDirection
 335 enumeration(LinkDirection, desc="...") {
 336   In, desc="Inward link direction";
 337   Out, desc="Outward link direction";
 338 }