src/mem/protocol/RubySlicc_Types.sm

   1 /*
   2  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 // External Types
  31
  32 //
  33 // **PLEASE NOTE!**  When adding objects to this file you must also add a line
  34 // in the src/mem/ruby/SConscript file.  Otherwise the external object's .hh
  35 // file will not be copied to the protocol directory and you will encounter a
  36 // undefined declaration error.
  37 //
  38
  39 external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
  40 external_type(OutPort, primitive="yes");
  41 external_type(Scalar, primitive="yes");
  42
  43 structure(InPort, external = "yes", primitive="yes") {
  44   bool isReady(Tick current_time);
  45   Tick dequeue(Tick current_time);
  46   void recycle(Tick current_time, Tick recycle_latency);
  47   bool isEmpty();
  48   bool isStallMapEmpty();
  49   int getStallMapSize();
  50 }
  51
  52 external_type(NodeID, default="0", primitive="yes");
  53 external_type(MachineID);
  54
  55 structure (Set, external = "yes", non_obj="yes") {
  56   void setSize(int);
  57   void add(NodeID);
  58   void addSet(Set);
  59   void remove(NodeID);
  60   void removeSet(Set);
  61   void broadcast();
  62   void addRandom();
  63   void clear();
  64   int count();
  65   bool isElement(NodeID);
  66   bool isEqual(Set);
  67   bool isSuperset(Set);
  68   bool intersectionIsEmpty(Set);
  69   NodeID smallestElement();
  70 }
  71
  72 structure (NetDest, external = "yes", non_obj="yes") {
  73   void setSize(int);
  74   void setSize(int, int);
  75   void add(NodeID);
  76   void add(MachineID);
  77   void addSet(Set);
  78   void addNetDest(NetDest);
  79   void setNetDest(MachineType, Set);
  80   void remove(NodeID);
  81   void remove(MachineID);
  82   void removeSet(Set);
  83   void removeNetDest(NetDest);
  84   void broadcast();
  85   void broadcast(MachineType);
  86   void addRandom();
  87   void clear();
  88   Set toSet();
  89   int count();
  90   bool isElement(NodeID);
  91   bool isElement(MachineID);
  92   bool isSuperset(Set);
  93   bool isSuperset(NetDest);
  94   bool isEmpty();
  95   bool intersectionIsEmpty(Set);
  96   bool intersectionIsEmpty(NetDest);
  97   MachineID smallestElement(MachineType);
  98 }
  99
 100 structure (Sequencer, external = "yes") {
 101   void readCallback(Addr, DataBlock);
 102   void readCallback(Addr, DataBlock, bool);
 103   void readCallback(Addr, DataBlock, bool, MachineType);
 104   void readCallback(Addr, DataBlock, bool, MachineType,
 105                     Cycles, Cycles, Cycles);
 106
 107   void writeCallback(Addr, DataBlock);
 108   void writeCallback(Addr, DataBlock, bool);
 109   void writeCallback(Addr, DataBlock, bool, MachineType);
 110   void writeCallback(Addr, DataBlock, bool, MachineType,
 111                      Cycles, Cycles, Cycles);
 112
 113   void checkCoherence(Addr);
 114   void evictionCallback(Addr);
 115   void recordRequestType(SequencerRequestType);
 116   bool checkResourceAvailable(CacheResourceType, Addr);
 117   void invalidateSC(Addr);
 118 }
 119
 120 structure(RubyRequest, desc="...", interface="Message", external="yes") {
 121   Addr LineAddress,       desc="Line address for this request";
 122   Addr PhysicalAddress,   desc="Physical address for this request";
 123   RubyRequestType Type,      desc="Type of request (LD, ST, etc)";
 124   Addr ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 125   RubyAccessMode AccessMode, desc="user/supervisor access type";
 126   int Size,                  desc="size in bytes of access";
 127   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 128   int contextId,             desc="this goes away but must be replace with Nilay";
 129 }
 130
 131 structure(AbstractEntry, primitive="yes", external = "yes") {
 132   void changePermission(AccessPermission);
 133 }
 134
 135 structure (DirectoryMemory, external = "yes") {
 136   AbstractEntry allocate(Addr, AbstractEntry);
 137   AbstractEntry lookup(Addr);
 138   bool isPresent(Addr);
 139   void invalidateBlock(Addr);
 140   void recordRequestType(DirectoryRequestType);
 141 }
 142
 143 structure(AbstractCacheEntry, primitive="yes", external = "yes") {
 144   void changePermission(AccessPermission);
 145 }
 146
 147 structure (CacheMemory, external = "yes") {
 148   bool cacheAvail(Addr);
 149   Addr cacheProbe(Addr);
 150   AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
 151   AbstractCacheEntry allocate(Addr, AbstractCacheEntry, bool);
 152   void allocateVoid(Addr, AbstractCacheEntry);
 153   void deallocate(Addr);
 154   AbstractCacheEntry lookup(Addr);
 155   bool isTagPresent(Addr);
 156   Cycles getTagLatency();
 157   Cycles getDataLatency();
 158   void setMRU(Addr);
 159   void setMRU(AbstractCacheEntry);
 160   void recordRequestType(CacheRequestType, Addr);
 161   bool checkResourceAvailable(CacheResourceType, Addr);
 162
 163   int getCacheSize();
 164   int getNumBlocks();
 165   Addr getAddressAtIdx(int);
 166
 167   Scalar demand_misses;
 168   Scalar demand_hits;
 169 }
 170
 171 structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
 172
 173 }
 174
 175 structure (DMASequencer, external = "yes") {
 176   void ackCallback();
 177   void dataCallback(DataBlock);
 178   void recordRequestType(CacheRequestType);
 179 }
 180
 181 structure (TimerTable, inport="yes", external = "yes") {
 182   bool isReady(Tick);
 183   Addr nextAddress();
 184   void set(Addr, Tick);
 185   void unset(Addr);
 186   bool isSet(Addr);
 187 }
 188
 189 structure (AbstractBloomFilter, external = "yes") {
 190   void clear(int);
 191   void increment(Addr, int);
 192   void decrement(Addr, int);
 193   void set(Addr, int);
 194   void unset(Addr, int);
 195
 196   bool isSet(Addr, int);
 197   int getCount(Addr, int);
 198 }
 199
 200 structure (Prefetcher, external = "yes") {
 201     void observeMiss(Addr, RubyRequestType);
 202     void observePfHit(Addr);
 203     void observePfMiss(Addr);
 204 }