x86: changes to apic, keyboard
[gem5.git] / src / mem / protocol / RubySlicc_Types.sm
1 /*
2 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 // External Types
30
31 //
32 // **PLEASE NOTE!** When adding objects to this file you must also add a line
33 // in the src/mem/ruby/SConscript file. Otherwise the external object's .hh
34 // file will not be copied to the protocol directory and you will encounter a
35 // undefined declaration error.
36 //
37
38 external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
39 external_type(OutPort, primitive="yes");
40
41 structure(InPort, external = "yes", primitive="yes") {
42 bool isReady();
43 void dequeue();
44 Cycles dequeue_getDelayCycles();
45 void recycle();
46 bool isEmpty();
47 }
48
49 external_type(NodeID, default="0", primitive="yes");
50 external_type(MachineID);
51
52 structure (Set, external = "yes", non_obj="yes") {
53 void setSize(int);
54 void add(NodeID);
55 void addSet(Set);
56 void remove(NodeID);
57 void removeSet(Set);
58 void broadcast();
59 void addRandom();
60 void clear();
61 int count();
62 bool isElement(NodeID);
63 bool isEqual(Set);
64 bool isSuperset(Set);
65 bool intersectionIsEmpty(Set);
66 NodeID smallestElement();
67 }
68
69 structure (NetDest, external = "yes", non_obj="yes") {
70 void setSize(int);
71 void setSize(int, int);
72 void add(NodeID);
73 void add(MachineID);
74 void addSet(Set);
75 void addNetDest(NetDest);
76 void setNetDest(MachineType, Set);
77 void remove(NodeID);
78 void remove(MachineID);
79 void removeSet(Set);
80 void removeNetDest(NetDest);
81 void broadcast();
82 void broadcast(MachineType);
83 void addRandom();
84 void clear();
85 Set toSet();
86 int count();
87 bool isElement(NodeID);
88 bool isElement(MachineID);
89 bool isSuperset(Set);
90 bool isSuperset(NetDest);
91 bool isEmpty();
92 bool intersectionIsEmpty(Set);
93 bool intersectionIsEmpty(NetDest);
94 MachineID smallestElement(MachineType);
95 }
96
97 structure (Sequencer, external = "yes") {
98 void readCallback(Address, DataBlock);
99 void readCallback(Address, GenericMachineType, DataBlock);
100 void readCallback(Address, GenericMachineType, DataBlock,
101 Cycles, Cycles, Cycles);
102
103 void writeCallback(Address, DataBlock);
104 void writeCallback(Address, GenericMachineType, DataBlock);
105 void writeCallback(Address, GenericMachineType, DataBlock,
106 Cycles, Cycles, Cycles);
107
108 void checkCoherence(Address);
109 void profileNack(Address, int, int, uint64);
110 void evictionCallback(Address);
111 void recordRequestType(SequencerRequestType);
112 bool checkResourceAvailable(CacheResourceType, Address);
113 void invalidateSC(Address);
114 }
115
116 structure(RubyRequest, desc="...", interface="Message", external="yes") {
117 Address LineAddress, desc="Line address for this request";
118 Address PhysicalAddress, desc="Physical address for this request";
119 RubyRequestType Type, desc="Type of request (LD, ST, etc)";
120 Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
121 RubyAccessMode AccessMode, desc="user/supervisor access type";
122 int Size, desc="size in bytes of access";
123 PrefetchBit Prefetch, desc="Is this a prefetch request";
124 int contextId, desc="this goes away but must be replace with Nilay";
125 }
126
127 structure(AbstractEntry, primitive="yes", external = "yes") {
128 void changePermission(AccessPermission);
129 }
130
131 structure (DirectoryMemory, external = "yes") {
132 AbstractEntry allocate(Address, AbstractEntry);
133 AbstractEntry lookup(Address);
134 bool isPresent(Address);
135 void invalidateBlock(Address);
136 void recordRequestType(DirectoryRequestType);
137 }
138
139 structure(AbstractCacheEntry, primitive="yes", external = "yes") {
140 void changePermission(AccessPermission);
141 }
142
143 structure (CacheMemory, external = "yes") {
144 bool cacheAvail(Address);
145 Address cacheProbe(Address);
146 AbstractCacheEntry allocate(Address, AbstractCacheEntry);
147 void allocateVoid(Address, AbstractCacheEntry);
148 void deallocate(Address);
149 AbstractCacheEntry lookup(Address);
150 bool isTagPresent(Address);
151 void profileMiss(RubyRequest);
152
153 void profileGenericRequest(GenericRequestType,
154 RubyAccessMode,
155 PrefetchBit);
156
157 void setMRU(Address);
158 void recordRequestType(CacheRequestType);
159 bool checkResourceAvailable(CacheResourceType, Address);
160 }
161
162 structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
163
164 }
165
166 structure (MemoryControl, inport="yes", outport="yes", external = "yes") {
167 void recordRequestType(CacheRequestType);
168 }
169
170 structure (DMASequencer, external = "yes") {
171 void ackCallback();
172 void dataCallback(DataBlock);
173 void recordRequestType(CacheRequestType);
174 }
175
176 structure (TimerTable, inport="yes", external = "yes") {
177 bool isReady();
178 Address readyAddress();
179 void set(Address, Cycles);
180 void unset(Address);
181 bool isSet(Address);
182 }
183
184 structure (GenericBloomFilter, external = "yes") {
185 void clear(int);
186 void increment(Address, int);
187 void decrement(Address, int);
188 void set(Address, int);
189 void unset(Address, int);
190
191 bool isSet(Address, int);
192 int getCount(Address, int);
193 }
194
195 structure (Prefetcher, external = "yes") {
196 void observeMiss(Address, RubyRequestType);
197 void observePfHit(Address);
198 void observePfMiss(Address);
199 }