1 # Copyright (c) 2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
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7 # to a hardware implementation of the functionality of the software
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22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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36 # Author: Matteo Andreozzi
38 from m5
.params
import *
39 from m5
.objects
.QoSMemCtrl
import *
41 class QoSMemSinkCtrl(QoSMemCtrl
):
42 type = 'QoSMemSinkCtrl'
43 cxx_header
= "mem/qos/mem_sink.hh"
44 cxx_class
= "QoS::MemSinkCtrl"
45 port
= SlavePort("Slave ports")
47 # the basic configuration of the controller architecture, note
48 # that each entry corresponds to a burst for the specific DRAM
49 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
50 # the cacheline size or request/packet size
51 write_buffer_size
= Param
.Unsigned(64, "Number of write queue entries")
52 read_buffer_size
= Param
.Unsigned(32, "Number of read queue entries")
55 memory_packet_size
= Param
.MemorySize("32B", "Memory packet size")
57 # request latency - minimum timing between requests
58 request_latency
= Param
.Latency("20ns", "Memory latency between requests")
60 # response latency - time to issue a response once a request is serviced
61 response_latency
= Param
.Latency("20ns", "Memory response latency")