src/mem/qos/QoSMemSinkCtrl.py

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  36 # Author: Matteo Andreozzi
  37
  38 from m5.params import *
  39 from m5.objects.QoSMemCtrl import *
  40 from m5.objects.QoSMemSinkInterface import *
  41
  42 class QoSMemSinkCtrl(QoSMemCtrl):
  43     type = 'QoSMemSinkCtrl'
  44     cxx_header = "mem/qos/mem_sink.hh"
  45     cxx_class = "QoS::MemSinkCtrl"
  46     port = ResponsePort("Response ports")
  47
  48
  49     interface = Param.QoSMemSinkInterface(QoSMemSinkInterface(),
  50                 "Interface to memory")
  51
  52     # the basic configuration of the controller architecture, note
  53     # that each entry corresponds to a burst for the specific DRAM
  54     # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
  55     # the cacheline size or request/packet size
  56     write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
  57     read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
  58
  59     # memory packet size
  60     memory_packet_size = Param.MemorySize("32B", "Memory packet size")
  61
  62     # request latency - minimum timing between requests
  63     request_latency = Param.Latency("20ns", "Memory latency between requests")
  64
  65     # response latency - time to issue a response once a request is serviced
  66     response_latency = Param.Latency("20ns", "Memory response latency")