src/mem/qos/mem_sink.hh

   1 /*
   2  * Copyright (c) 2018-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
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  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Author: Matteo Andreozzi
  38  */
  39
  40
  41 #ifndef __MEM_QOS_MEM_SINK_HH__
  42 #define __MEM_QOS_MEM_SINK_HH__
  43
  44 #include "mem/abstract_mem.hh"
  45 #include "mem/qos/mem_ctrl.hh"
  46 #include "mem/qport.hh"
  47 #include "params/QoSMemSinkCtrl.hh"
  48
  49 class QoSMemSinkInterfaceParams;
  50 class QoSMemSinkInterface;
  51
  52 namespace QoS {
  53
  54 /**
  55  * QoS Memory Sink
  56  *
  57  * The QoS Memory Sink is a lightweight memory controller with QoS
  58  * support. It is meant to provide a QoS aware simple memory system
  59  * without the need of using a complex DRAM memory controller
  60  */
  61 class MemSinkCtrl : public MemCtrl
  62 {
  63   protected:
  64     /**
  65      * The Request packets are store in a multiple dequeue structure,
  66      * based on their QoS priority
  67      */
  68     using PacketQueue = std::deque<PacketPtr>;
  69
  70   private:
  71     class MemoryPort : public QueuedSlavePort
  72     {
  73       private:
  74         /** reference to parent memory object */
  75         MemSinkCtrl& memory;
  76
  77         /** Outgoing packet responses queue */
  78         RespPacketQueue queue;
  79
  80       public:
  81        /**
  82         * Constructor
  83         *
  84         * @param n port name
  85         * @param m reference to ProfileGen parent object
  86         */
  87         MemoryPort(const std::string&, MemSinkCtrl&);
  88
  89       protected:
  90        /**
  91         * Receive a Packet in Atomic mode
  92         *
  93         * @param pkt pointer to memory packet
  94         * @return packet access latency in ticks
  95         */
  96         Tick recvAtomic(PacketPtr pkt);
  97
  98         /**
  99         * Receive a Packet in Functional mode
 100         *
 101         * @param pkt pointer to memory packet
 102         */
 103         void recvFunctional(PacketPtr pkt);
 104
 105         /**
 106         * Receive a Packet in Timing mode
 107         *
 108         * @param pkt pointer to memory packet
 109         * @return true if the request was accepted
 110         */
 111         bool recvTimingReq(PacketPtr pkt);
 112
 113         /**
 114          * Gets the configured address ranges for this port
 115          * @return the configured address ranges for this port
 116          */
 117         AddrRangeList getAddrRanges() const;
 118
 119     };
 120
 121   public:
 122     /**
 123      * QoS Memory Sink Constructor
 124      *
 125      * @param p QoS Memory Sink configuration parameters
 126      */
 127     MemSinkCtrl(const QoSMemSinkCtrlParams*);
 128
 129     virtual ~MemSinkCtrl();
 130
 131     /**
 132      * Checks and return the Drain state of this SimObject
 133      * @return current Drain state
 134      */
 135     DrainState drain() override;
 136
 137     /**
 138      * Getter method to access this memory's slave port
 139      *
 140      * @param if_name interface name
 141      * @param idx port ID number
 142      * @return reference to this memory's slave port
 143      */
 144     Port &getPort(const std::string &if_name, PortID=InvalidPortID) override;
 145
 146     /**
 147      * Initializes this object
 148      */
 149     void init() override;
 150
 151   protected:
 152     /** Memory between requests latency (ticks) */
 153     const Tick requestLatency;
 154
 155     /** Memory response latency (ticks) */
 156     const Tick responseLatency;
 157
 158     /** Memory packet size in bytes */
 159     const uint64_t memoryPacketSize;
 160
 161     /** Read request packets queue buffer size in #packets */
 162     const uint64_t readBufferSize;
 163
 164     /** Write request packets queue buffer size in #packets */
 165     const uint64_t writeBufferSize;
 166
 167     /** Memory slave port */
 168     MemoryPort port;
 169
 170     /**
 171      * Create pointer to interface of actual media
 172      */
 173     QoSMemSinkInterface* const interface;
 174
 175     /** Read request pending */
 176     bool retryRdReq;
 177
 178     /** Write request pending */
 179     bool retryWrReq;
 180
 181     /** Next request service time */
 182     Tick nextRequest;
 183
 184     /** Count the number of read retries */
 185     Stats::Scalar numReadRetries;
 186
 187     /** Count the number of write retries */
 188     Stats::Scalar numWriteRetries;
 189
 190     /**
 191      * QoS-aware (per priority) incoming read requests packets queue
 192      */
 193     std::vector<PacketQueue> readQueue;
 194
 195     /**
 196      * QoS-aware (per priority) incoming read requests packets queue
 197      */
 198     std::vector<PacketQueue> writeQueue;
 199
 200     /**
 201      * Processes the next Request event according to configured
 202      * request latency
 203      */
 204     void processNextReqEvent();
 205
 206     /** Event wrapper to schedule next request handler function */
 207     EventWrapper<
 208         MemSinkCtrl,
 209         &MemSinkCtrl::processNextReqEvent> nextReqEvent;
 210
 211     /**
 212      * Check if the read queue has room for more entries
 213      *
 214      * @param packets The number of entries needed in the read queue
 215      * @return true if read queue is full, false otherwise
 216      */
 217     inline bool readQueueFull(const uint64_t packets) const;
 218
 219     /**
 220      * Check if the write queue has room for more entries
 221      *
 222      * @param packets  The number of entries needed in the write queue
 223      * @return true if write queue is full, false otherwise
 224      */
 225     inline bool writeQueueFull(const uint64_t packets) const;
 226
 227     /**
 228      * Receive a Packet in Atomic mode
 229      *
 230      * @param pkt pointer to memory packet
 231      * @return packet access latency in ticks
 232      */
 233     Tick recvAtomic(PacketPtr pkt);
 234
 235     /**
 236      * Receive a Packet in Functional mode
 237      *
 238      * @param pkt pointer to memory packet
 239      */
 240     void recvFunctional(PacketPtr pkt);
 241
 242    /**
 243     * Receive a Packet in Timing mode
 244     *
 245     * @param pkt pointer to memory packet
 246     * @return true if the request was accepted
 247     */
 248     bool recvTimingReq(PacketPtr pkt);
 249
 250     /** Registers statistics */
 251     void regStats() override;
 252 };
 253
 254 } // namespace QoS
 255
 256 class QoSMemSinkInterface : public AbstractMemory
 257 {
 258   public:
 259     /** Setting a pointer to the interface */
 260     void setMemCtrl(QoS::MemSinkCtrl* _ctrl) { ctrl = _ctrl; };
 261
 262     /** Pointer to the controller */
 263     QoS::MemSinkCtrl* ctrl;
 264
 265     QoSMemSinkInterface(const QoSMemSinkInterfaceParams* _p);
 266 };
 267
 268
 269 #endif /* __MEM_QOS_MEM_SINK_HH__ */