misc: Replaced master/slave terminology
[gem5.git] / src / mem / qport.hh
1 /*
2 * Copyright (c) 2012,2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef __MEM_QPORT_HH__
39 #define __MEM_QPORT_HH__
40
41 /**
42 * @file
43 * Declaration of the queued port.
44 */
45
46 #include "mem/packet_queue.hh"
47 #include "mem/port.hh"
48 #include "sim/sim_object.hh"
49
50 /**
51 * A queued port is a port that has an infinite queue for outgoing
52 * packets and thus decouples the module that wants to send
53 * request/responses from the flow control (retry mechanism) of the
54 * port. A queued port can be used by both a requestor and a responder. The
55 * queue is a parameter to allow tailoring of the queue implementation
56 * (used in the cache).
57 */
58 class QueuedResponsePort : public ResponsePort
59 {
60
61 protected:
62
63 /** Packet queue used to store outgoing responses. */
64 RespPacketQueue &respQueue;
65
66 void recvRespRetry() { respQueue.retry(); }
67
68 public:
69
70 /**
71 * Create a QueuedPort with a given name, owner, and a supplied
72 * implementation of a packet queue. The external definition of
73 * the queue enables e.g. the cache to implement a specific queue
74 * behaviuor in a subclass, and provide the latter to the
75 * QueuePort constructor.
76 */
77 QueuedResponsePort(const std::string& name, SimObject* owner,
78 RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
79 ResponsePort(name, owner, id), respQueue(resp_queue)
80 { }
81
82 virtual ~QueuedResponsePort() { }
83
84 /**
85 * Schedule the sending of a timing response.
86 *
87 * @param pkt Packet to send
88 * @param when Absolute time (in ticks) to send packet
89 */
90 void schedTimingResp(PacketPtr pkt, Tick when)
91 { respQueue.schedSendTiming(pkt, when); }
92
93 /** Check the list of buffered packets against the supplied
94 * functional request. */
95 bool trySatisfyFunctional(PacketPtr pkt)
96 { return respQueue.trySatisfyFunctional(pkt); }
97 };
98
99 /**
100 * The QueuedRequestPort combines two queues, a request queue and a
101 * snoop response queue, that both share the same port. The flow
102 * control for requests and snoop responses are completely
103 * independent, and so each queue manages its own flow control
104 * (retries).
105 */
106 class QueuedRequestPort : public RequestPort
107 {
108
109 protected:
110
111 /** Packet queue used to store outgoing requests. */
112 ReqPacketQueue &reqQueue;
113
114 /** Packet queue used to store outgoing snoop responses. */
115 SnoopRespPacketQueue &snoopRespQueue;
116
117 void recvReqRetry() { reqQueue.retry(); }
118
119 void recvRetrySnoopResp() { snoopRespQueue.retry(); }
120
121 public:
122
123 /**
124 * Create a QueuedPort with a given name, owner, and a supplied
125 * implementation of two packet queues. The external definition of
126 * the queues enables e.g. the cache to implement a specific queue
127 * behaviuor in a subclass, and provide the latter to the
128 * QueuePort constructor.
129 */
130 QueuedRequestPort(const std::string& name, SimObject* owner,
131 ReqPacketQueue &req_queue,
132 SnoopRespPacketQueue &snoop_resp_queue,
133 PortID id = InvalidPortID) :
134 RequestPort(name, owner, id), reqQueue(req_queue),
135 snoopRespQueue(snoop_resp_queue)
136 { }
137
138 virtual ~QueuedRequestPort() { }
139
140 /**
141 * Schedule the sending of a timing request.
142 *
143 * @param pkt Packet to send
144 * @param when Absolute time (in ticks) to send packet
145 */
146 void schedTimingReq(PacketPtr pkt, Tick when)
147 { reqQueue.schedSendTiming(pkt, when); }
148
149 /**
150 * Schedule the sending of a timing snoop response.
151 *
152 * @param pkt Packet to send
153 * @param when Absolute time (in ticks) to send packet
154 */
155 void schedTimingSnoopResp(PacketPtr pkt, Tick when)
156 { snoopRespQueue.schedSendTiming(pkt, when); }
157
158 /** Check the list of buffered packets against the supplied
159 * functional request. */
160 bool trySatisfyFunctional(PacketPtr pkt)
161 {
162 return reqQueue.trySatisfyFunctional(pkt) ||
163 snoopRespQueue.trySatisfyFunctional(pkt);
164 }
165 };
166
167 #endif // __MEM_QPORT_HH__