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41 * Authors: Ron Dreslinski
48 * Declaration of a request, the overall memory request consisting of
49 the parts of the request that are persistent throughout the transaction.
52 #ifndef __MEM_REQUEST_HH__
53 #define __MEM_REQUEST_HH__
58 #include "base/flags.hh"
59 #include "base/logging.hh"
60 #include "base/types.hh"
61 #include "cpu/inst_seq.hh"
62 #include "sim/core.hh"
65 * Special TaskIds that are used for per-context-switch stats dumps
66 * and Cache Occupancy. Having too many tasks seems to be a problem
67 * with vector stats. 1024 seems to be a reasonable number that
68 * doesn't cause a problem with stats and is large enough to realistic
69 * benchmarks (Linux/Android boot, BBench, etc.)
72 namespace ContextSwitchTaskId {
74 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
75 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
76 DMA = 1023, /* Mostly Table Walker */
84 typedef std::shared_ptr<Request> RequestPtr;
85 typedef uint16_t MasterID;
90 typedef uint64_t FlagsType;
91 typedef uint8_t ArchFlagsType;
92 typedef ::Flags<FlagsType> Flags;
96 * Architecture specific flags.
98 * These bits int the flag field are reserved for
99 * architecture-specific code. For example, SPARC uses them to
102 ARCH_BITS = 0x000000FF,
103 /** The request was an instruction fetch. */
104 INST_FETCH = 0x00000100,
105 /** The virtual address is also the physical address. */
106 PHYSICAL = 0x00000200,
108 * The request is to an uncacheable address.
110 * @note Uncacheable accesses may be reordered by CPU models. The
111 * STRICT_ORDER flag should be set if such reordering is
114 UNCACHEABLE = 0x00000400,
116 * The request is required to be strictly ordered by <i>CPU
117 * models</i> and is non-speculative.
119 * A strictly ordered request is guaranteed to never be
120 * re-ordered or executed speculatively by a CPU model. The
121 * memory system may still reorder requests in caches unless
122 * the UNCACHEABLE flag is set as well.
124 STRICT_ORDER = 0x00000800,
125 /** This request is to a memory mapped register. */
126 MMAPPED_IPR = 0x00002000,
127 /** This request is made in privileged mode. */
128 PRIVILEGED = 0x00008000,
131 * This is a write that is targeted and zeroing an entire
132 * cache block. There is no need for a read/modify/write
134 CACHE_BLOCK_ZERO = 0x00010000,
136 /** The request should not cause a memory access. */
137 NO_ACCESS = 0x00080000,
139 * This request will lock or unlock the accessed memory. When
140 * used with a load, the access locks the particular chunk of
141 * memory. When used with a store, it unlocks. The rule is
142 * that locked accesses have to be made up of a locked load,
143 * some operation on the data, and then a locked store.
145 LOCKED_RMW = 0x00100000,
146 /** The request is a Load locked/store conditional. */
148 /** This request is for a memory swap. */
149 MEM_SWAP = 0x00400000,
150 MEM_SWAP_COND = 0x00800000,
152 /** The request is a prefetch. */
153 PREFETCH = 0x01000000,
154 /** The request should be prefetched into the exclusive state. */
155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158 /** The request should be marked with ACQUIRE. */
159 ACQUIRE = 0x00020000,
160 /** The request should be marked with RELEASE. */
161 RELEASE = 0x00040000,
163 /** The request is an atomic that returns data. */
164 ATOMIC_RETURN_OP = 0x40000000,
165 /** The request is an atomic that does not return data. */
166 ATOMIC_NO_RETURN_OP = 0x80000000,
168 /** The request should be marked with KERNEL.
169 * Used to indicate the synchronization associated with a GPU kernel
170 * launch or completion.
175 * The request should be handled by the generic IPR code (only
176 * valid together with MMAPPED_IPR)
178 GENERIC_IPR = 0x08000000,
180 /** The request targets the secure memory space. */
182 /** The request is a page table walk */
183 PT_WALK = 0x20000000,
185 /** The request invalidates a memory location */
186 INVALIDATE = 0x0000000100000000,
187 /** The request cleans a memory location */
188 CLEAN = 0x0000000200000000,
190 /** The request targets the point of unification */
191 DST_POU = 0x0000001000000000,
193 /** The request targets the point of coherence */
194 DST_POC = 0x0000002000000000,
196 /** Bits to define the destination of a request */
197 DST_BITS = 0x0000003000000000,
200 * These flags are *not* cleared when a Request object is
201 * reused (assigned a new address).
203 STICKY_FLAGS = INST_FETCH
205 static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
208 /** Master Ids that are statically allocated
211 /** This master id is used for writeback requests by the caches */
214 * This master id is used for functional requests that
215 * don't come from a particular device
218 /** This master id is used for message signaled interrupts */
221 * Invalid master id for assertion checking only. It is
222 * invalid behavior to ever send this id as part of a request.
224 invldMasterId = std::numeric_limits<MasterID>::max()
228 typedef uint32_t MemSpaceConfigFlagsType;
229 typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
231 enum : MemSpaceConfigFlagsType {
232 /** Has a synchronization scope been set? */
233 SCOPE_VALID = 0x00000001,
234 /** Access has Wavefront scope visibility */
235 WAVEFRONT_SCOPE = 0x00000002,
236 /** Access has Workgroup scope visibility */
237 WORKGROUP_SCOPE = 0x00000004,
238 /** Access has Device (e.g., GPU) scope visibility */
239 DEVICE_SCOPE = 0x00000008,
240 /** Access has System (e.g., CPU + GPU) scope visibility */
241 SYSTEM_SCOPE = 0x00000010,
243 /** Global Segment */
244 GLOBAL_SEGMENT = 0x00000020,
246 GROUP_SEGMENT = 0x00000040,
247 /** Private Segment */
248 PRIVATE_SEGMENT = 0x00000080,
249 /** Kergarg Segment */
250 KERNARG_SEGMENT = 0x00000100,
251 /** Readonly Segment */
252 READONLY_SEGMENT = 0x00000200,
254 SPILL_SEGMENT = 0x00000400,
256 ARG_SEGMENT = 0x00000800,
260 typedef uint8_t PrivateFlagsType;
261 typedef ::Flags<PrivateFlagsType> PrivateFlags;
263 enum : PrivateFlagsType {
264 /** Whether or not the size is valid. */
265 VALID_SIZE = 0x00000001,
266 /** Whether or not paddr is valid (has been written yet). */
267 VALID_PADDR = 0x00000002,
268 /** Whether or not the vaddr & asid are valid. */
269 VALID_VADDR = 0x00000004,
270 /** Whether or not the instruction sequence number is valid. */
271 VALID_INST_SEQ_NUM = 0x00000008,
272 /** Whether or not the pc is valid. */
273 VALID_PC = 0x00000010,
274 /** Whether or not the context ID is valid. */
275 VALID_CONTEXT_ID = 0x00000020,
276 /** Whether or not the sc result is valid. */
277 VALID_EXTRA_DATA = 0x00000080,
279 * These flags are *not* cleared when a Request object is reused
280 * (assigned a new address).
282 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
288 * Set up a physical (e.g. device) request in a previously
289 * allocated Request object.
292 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
298 _flags.clear(~STICKY_FLAGS);
300 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
301 privateFlags.set(VALID_PADDR|VALID_SIZE);
304 //translateDelta = 0;
308 * The physical address of the request. Valid only if validPaddr
314 * The size of the request. This field must be set when vaddr or
315 * paddr is written via setVirt() or setPhys(), so it is always
316 * valid as long as one of the address fields is valid.
320 /** The requestor ID which is unique in the system for all ports
321 * that are capable of issuing a transaction
325 /** Flag structure for the request. */
328 /** Memory space configuraiton flag structure for the request. */
329 MemSpaceConfigFlags _memSpaceConfigFlags;
331 /** Private flags for field validity checking. */
332 PrivateFlags privateFlags;
335 * The time this request was started. Used to calculate
336 * latencies. This field is set to curTick() any time paddr or vaddr
342 * The task id associated with this request
346 /** The address space ID. */
349 /** The virtual address of the request. */
353 * Extra data for the request, such as the return value of
354 * store conditional or the compare value for a CAS. */
357 /** The context ID (for statistics, locks, and wakeups). */
358 ContextID _contextId;
360 /** program counter of initiating access; for tracing/debugging */
363 /** Sequence number of the instruction that creates the request */
364 InstSeqNum _reqInstSeqNum;
366 /** A pointer to an atomic operation */
367 AtomicOpFunctor *atomicOpFunctor;
372 * Minimal constructor. No fields are initialized. (Note that
373 * _flags and privateFlags are cleared by Flags default
377 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
378 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
379 _extraData(0), _contextId(0), _pc(0),
380 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
381 accessDelta(0), depth(0)
384 Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
385 InstSeqNum seq_num, ContextID cid)
386 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
387 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
388 _extraData(0), _contextId(0), _pc(0),
389 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
390 accessDelta(0), depth(0)
392 setPhys(paddr, size, flags, mid, curTick());
394 privateFlags.set(VALID_INST_SEQ_NUM);
398 * Constructor for physical (e.g. device) requests. Initializes
399 * just physical address, size, flags, and timestamp (to curTick()).
400 * These fields are adequate to perform a request.
402 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
403 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
404 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
405 _extraData(0), _contextId(0), _pc(0),
406 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
407 accessDelta(0), depth(0)
409 setPhys(paddr, size, flags, mid, curTick());
412 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
413 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
414 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
415 _extraData(0), _contextId(0), _pc(0),
416 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
417 accessDelta(0), depth(0)
419 setPhys(paddr, size, flags, mid, time);
422 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
424 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
425 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
426 _extraData(0), _contextId(0), _pc(pc),
427 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
428 accessDelta(0), depth(0)
430 setPhys(paddr, size, flags, mid, time);
431 privateFlags.set(VALID_PC);
434 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
435 Addr pc, ContextID cid)
436 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
437 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
438 _extraData(0), _contextId(0), _pc(0),
439 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
440 accessDelta(0), depth(0)
442 setVirt(asid, vaddr, size, flags, mid, pc);
446 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
447 Addr pc, ContextID cid, AtomicOpFunctor *atomic_op)
449 setVirt(asid, vaddr, size, flags, mid, pc, atomic_op);
453 Request(const Request& other)
454 : _paddr(other._paddr), _size(other._size),
455 _masterId(other._masterId),
456 _flags(other._flags),
457 _memSpaceConfigFlags(other._memSpaceConfigFlags),
458 privateFlags(other.privateFlags),
460 _taskId(other._taskId), _asid(other._asid), _vaddr(other._vaddr),
461 _extraData(other._extraData), _contextId(other._contextId),
462 _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
463 translateDelta(other.translateDelta),
464 accessDelta(other.accessDelta), depth(other.depth)
466 if (other.atomicOpFunctor)
467 atomicOpFunctor = (other.atomicOpFunctor)->clone();
469 atomicOpFunctor = nullptr;
474 if (hasAtomicOpFunctor()) {
475 delete atomicOpFunctor;
480 * Set up Context numbers.
483 setContext(ContextID context_id)
485 _contextId = context_id;
486 privateFlags.set(VALID_CONTEXT_ID);
490 * Set up a virtual (e.g., CPU) request in a previously
491 * allocated Request object.
494 setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
495 Addr pc, AtomicOpFunctor *amo_op = nullptr)
504 _flags.clear(~STICKY_FLAGS);
506 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
507 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
511 atomicOpFunctor = amo_op;
515 * Set just the physical address. This usually used to record the
516 * result of a translation. However, when using virtualized CPUs
517 * setPhys() is sometimes called to finalize a physical address
518 * without a virtual address, so we can't check if the virtual
525 privateFlags.set(VALID_PADDR);
529 * Generate two requests as if this request had been split into two
530 * pieces. The original request can't have been translated already.
532 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
534 assert(privateFlags.isSet(VALID_VADDR));
535 assert(privateFlags.noneSet(VALID_PADDR));
536 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
537 req1 = std::make_shared<Request>(*this);
538 req2 = std::make_shared<Request>(*this);
539 req1->_size = split_addr - _vaddr;
540 req2->_vaddr = split_addr;
541 req2->_size = _size - req1->_size;
545 * Accessor for paddr.
550 return privateFlags.isSet(VALID_PADDR);
556 assert(privateFlags.isSet(VALID_PADDR));
561 * Time for the TLB/table walker to successfully translate this request.
566 * Access latency to complete this memory transaction not including
572 * Level of the cache hierachy where this request was responded to
573 * (e.g. 0 = L1; 1 = L2).
583 return privateFlags.isSet(VALID_SIZE);
589 assert(privateFlags.isSet(VALID_SIZE));
593 /** Accessor for time. */
597 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
602 * Accessor for atomic-op functor.
607 return atomicOpFunctor != NULL;
613 assert(atomicOpFunctor != NULL);
614 return atomicOpFunctor;
617 /** Accessor for flags. */
621 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
625 /** Note that unlike other accessors, this function sets *specific
626 flags* (ORs them in); it does not assign its argument to the
627 _flags field. Thus this method should rightly be called
628 setFlags() and not just flags(). */
630 setFlags(Flags flags)
632 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
637 setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
639 assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
640 _memSpaceConfigFlags.set(extraFlags);
643 /** Accessor function for vaddr.*/
647 return privateFlags.isSet(VALID_VADDR);
653 assert(privateFlags.isSet(VALID_VADDR));
657 /** Accesssor for the requestor id. */
671 taskId(uint32_t id) {
675 /** Accessor function for asid.*/
679 assert(privateFlags.isSet(VALID_VADDR));
683 /** Accessor function for asid.*/
690 /** Accessor function for architecture-specific flags.*/
694 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
695 return _flags & ARCH_BITS;
698 /** Accessor function to check if sc result is valid. */
700 extraDataValid() const
702 return privateFlags.isSet(VALID_EXTRA_DATA);
705 /** Accessor function for store conditional return value.*/
709 assert(privateFlags.isSet(VALID_EXTRA_DATA));
713 /** Accessor function for store conditional return value.*/
715 setExtraData(uint64_t extraData)
717 _extraData = extraData;
718 privateFlags.set(VALID_EXTRA_DATA);
724 return privateFlags.isSet(VALID_CONTEXT_ID);
727 /** Accessor function for context ID.*/
731 assert(privateFlags.isSet(VALID_CONTEXT_ID));
738 privateFlags.set(VALID_PC);
745 return privateFlags.isSet(VALID_PC);
748 /** Accessor function for pc.*/
752 assert(privateFlags.isSet(VALID_PC));
757 * Increment/Get the depth at which this request is responded to.
758 * This currently happens when the request misses in any cache level.
760 void incAccessDepth() const { depth++; }
761 int getAccessDepth() const { return depth; }
764 * Set/Get the time taken for this request to be successfully translated.
766 void setTranslateLatency() { translateDelta = curTick() - _time; }
767 Tick getTranslateLatency() const { return translateDelta; }
770 * Set/Get the time taken to complete this request's access, not including
771 * the time to successfully translate the request.
773 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
774 Tick getAccessLatency() const { return accessDelta; }
777 * Accessor for the sequence number of instruction that creates the
781 hasInstSeqNum() const
783 return privateFlags.isSet(VALID_INST_SEQ_NUM);
787 getReqInstSeqNum() const
789 assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
790 return _reqInstSeqNum;
794 setReqInstSeqNum(const InstSeqNum seq_num)
796 privateFlags.set(VALID_INST_SEQ_NUM);
797 _reqInstSeqNum = seq_num;
800 /** Accessor functions for flags. Note that these are for testing
801 only; setting flags should be done via setFlags(). */
802 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
803 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
804 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
805 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
806 bool isLLSC() const { return _flags.isSet(LLSC); }
807 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
808 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
809 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
810 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
811 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
812 bool isSecure() const { return _flags.isSet(SECURE); }
813 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
814 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
815 bool isRelease() const { return _flags.isSet(RELEASE); }
816 bool isKernel() const { return _flags.isSet(KERNEL); }
817 bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
818 bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
823 return _flags.isSet(ATOMIC_RETURN_OP) ||
824 _flags.isSet(ATOMIC_NO_RETURN_OP);
828 * Accessor functions for the destination of a memory request. The
829 * destination flag can specify a point of reference for the
830 * operation (e.g. a cache block clean to the the point of
831 * unification). At the moment the destination is only used by the
832 * cache maintenance operations.
834 bool isToPOU() const { return _flags.isSet(DST_POU); }
835 bool isToPOC() const { return _flags.isSet(DST_POC); }
836 Flags getDest() const { return _flags & DST_BITS; }
839 * Accessor functions for the memory space configuration flags and used by
840 * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
841 * these are for testing only; setting extraFlags should be done via
842 * setMemSpaceConfigFlags().
844 bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
847 isWavefrontScope() const
850 return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
854 isWorkgroupScope() const
857 return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
861 isDeviceScope() const
864 return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
868 isSystemScope() const
871 return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
875 isGlobalSegment() const
877 return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
878 (!isGroupSegment() && !isPrivateSegment() &&
879 !isKernargSegment() && !isReadonlySegment() &&
880 !isSpillSegment() && !isArgSegment());
884 isGroupSegment() const
886 return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
890 isPrivateSegment() const
892 return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
896 isKernargSegment() const
898 return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
902 isReadonlySegment() const
904 return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
908 isSpillSegment() const
910 return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
916 return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
920 * Accessor functions to determine whether this request is part of
921 * a cache maintenance operation. At the moment three operations
924 * 1) A cache clean operation updates all copies of a memory
925 * location to the point of reference,
926 * 2) A cache invalidate operation invalidates all copies of the
927 * specified block in the memory above the point of reference,
928 * 3) A clean and invalidate operation is a combination of the two
931 bool isCacheClean() const { return _flags.isSet(CLEAN); }
932 bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
933 bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
937 #endif // __MEM_REQUEST_HH__