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41 * Authors: Ron Dreslinski
48 * Declaration of a request, the overall memory request consisting of
49 the parts of the request that are persistent throughout the transaction.
52 #ifndef __MEM_REQUEST_HH__
53 #define __MEM_REQUEST_HH__
58 #include "base/flags.hh"
59 #include "base/logging.hh"
60 #include "base/types.hh"
61 #include "cpu/inst_seq.hh"
62 #include "sim/core.hh"
65 * Special TaskIds that are used for per-context-switch stats dumps
66 * and Cache Occupancy. Having too many tasks seems to be a problem
67 * with vector stats. 1024 seems to be a reasonable number that
68 * doesn't cause a problem with stats and is large enough to realistic
69 * benchmarks (Linux/Android boot, BBench, etc.)
72 namespace ContextSwitchTaskId {
74 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
75 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
76 DMA = 1023, /* Mostly Table Walker */
84 typedef std::shared_ptr<Request> RequestPtr;
85 typedef uint16_t MasterID;
90 typedef uint64_t FlagsType;
91 typedef uint8_t ArchFlagsType;
92 typedef ::Flags<FlagsType> Flags;
96 * Architecture specific flags.
98 * These bits int the flag field are reserved for
99 * architecture-specific code. For example, SPARC uses them to
102 ARCH_BITS = 0x000000FF,
103 /** The request was an instruction fetch. */
104 INST_FETCH = 0x00000100,
105 /** The virtual address is also the physical address. */
106 PHYSICAL = 0x00000200,
108 * The request is to an uncacheable address.
110 * @note Uncacheable accesses may be reordered by CPU models. The
111 * STRICT_ORDER flag should be set if such reordering is
114 UNCACHEABLE = 0x00000400,
116 * The request is required to be strictly ordered by <i>CPU
117 * models</i> and is non-speculative.
119 * A strictly ordered request is guaranteed to never be
120 * re-ordered or executed speculatively by a CPU model. The
121 * memory system may still reorder requests in caches unless
122 * the UNCACHEABLE flag is set as well.
124 STRICT_ORDER = 0x00000800,
125 /** This request is to a memory mapped register. */
126 MMAPPED_IPR = 0x00002000,
127 /** This request is made in privileged mode. */
128 PRIVILEGED = 0x00008000,
131 * This is a write that is targeted and zeroing an entire
132 * cache block. There is no need for a read/modify/write
134 CACHE_BLOCK_ZERO = 0x00010000,
136 /** The request should not cause a memory access. */
137 NO_ACCESS = 0x00080000,
139 * This request will lock or unlock the accessed memory. When
140 * used with a load, the access locks the particular chunk of
141 * memory. When used with a store, it unlocks. The rule is
142 * that locked accesses have to be made up of a locked load,
143 * some operation on the data, and then a locked store.
145 LOCKED_RMW = 0x00100000,
146 /** The request is a Load locked/store conditional. */
148 /** This request is for a memory swap. */
149 MEM_SWAP = 0x00400000,
150 MEM_SWAP_COND = 0x00800000,
152 /** The request is a prefetch. */
153 PREFETCH = 0x01000000,
154 /** The request should be prefetched into the exclusive state. */
155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158 /** The request should be marked with ACQUIRE. */
159 ACQUIRE = 0x00020000,
160 /** The request should be marked with RELEASE. */
161 RELEASE = 0x00040000,
163 /** The request is an atomic that returns data. */
164 ATOMIC_RETURN_OP = 0x40000000,
165 /** The request is an atomic that does not return data. */
166 ATOMIC_NO_RETURN_OP = 0x80000000,
168 /** The request should be marked with KERNEL.
169 * Used to indicate the synchronization associated with a GPU kernel
170 * launch or completion.
175 * The request should be handled by the generic IPR code (only
176 * valid together with MMAPPED_IPR)
178 GENERIC_IPR = 0x08000000,
180 /** The request targets the secure memory space. */
182 /** The request is a page table walk */
183 PT_WALK = 0x20000000,
185 /** The request invalidates a memory location */
186 INVALIDATE = 0x0000000100000000,
187 /** The request cleans a memory location */
188 CLEAN = 0x0000000200000000,
190 /** The request targets the point of unification */
191 DST_POU = 0x0000001000000000,
193 /** The request targets the point of coherence */
194 DST_POC = 0x0000002000000000,
196 /** Bits to define the destination of a request */
197 DST_BITS = 0x0000003000000000,
200 * These flags are *not* cleared when a Request object is
201 * reused (assigned a new address).
203 STICKY_FLAGS = INST_FETCH
205 static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
208 /** Master Ids that are statically allocated
211 /** This master id is used for writeback requests by the caches */
214 * This master id is used for functional requests that
215 * don't come from a particular device
218 /** This master id is used for message signaled interrupts */
221 * Invalid master id for assertion checking only. It is
222 * invalid behavior to ever send this id as part of a request.
224 invldMasterId = std::numeric_limits<MasterID>::max()
228 typedef uint32_t MemSpaceConfigFlagsType;
229 typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
231 enum : MemSpaceConfigFlagsType {
232 /** Has a synchronization scope been set? */
233 SCOPE_VALID = 0x00000001,
234 /** Access has Wavefront scope visibility */
235 WAVEFRONT_SCOPE = 0x00000002,
236 /** Access has Workgroup scope visibility */
237 WORKGROUP_SCOPE = 0x00000004,
238 /** Access has Device (e.g., GPU) scope visibility */
239 DEVICE_SCOPE = 0x00000008,
240 /** Access has System (e.g., CPU + GPU) scope visibility */
241 SYSTEM_SCOPE = 0x00000010,
243 /** Global Segment */
244 GLOBAL_SEGMENT = 0x00000020,
246 GROUP_SEGMENT = 0x00000040,
247 /** Private Segment */
248 PRIVATE_SEGMENT = 0x00000080,
249 /** Kergarg Segment */
250 KERNARG_SEGMENT = 0x00000100,
251 /** Readonly Segment */
252 READONLY_SEGMENT = 0x00000200,
254 SPILL_SEGMENT = 0x00000400,
256 ARG_SEGMENT = 0x00000800,
260 typedef uint16_t PrivateFlagsType;
261 typedef ::Flags<PrivateFlagsType> PrivateFlags;
263 enum : PrivateFlagsType {
264 /** Whether or not the size is valid. */
265 VALID_SIZE = 0x00000001,
266 /** Whether or not paddr is valid (has been written yet). */
267 VALID_PADDR = 0x00000002,
268 /** Whether or not the vaddr & asid are valid. */
269 VALID_VADDR = 0x00000004,
270 /** Whether or not the instruction sequence number is valid. */
271 VALID_INST_SEQ_NUM = 0x00000008,
272 /** Whether or not the pc is valid. */
273 VALID_PC = 0x00000010,
274 /** Whether or not the context ID is valid. */
275 VALID_CONTEXT_ID = 0x00000020,
276 /** Whether or not the sc result is valid. */
277 VALID_EXTRA_DATA = 0x00000080,
278 /** Whether or not the stream ID and substream ID is valid. */
279 VALID_STREAM_ID = 0x00000100,
280 VALID_SUBSTREAM_ID = 0x00000200,
282 * These flags are *not* cleared when a Request object is reused
283 * (assigned a new address).
285 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
291 * Set up a physical (e.g. device) request in a previously
292 * allocated Request object.
295 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
301 _flags.clear(~STICKY_FLAGS);
303 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
304 privateFlags.set(VALID_PADDR|VALID_SIZE);
307 //translateDelta = 0;
311 * The physical address of the request. Valid only if validPaddr
317 * The size of the request. This field must be set when vaddr or
318 * paddr is written via setVirt() or setPhys(), so it is always
319 * valid as long as one of the address fields is valid.
323 /** The requestor ID which is unique in the system for all ports
324 * that are capable of issuing a transaction
328 /** Flag structure for the request. */
331 /** Memory space configuraiton flag structure for the request. */
332 MemSpaceConfigFlags _memSpaceConfigFlags;
334 /** Private flags for field validity checking. */
335 PrivateFlags privateFlags;
338 * The time this request was started. Used to calculate
339 * latencies. This field is set to curTick() any time paddr or vaddr
345 * The task id associated with this request
352 * The stream ID uniquely identifies a device behind the
353 * SMMU/IOMMU Each transaction arriving at the SMMU/IOMMU is
354 * associated with exactly one stream ID.
359 * The substream ID identifies an "execution context" within a
360 * device behind an SMMU/IOMMU. It's intended to map 1-to-1 to
361 * PCIe PASID (Process Address Space ID). The presence of a
362 * substream ID is optional.
364 uint32_t _substreamId;
367 /** The address space ID. */
371 /** The virtual address of the request. */
375 * Extra data for the request, such as the return value of
376 * store conditional or the compare value for a CAS. */
379 /** The context ID (for statistics, locks, and wakeups). */
380 ContextID _contextId;
382 /** program counter of initiating access; for tracing/debugging */
385 /** Sequence number of the instruction that creates the request */
386 InstSeqNum _reqInstSeqNum;
388 /** A pointer to an atomic operation */
389 AtomicOpFunctor *atomicOpFunctor;
394 * Minimal constructor. No fields are initialized. (Note that
395 * _flags and privateFlags are cleared by Flags default
399 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
400 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
401 _extraData(0), _contextId(0), _pc(0),
402 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
403 accessDelta(0), depth(0)
406 Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
407 InstSeqNum seq_num, ContextID cid)
408 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
409 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
410 _extraData(0), _contextId(0), _pc(0),
411 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
412 accessDelta(0), depth(0)
414 setPhys(paddr, size, flags, mid, curTick());
416 privateFlags.set(VALID_INST_SEQ_NUM);
420 * Constructor for physical (e.g. device) requests. Initializes
421 * just physical address, size, flags, and timestamp (to curTick()).
422 * These fields are adequate to perform a request.
424 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
425 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
426 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
427 _extraData(0), _contextId(0), _pc(0),
428 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
429 accessDelta(0), depth(0)
431 setPhys(paddr, size, flags, mid, curTick());
434 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
435 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
436 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
437 _extraData(0), _contextId(0), _pc(0),
438 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
439 accessDelta(0), depth(0)
441 setPhys(paddr, size, flags, mid, time);
444 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
446 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
447 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
448 _extraData(0), _contextId(0), _pc(pc),
449 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
450 accessDelta(0), depth(0)
452 setPhys(paddr, size, flags, mid, time);
453 privateFlags.set(VALID_PC);
456 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
457 MasterID mid, Addr pc, ContextID cid)
458 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
459 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
460 _extraData(0), _contextId(0), _pc(0),
461 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
462 accessDelta(0), depth(0)
464 setVirt(asid, vaddr, size, flags, mid, pc);
468 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
469 MasterID mid, Addr pc, ContextID cid,
470 AtomicOpFunctor *atomic_op)
472 setVirt(asid, vaddr, size, flags, mid, pc, atomic_op);
476 Request(const Request& other)
477 : _paddr(other._paddr), _size(other._size),
478 _masterId(other._masterId),
479 _flags(other._flags),
480 _memSpaceConfigFlags(other._memSpaceConfigFlags),
481 privateFlags(other.privateFlags),
483 _taskId(other._taskId), _asid(other._asid), _vaddr(other._vaddr),
484 _extraData(other._extraData), _contextId(other._contextId),
485 _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
486 translateDelta(other.translateDelta),
487 accessDelta(other.accessDelta), depth(other.depth)
489 if (other.atomicOpFunctor)
490 atomicOpFunctor = (other.atomicOpFunctor)->clone();
492 atomicOpFunctor = nullptr;
497 if (hasAtomicOpFunctor()) {
498 delete atomicOpFunctor;
503 * Set up Context numbers.
506 setContext(ContextID context_id)
508 _contextId = context_id;
509 privateFlags.set(VALID_CONTEXT_ID);
513 setStreamId(uint32_t sid)
516 privateFlags.set(VALID_STREAM_ID);
520 setSubStreamId(uint32_t ssid)
522 assert(privateFlags.isSet(VALID_STREAM_ID));
524 privateFlags.set(VALID_SUBSTREAM_ID);
528 * Set up a virtual (e.g., CPU) request in a previously
529 * allocated Request object.
532 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
533 MasterID mid, Addr pc, AtomicOpFunctor *amo_op = nullptr)
542 _flags.clear(~STICKY_FLAGS);
544 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
545 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
549 atomicOpFunctor = amo_op;
553 * Set just the physical address. This usually used to record the
554 * result of a translation. However, when using virtualized CPUs
555 * setPhys() is sometimes called to finalize a physical address
556 * without a virtual address, so we can't check if the virtual
563 privateFlags.set(VALID_PADDR);
567 * Generate two requests as if this request had been split into two
568 * pieces. The original request can't have been translated already.
570 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
572 assert(privateFlags.isSet(VALID_VADDR));
573 assert(privateFlags.noneSet(VALID_PADDR));
574 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
575 req1 = std::make_shared<Request>(*this);
576 req2 = std::make_shared<Request>(*this);
577 req1->_size = split_addr - _vaddr;
578 req2->_vaddr = split_addr;
579 req2->_size = _size - req1->_size;
583 * Accessor for paddr.
588 return privateFlags.isSet(VALID_PADDR);
594 assert(privateFlags.isSet(VALID_PADDR));
599 * Time for the TLB/table walker to successfully translate this request.
604 * Access latency to complete this memory transaction not including
610 * Level of the cache hierachy where this request was responded to
611 * (e.g. 0 = L1; 1 = L2).
621 return privateFlags.isSet(VALID_SIZE);
627 assert(privateFlags.isSet(VALID_SIZE));
631 /** Accessor for time. */
635 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
640 * Accessor for atomic-op functor.
645 return atomicOpFunctor != NULL;
651 assert(atomicOpFunctor != NULL);
652 return atomicOpFunctor;
655 /** Accessor for flags. */
659 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
663 /** Note that unlike other accessors, this function sets *specific
664 flags* (ORs them in); it does not assign its argument to the
665 _flags field. Thus this method should rightly be called
666 setFlags() and not just flags(). */
668 setFlags(Flags flags)
670 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
675 setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
677 assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
678 _memSpaceConfigFlags.set(extraFlags);
681 /** Accessor function for vaddr.*/
685 return privateFlags.isSet(VALID_VADDR);
691 assert(privateFlags.isSet(VALID_VADDR));
695 /** Accesssor for the requestor id. */
709 taskId(uint32_t id) {
713 /** Accessor function for asid.*/
717 assert(privateFlags.isSet(VALID_VADDR));
721 /** Accessor function for asid.*/
723 setAsid(uint64_t asid)
728 /** Accessor function for architecture-specific flags.*/
732 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
733 return _flags & ARCH_BITS;
736 /** Accessor function to check if sc result is valid. */
738 extraDataValid() const
740 return privateFlags.isSet(VALID_EXTRA_DATA);
743 /** Accessor function for store conditional return value.*/
747 assert(privateFlags.isSet(VALID_EXTRA_DATA));
751 /** Accessor function for store conditional return value.*/
753 setExtraData(uint64_t extraData)
755 _extraData = extraData;
756 privateFlags.set(VALID_EXTRA_DATA);
762 return privateFlags.isSet(VALID_CONTEXT_ID);
765 /** Accessor function for context ID.*/
769 assert(privateFlags.isSet(VALID_CONTEXT_ID));
776 assert(privateFlags.isSet(VALID_STREAM_ID));
781 hasSubstreamId() const
783 return privateFlags.isSet(VALID_SUBSTREAM_ID);
789 assert(privateFlags.isSet(VALID_SUBSTREAM_ID));
796 privateFlags.set(VALID_PC);
803 return privateFlags.isSet(VALID_PC);
806 /** Accessor function for pc.*/
810 assert(privateFlags.isSet(VALID_PC));
815 * Increment/Get the depth at which this request is responded to.
816 * This currently happens when the request misses in any cache level.
818 void incAccessDepth() const { depth++; }
819 int getAccessDepth() const { return depth; }
822 * Set/Get the time taken for this request to be successfully translated.
824 void setTranslateLatency() { translateDelta = curTick() - _time; }
825 Tick getTranslateLatency() const { return translateDelta; }
828 * Set/Get the time taken to complete this request's access, not including
829 * the time to successfully translate the request.
831 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
832 Tick getAccessLatency() const { return accessDelta; }
835 * Accessor for the sequence number of instruction that creates the
839 hasInstSeqNum() const
841 return privateFlags.isSet(VALID_INST_SEQ_NUM);
845 getReqInstSeqNum() const
847 assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
848 return _reqInstSeqNum;
852 setReqInstSeqNum(const InstSeqNum seq_num)
854 privateFlags.set(VALID_INST_SEQ_NUM);
855 _reqInstSeqNum = seq_num;
858 /** Accessor functions for flags. Note that these are for testing
859 only; setting flags should be done via setFlags(). */
860 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
861 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
862 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
863 bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
864 _flags.isSet(PF_EXCLUSIVE)); }
865 bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
866 bool isLLSC() const { return _flags.isSet(LLSC); }
867 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
868 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
869 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
870 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
871 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
872 bool isSecure() const { return _flags.isSet(SECURE); }
873 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
874 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
875 bool isRelease() const { return _flags.isSet(RELEASE); }
876 bool isKernel() const { return _flags.isSet(KERNEL); }
877 bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
878 bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
883 return _flags.isSet(ATOMIC_RETURN_OP) ||
884 _flags.isSet(ATOMIC_NO_RETURN_OP);
888 * Accessor functions for the destination of a memory request. The
889 * destination flag can specify a point of reference for the
890 * operation (e.g. a cache block clean to the the point of
891 * unification). At the moment the destination is only used by the
892 * cache maintenance operations.
894 bool isToPOU() const { return _flags.isSet(DST_POU); }
895 bool isToPOC() const { return _flags.isSet(DST_POC); }
896 Flags getDest() const { return _flags & DST_BITS; }
899 * Accessor functions for the memory space configuration flags and used by
900 * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
901 * these are for testing only; setting extraFlags should be done via
902 * setMemSpaceConfigFlags().
904 bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
907 isWavefrontScope() const
910 return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
914 isWorkgroupScope() const
917 return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
921 isDeviceScope() const
924 return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
928 isSystemScope() const
931 return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
935 isGlobalSegment() const
937 return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
938 (!isGroupSegment() && !isPrivateSegment() &&
939 !isKernargSegment() && !isReadonlySegment() &&
940 !isSpillSegment() && !isArgSegment());
944 isGroupSegment() const
946 return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
950 isPrivateSegment() const
952 return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
956 isKernargSegment() const
958 return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
962 isReadonlySegment() const
964 return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
968 isSpillSegment() const
970 return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
976 return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
980 * Accessor functions to determine whether this request is part of
981 * a cache maintenance operation. At the moment three operations
984 * 1) A cache clean operation updates all copies of a memory
985 * location to the point of reference,
986 * 2) A cache invalidate operation invalidates all copies of the
987 * specified block in the memory above the point of reference,
988 * 3) A clean and invalidate operation is a combination of the two
991 bool isCacheClean() const { return _flags.isSet(CLEAN); }
992 bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
993 bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
997 #endif // __MEM_REQUEST_HH__