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41 * Authors: Ron Dreslinski
48 * Declaration of a request, the overall memory request consisting of
49 the parts of the request that are persistent throughout the transaction.
52 #ifndef __MEM_REQUEST_HH__
53 #define __MEM_REQUEST_HH__
58 #include "base/flags.hh"
59 #include "base/logging.hh"
60 #include "base/types.hh"
61 #include "cpu/inst_seq.hh"
62 #include "sim/core.hh"
65 * Special TaskIds that are used for per-context-switch stats dumps
66 * and Cache Occupancy. Having too many tasks seems to be a problem
67 * with vector stats. 1024 seems to be a reasonable number that
68 * doesn't cause a problem with stats and is large enough to realistic
69 * benchmarks (Linux/Android boot, BBench, etc.)
72 namespace ContextSwitchTaskId {
74 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
75 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
76 DMA = 1023, /* Mostly Table Walker */
84 typedef std::shared_ptr<Request> RequestPtr;
85 typedef uint16_t MasterID;
90 typedef uint64_t FlagsType;
91 typedef uint8_t ArchFlagsType;
92 typedef ::Flags<FlagsType> Flags;
96 * Architecture specific flags.
98 * These bits int the flag field are reserved for
99 * architecture-specific code. For example, SPARC uses them to
102 ARCH_BITS = 0x000000FF,
103 /** The request was an instruction fetch. */
104 INST_FETCH = 0x00000100,
105 /** The virtual address is also the physical address. */
106 PHYSICAL = 0x00000200,
108 * The request is to an uncacheable address.
110 * @note Uncacheable accesses may be reordered by CPU models. The
111 * STRICT_ORDER flag should be set if such reordering is
114 UNCACHEABLE = 0x00000400,
116 * The request is required to be strictly ordered by <i>CPU
117 * models</i> and is non-speculative.
119 * A strictly ordered request is guaranteed to never be
120 * re-ordered or executed speculatively by a CPU model. The
121 * memory system may still reorder requests in caches unless
122 * the UNCACHEABLE flag is set as well.
124 STRICT_ORDER = 0x00000800,
125 /** This request is to a memory mapped register. */
126 MMAPPED_IPR = 0x00002000,
127 /** This request is made in privileged mode. */
128 PRIVILEGED = 0x00008000,
131 * This is a write that is targeted and zeroing an entire
132 * cache block. There is no need for a read/modify/write
134 CACHE_BLOCK_ZERO = 0x00010000,
136 /** The request should not cause a memory access. */
137 NO_ACCESS = 0x00080000,
139 * This request will lock or unlock the accessed memory. When
140 * used with a load, the access locks the particular chunk of
141 * memory. When used with a store, it unlocks. The rule is
142 * that locked accesses have to be made up of a locked load,
143 * some operation on the data, and then a locked store.
145 LOCKED_RMW = 0x00100000,
146 /** The request is a Load locked/store conditional. */
148 /** This request is for a memory swap. */
149 MEM_SWAP = 0x00400000,
150 MEM_SWAP_COND = 0x00800000,
152 /** The request is a prefetch. */
153 PREFETCH = 0x01000000,
154 /** The request should be prefetched into the exclusive state. */
155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158 /** The request should be marked with ACQUIRE. */
159 ACQUIRE = 0x00020000,
160 /** The request should be marked with RELEASE. */
161 RELEASE = 0x00040000,
163 /** The request is an atomic that returns data. */
164 ATOMIC_RETURN_OP = 0x40000000,
165 /** The request is an atomic that does not return data. */
166 ATOMIC_NO_RETURN_OP = 0x80000000,
168 /** The request should be marked with KERNEL.
169 * Used to indicate the synchronization associated with a GPU kernel
170 * launch or completion.
175 * The request should be handled by the generic IPR code (only
176 * valid together with MMAPPED_IPR)
178 GENERIC_IPR = 0x08000000,
180 /** The request targets the secure memory space. */
182 /** The request is a page table walk */
183 PT_WALK = 0x20000000,
185 /** The request invalidates a memory location */
186 INVALIDATE = 0x0000000100000000,
187 /** The request cleans a memory location */
188 CLEAN = 0x0000000200000000,
190 /** The request targets the point of unification */
191 DST_POU = 0x0000001000000000,
193 /** The request targets the point of coherence */
194 DST_POC = 0x0000002000000000,
196 /** Bits to define the destination of a request */
197 DST_BITS = 0x0000003000000000,
200 * These flags are *not* cleared when a Request object is
201 * reused (assigned a new address).
203 STICKY_FLAGS = INST_FETCH
205 static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
208 /** Master Ids that are statically allocated
211 /** This master id is used for writeback requests by the caches */
214 * This master id is used for functional requests that
215 * don't come from a particular device
218 /** This master id is used for message signaled interrupts */
221 * Invalid master id for assertion checking only. It is
222 * invalid behavior to ever send this id as part of a request.
224 invldMasterId = std::numeric_limits<MasterID>::max()
228 typedef uint32_t MemSpaceConfigFlagsType;
229 typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
231 enum : MemSpaceConfigFlagsType {
232 /** Has a synchronization scope been set? */
233 SCOPE_VALID = 0x00000001,
234 /** Access has Wavefront scope visibility */
235 WAVEFRONT_SCOPE = 0x00000002,
236 /** Access has Workgroup scope visibility */
237 WORKGROUP_SCOPE = 0x00000004,
238 /** Access has Device (e.g., GPU) scope visibility */
239 DEVICE_SCOPE = 0x00000008,
240 /** Access has System (e.g., CPU + GPU) scope visibility */
241 SYSTEM_SCOPE = 0x00000010,
243 /** Global Segment */
244 GLOBAL_SEGMENT = 0x00000020,
246 GROUP_SEGMENT = 0x00000040,
247 /** Private Segment */
248 PRIVATE_SEGMENT = 0x00000080,
249 /** Kergarg Segment */
250 KERNARG_SEGMENT = 0x00000100,
251 /** Readonly Segment */
252 READONLY_SEGMENT = 0x00000200,
254 SPILL_SEGMENT = 0x00000400,
256 ARG_SEGMENT = 0x00000800,
260 typedef uint16_t PrivateFlagsType;
261 typedef ::Flags<PrivateFlagsType> PrivateFlags;
263 enum : PrivateFlagsType {
264 /** Whether or not the size is valid. */
265 VALID_SIZE = 0x00000001,
266 /** Whether or not paddr is valid (has been written yet). */
267 VALID_PADDR = 0x00000002,
268 /** Whether or not the vaddr & asid are valid. */
269 VALID_VADDR = 0x00000004,
270 /** Whether or not the instruction sequence number is valid. */
271 VALID_INST_SEQ_NUM = 0x00000008,
272 /** Whether or not the pc is valid. */
273 VALID_PC = 0x00000010,
274 /** Whether or not the context ID is valid. */
275 VALID_CONTEXT_ID = 0x00000020,
276 /** Whether or not the sc result is valid. */
277 VALID_EXTRA_DATA = 0x00000080,
278 /** Whether or not the stream ID and substream ID is valid. */
279 VALID_STREAM_ID = 0x00000100,
280 VALID_SUBSTREAM_ID = 0x00000200,
282 * These flags are *not* cleared when a Request object is reused
283 * (assigned a new address).
285 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
291 * Set up a physical (e.g. device) request in a previously
292 * allocated Request object.
295 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
301 _flags.clear(~STICKY_FLAGS);
303 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
304 privateFlags.set(VALID_PADDR|VALID_SIZE);
307 //translateDelta = 0;
311 * The physical address of the request. Valid only if validPaddr
317 * The size of the request. This field must be set when vaddr or
318 * paddr is written via setVirt() or setPhys(), so it is always
319 * valid as long as one of the address fields is valid.
323 /** Byte-enable mask for writes. */
324 std::vector<bool> _byteEnable;
326 /** The requestor ID which is unique in the system for all ports
327 * that are capable of issuing a transaction
331 /** Flag structure for the request. */
334 /** Memory space configuraiton flag structure for the request. */
335 MemSpaceConfigFlags _memSpaceConfigFlags;
337 /** Private flags for field validity checking. */
338 PrivateFlags privateFlags;
341 * The time this request was started. Used to calculate
342 * latencies. This field is set to curTick() any time paddr or vaddr
348 * The task id associated with this request
355 * The stream ID uniquely identifies a device behind the
356 * SMMU/IOMMU Each transaction arriving at the SMMU/IOMMU is
357 * associated with exactly one stream ID.
362 * The substream ID identifies an "execution context" within a
363 * device behind an SMMU/IOMMU. It's intended to map 1-to-1 to
364 * PCIe PASID (Process Address Space ID). The presence of a
365 * substream ID is optional.
367 uint32_t _substreamId;
370 /** The address space ID. */
374 /** The virtual address of the request. */
378 * Extra data for the request, such as the return value of
379 * store conditional or the compare value for a CAS. */
382 /** The context ID (for statistics, locks, and wakeups). */
383 ContextID _contextId;
385 /** program counter of initiating access; for tracing/debugging */
388 /** Sequence number of the instruction that creates the request */
389 InstSeqNum _reqInstSeqNum;
391 /** A pointer to an atomic operation */
392 AtomicOpFunctor *atomicOpFunctor;
397 * Minimal constructor. No fields are initialized. (Note that
398 * _flags and privateFlags are cleared by Flags default
402 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
403 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
404 _extraData(0), _contextId(0), _pc(0),
405 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
406 accessDelta(0), depth(0)
409 Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
410 InstSeqNum seq_num, ContextID cid)
411 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
412 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
413 _extraData(0), _contextId(0), _pc(0),
414 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
415 accessDelta(0), depth(0)
417 setPhys(paddr, size, flags, mid, curTick());
419 privateFlags.set(VALID_INST_SEQ_NUM);
423 * Constructor for physical (e.g. device) requests. Initializes
424 * just physical address, size, flags, and timestamp (to curTick()).
425 * These fields are adequate to perform a request.
427 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
428 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
429 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
430 _extraData(0), _contextId(0), _pc(0),
431 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
432 accessDelta(0), depth(0)
434 setPhys(paddr, size, flags, mid, curTick());
437 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
438 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
439 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
440 _extraData(0), _contextId(0), _pc(0),
441 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
442 accessDelta(0), depth(0)
444 setPhys(paddr, size, flags, mid, time);
447 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
449 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
450 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
451 _extraData(0), _contextId(0), _pc(pc),
452 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
453 accessDelta(0), depth(0)
455 setPhys(paddr, size, flags, mid, time);
456 privateFlags.set(VALID_PC);
459 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
460 MasterID mid, Addr pc, ContextID cid)
461 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
462 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
463 _extraData(0), _contextId(0), _pc(0),
464 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
465 accessDelta(0), depth(0)
467 setVirt(asid, vaddr, size, flags, mid, pc);
471 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
472 MasterID mid, Addr pc, ContextID cid,
473 AtomicOpFunctor *atomic_op)
475 setVirt(asid, vaddr, size, flags, mid, pc, atomic_op);
479 Request(const Request& other)
480 : _paddr(other._paddr), _size(other._size),
481 _masterId(other._masterId),
482 _flags(other._flags),
483 _memSpaceConfigFlags(other._memSpaceConfigFlags),
484 privateFlags(other.privateFlags),
486 _taskId(other._taskId), _asid(other._asid), _vaddr(other._vaddr),
487 _extraData(other._extraData), _contextId(other._contextId),
488 _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
489 translateDelta(other.translateDelta),
490 accessDelta(other.accessDelta), depth(other.depth)
492 if (other.atomicOpFunctor)
493 atomicOpFunctor = (other.atomicOpFunctor)->clone();
495 atomicOpFunctor = nullptr;
500 if (hasAtomicOpFunctor()) {
501 delete atomicOpFunctor;
506 * Set up Context numbers.
509 setContext(ContextID context_id)
511 _contextId = context_id;
512 privateFlags.set(VALID_CONTEXT_ID);
516 setStreamId(uint32_t sid)
519 privateFlags.set(VALID_STREAM_ID);
523 setSubStreamId(uint32_t ssid)
525 assert(privateFlags.isSet(VALID_STREAM_ID));
527 privateFlags.set(VALID_SUBSTREAM_ID);
531 * Set up a virtual (e.g., CPU) request in a previously
532 * allocated Request object.
535 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
536 MasterID mid, Addr pc, AtomicOpFunctor *amo_op = nullptr)
545 _flags.clear(~STICKY_FLAGS);
547 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
548 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
552 atomicOpFunctor = amo_op;
556 * Set just the physical address. This usually used to record the
557 * result of a translation. However, when using virtualized CPUs
558 * setPhys() is sometimes called to finalize a physical address
559 * without a virtual address, so we can't check if the virtual
566 privateFlags.set(VALID_PADDR);
570 * Generate two requests as if this request had been split into two
571 * pieces. The original request can't have been translated already.
573 // TODO: this function is still required by TimingSimpleCPU - should be
574 // removed once TimingSimpleCPU will support arbitrarily long multi-line
576 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
578 assert(privateFlags.isSet(VALID_VADDR));
579 assert(privateFlags.noneSet(VALID_PADDR));
580 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
581 req1 = std::make_shared<Request>(*this);
582 req2 = std::make_shared<Request>(*this);
583 req1->_size = split_addr - _vaddr;
584 req2->_vaddr = split_addr;
585 req2->_size = _size - req1->_size;
586 if (!_byteEnable.empty()) {
587 req1->_byteEnable = std::vector<bool>(
589 _byteEnable.begin() + req1->_size);
590 req2->_byteEnable = std::vector<bool>(
591 _byteEnable.begin() + req1->_size,
597 * Accessor for paddr.
602 return privateFlags.isSet(VALID_PADDR);
608 assert(privateFlags.isSet(VALID_PADDR));
613 * Time for the TLB/table walker to successfully translate this request.
618 * Access latency to complete this memory transaction not including
624 * Level of the cache hierachy where this request was responded to
625 * (e.g. 0 = L1; 1 = L2).
635 return privateFlags.isSet(VALID_SIZE);
641 assert(privateFlags.isSet(VALID_SIZE));
645 const std::vector<bool>&
646 getByteEnable() const
652 setByteEnable(const std::vector<bool>& be)
654 assert(be.empty() || be.size() == _size);
658 /** Accessor for time. */
662 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
667 * Accessor for atomic-op functor.
672 return atomicOpFunctor != NULL;
678 assert(atomicOpFunctor != NULL);
679 return atomicOpFunctor;
682 /** Accessor for flags. */
686 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
690 /** Note that unlike other accessors, this function sets *specific
691 flags* (ORs them in); it does not assign its argument to the
692 _flags field. Thus this method should rightly be called
693 setFlags() and not just flags(). */
695 setFlags(Flags flags)
697 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
702 setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
704 assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
705 _memSpaceConfigFlags.set(extraFlags);
708 /** Accessor function for vaddr.*/
712 return privateFlags.isSet(VALID_VADDR);
718 assert(privateFlags.isSet(VALID_VADDR));
722 /** Accesssor for the requestor id. */
736 taskId(uint32_t id) {
740 /** Accessor function for asid.*/
744 assert(privateFlags.isSet(VALID_VADDR));
748 /** Accessor function for asid.*/
750 setAsid(uint64_t asid)
755 /** Accessor function for architecture-specific flags.*/
759 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
760 return _flags & ARCH_BITS;
763 /** Accessor function to check if sc result is valid. */
765 extraDataValid() const
767 return privateFlags.isSet(VALID_EXTRA_DATA);
770 /** Accessor function for store conditional return value.*/
774 assert(privateFlags.isSet(VALID_EXTRA_DATA));
778 /** Accessor function for store conditional return value.*/
780 setExtraData(uint64_t extraData)
782 _extraData = extraData;
783 privateFlags.set(VALID_EXTRA_DATA);
789 return privateFlags.isSet(VALID_CONTEXT_ID);
792 /** Accessor function for context ID.*/
796 assert(privateFlags.isSet(VALID_CONTEXT_ID));
803 assert(privateFlags.isSet(VALID_STREAM_ID));
808 hasSubstreamId() const
810 return privateFlags.isSet(VALID_SUBSTREAM_ID);
816 assert(privateFlags.isSet(VALID_SUBSTREAM_ID));
823 privateFlags.set(VALID_PC);
830 return privateFlags.isSet(VALID_PC);
833 /** Accessor function for pc.*/
837 assert(privateFlags.isSet(VALID_PC));
842 * Increment/Get the depth at which this request is responded to.
843 * This currently happens when the request misses in any cache level.
845 void incAccessDepth() const { depth++; }
846 int getAccessDepth() const { return depth; }
849 * Set/Get the time taken for this request to be successfully translated.
851 void setTranslateLatency() { translateDelta = curTick() - _time; }
852 Tick getTranslateLatency() const { return translateDelta; }
855 * Set/Get the time taken to complete this request's access, not including
856 * the time to successfully translate the request.
858 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
859 Tick getAccessLatency() const { return accessDelta; }
862 * Accessor for the sequence number of instruction that creates the
866 hasInstSeqNum() const
868 return privateFlags.isSet(VALID_INST_SEQ_NUM);
872 getReqInstSeqNum() const
874 assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
875 return _reqInstSeqNum;
879 setReqInstSeqNum(const InstSeqNum seq_num)
881 privateFlags.set(VALID_INST_SEQ_NUM);
882 _reqInstSeqNum = seq_num;
885 /** Accessor functions for flags. Note that these are for testing
886 only; setting flags should be done via setFlags(). */
887 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
888 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
889 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
890 bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
891 _flags.isSet(PF_EXCLUSIVE)); }
892 bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
893 bool isLLSC() const { return _flags.isSet(LLSC); }
894 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
895 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
896 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
897 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
898 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
899 bool isSecure() const { return _flags.isSet(SECURE); }
900 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
901 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
902 bool isRelease() const { return _flags.isSet(RELEASE); }
903 bool isKernel() const { return _flags.isSet(KERNEL); }
904 bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
905 bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
910 return _flags.isSet(ATOMIC_RETURN_OP) ||
911 _flags.isSet(ATOMIC_NO_RETURN_OP);
915 * Accessor functions for the destination of a memory request. The
916 * destination flag can specify a point of reference for the
917 * operation (e.g. a cache block clean to the the point of
918 * unification). At the moment the destination is only used by the
919 * cache maintenance operations.
921 bool isToPOU() const { return _flags.isSet(DST_POU); }
922 bool isToPOC() const { return _flags.isSet(DST_POC); }
923 Flags getDest() const { return _flags & DST_BITS; }
926 * Accessor functions for the memory space configuration flags and used by
927 * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
928 * these are for testing only; setting extraFlags should be done via
929 * setMemSpaceConfigFlags().
931 bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
934 isWavefrontScope() const
937 return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
941 isWorkgroupScope() const
944 return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
948 isDeviceScope() const
951 return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
955 isSystemScope() const
958 return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
962 isGlobalSegment() const
964 return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
965 (!isGroupSegment() && !isPrivateSegment() &&
966 !isKernargSegment() && !isReadonlySegment() &&
967 !isSpillSegment() && !isArgSegment());
971 isGroupSegment() const
973 return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
977 isPrivateSegment() const
979 return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
983 isKernargSegment() const
985 return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
989 isReadonlySegment() const
991 return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
995 isSpillSegment() const
997 return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
1001 isArgSegment() const
1003 return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
1007 * Accessor functions to determine whether this request is part of
1008 * a cache maintenance operation. At the moment three operations
1011 * 1) A cache clean operation updates all copies of a memory
1012 * location to the point of reference,
1013 * 2) A cache invalidate operation invalidates all copies of the
1014 * specified block in the memory above the point of reference,
1015 * 3) A clean and invalidate operation is a combination of the two
1018 bool isCacheClean() const { return _flags.isSet(CLEAN); }
1019 bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
1020 bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
1024 #endif // __MEM_REQUEST_HH__