src/mem/request.hh

   1 /*
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  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
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  40  */
  41
  42 /**
  43  * @file
  44  * Declaration of a request, the overall memory request consisting of
  45  the parts of the request that are persistent throughout the transaction.
  46  */
  47
  48 #ifndef __MEM_REQUEST_HH__
  49 #define __MEM_REQUEST_HH__
  50
  51 #include <cassert>
  52 #include <climits>
  53
  54 #include "base/amo.hh"
  55 #include "base/flags.hh"
  56 #include "base/logging.hh"
  57 #include "base/types.hh"
  58 #include "cpu/inst_seq.hh"
  59 #include "sim/core.hh"
  60
  61 /**
  62  * Special TaskIds that are used for per-context-switch stats dumps
  63  * and Cache Occupancy. Having too many tasks seems to be a problem
  64  * with vector stats. 1024 seems to be a reasonable number that
  65  * doesn't cause a problem with stats and is large enough to realistic
  66  * benchmarks (Linux/Android boot, BBench, etc.)
  67  */
  68
  69 namespace ContextSwitchTaskId {
  70     enum TaskId {
  71         MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
  72         Prefetcher = 1022, /* For cache lines brought in by prefetcher */
  73         DMA = 1023, /* Mostly Table Walker */
  74         Unknown = 1024,
  75         NumTaskId
  76     };
  77 }
  78
  79 class Packet;
  80 class Request;
  81 class ThreadContext;
  82
  83 typedef std::shared_ptr<Request> RequestPtr;
  84 typedef uint16_t MasterID;
  85
  86 class Request
  87 {
  88   public:
  89     typedef uint64_t FlagsType;
  90     typedef uint8_t ArchFlagsType;
  91     typedef ::Flags<FlagsType> Flags;
  92
  93     enum : FlagsType {
  94         /**
  95          * Architecture specific flags.
  96          *
  97          * These bits int the flag field are reserved for
  98          * architecture-specific code. For example, SPARC uses them to
  99          * represent ASIs.
 100          */
 101         ARCH_BITS                   = 0x000000FF,
 102         /** The request was an instruction fetch. */
 103         INST_FETCH                  = 0x00000100,
 104         /** The virtual address is also the physical address. */
 105         PHYSICAL                    = 0x00000200,
 106         /**
 107          * The request is to an uncacheable address.
 108          *
 109          * @note Uncacheable accesses may be reordered by CPU models. The
 110          * STRICT_ORDER flag should be set if such reordering is
 111          * undesirable.
 112          */
 113         UNCACHEABLE                 = 0x00000400,
 114         /**
 115          * The request is required to be strictly ordered by <i>CPU
 116          * models</i> and is non-speculative.
 117          *
 118          * A strictly ordered request is guaranteed to never be
 119          * re-ordered or executed speculatively by a CPU model. The
 120          * memory system may still reorder requests in caches unless
 121          * the UNCACHEABLE flag is set as well.
 122          */
 123         STRICT_ORDER                = 0x00000800,
 124         /** This request is made in privileged mode. */
 125         PRIVILEGED                  = 0x00008000,
 126
 127         /**
 128          * This is a write that is targeted and zeroing an entire
 129          * cache block.  There is no need for a read/modify/write
 130          */
 131         CACHE_BLOCK_ZERO            = 0x00010000,
 132
 133         /** The request should not cause a memory access. */
 134         NO_ACCESS                   = 0x00080000,
 135         /**
 136          * This request will lock or unlock the accessed memory. When
 137          * used with a load, the access locks the particular chunk of
 138          * memory. When used with a store, it unlocks. The rule is
 139          * that locked accesses have to be made up of a locked load,
 140          * some operation on the data, and then a locked store.
 141          */
 142         LOCKED_RMW                  = 0x00100000,
 143         /** The request is a Load locked/store conditional. */
 144         LLSC                        = 0x00200000,
 145         /** This request is for a memory swap. */
 146         MEM_SWAP                    = 0x00400000,
 147         MEM_SWAP_COND               = 0x00800000,
 148
 149         /** The request is a prefetch. */
 150         PREFETCH                    = 0x01000000,
 151         /** The request should be prefetched into the exclusive state. */
 152         PF_EXCLUSIVE                = 0x02000000,
 153         /** The request should be marked as LRU. */
 154         EVICT_NEXT                  = 0x04000000,
 155         /** The request should be marked with ACQUIRE. */
 156         ACQUIRE                     = 0x00020000,
 157         /** The request should be marked with RELEASE. */
 158         RELEASE                     = 0x00040000,
 159
 160         /** The request is an atomic that returns data. */
 161         ATOMIC_RETURN_OP            = 0x40000000,
 162         /** The request is an atomic that does not return data. */
 163         ATOMIC_NO_RETURN_OP         = 0x80000000,
 164
 165         /** The request should be marked with KERNEL.
 166           * Used to indicate the synchronization associated with a GPU kernel
 167           * launch or completion.
 168           */
 169         KERNEL                      = 0x00001000,
 170
 171         /** The request targets the secure memory space. */
 172         SECURE                      = 0x10000000,
 173         /** The request is a page table walk */
 174         PT_WALK                     = 0x20000000,
 175
 176         /** The request invalidates a memory location */
 177         INVALIDATE                  = 0x0000000100000000,
 178         /** The request cleans a memory location */
 179         CLEAN                       = 0x0000000200000000,
 180
 181         /** The request targets the point of unification */
 182         DST_POU                     = 0x0000001000000000,
 183
 184         /** The request targets the point of coherence */
 185         DST_POC                     = 0x0000002000000000,
 186
 187         /** Bits to define the destination of a request */
 188         DST_BITS                    = 0x0000003000000000,
 189
 190         /**
 191          * These flags are *not* cleared when a Request object is
 192          * reused (assigned a new address).
 193          */
 194         STICKY_FLAGS = INST_FETCH
 195     };
 196     static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
 197         CLEAN | INVALIDATE;
 198
 199     /** Master Ids that are statically allocated
 200      * @{*/
 201     enum : MasterID {
 202         /** This master id is used for writeback requests by the caches */
 203         wbMasterId = 0,
 204         /**
 205          * This master id is used for functional requests that
 206          * don't come from a particular device
 207          */
 208         funcMasterId = 1,
 209         /** This master id is used for message signaled interrupts */
 210         intMasterId = 2,
 211         /**
 212          * Invalid master id for assertion checking only. It is
 213          * invalid behavior to ever send this id as part of a request.
 214          */
 215         invldMasterId = std::numeric_limits<MasterID>::max()
 216     };
 217     /** @} */
 218
 219     typedef uint64_t CacheCoherenceFlagsType;
 220     typedef ::Flags<CacheCoherenceFlagsType> CacheCoherenceFlags;
 221
 222     /**
 223      * These bits are used to set the coherence policy
 224      * for the GPU and are encoded in the GCN3 instructions.
 225      * See the AMD GCN3 ISA Architecture Manual for more
 226      * details.
 227      *
 228      * INV_L1: L1 cache invalidation
 229      * WB_L2: L2 cache writeback
 230      *
 231      * SLC: System Level Coherent. Accesses are forced to miss in
 232      *      the L2 cache and are coherent with system memory.
 233      *
 234      * GLC: Globally Coherent. Controls how reads and writes are
 235      *      handled by the L1 cache. Global here referes to the
 236      *      data being visible globally on the GPU (i.e., visible
 237      *      to all WGs).
 238      *
 239      * For atomics, the GLC bit is used to distinguish between
 240      * between atomic return/no-return operations.
 241      */
 242     enum : CacheCoherenceFlagsType {
 243         /** mem_sync_op flags */
 244         INV_L1                  = 0x00000001,
 245         WB_L2                   = 0x00000020,
 246         /** user-policy flags */
 247         /** user-policy flags */
 248         SLC_BIT                 = 0x00000080,
 249         GLC_BIT                 = 0x00000100,
 250     };
 251
 252     using LocalAccessor =
 253         std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
 254
 255   private:
 256     typedef uint16_t PrivateFlagsType;
 257     typedef ::Flags<PrivateFlagsType> PrivateFlags;
 258
 259     enum : PrivateFlagsType {
 260         /** Whether or not the size is valid. */
 261         VALID_SIZE           = 0x00000001,
 262         /** Whether or not paddr is valid (has been written yet). */
 263         VALID_PADDR          = 0x00000002,
 264         /** Whether or not the vaddr is valid. */
 265         VALID_VADDR          = 0x00000004,
 266         /** Whether or not the instruction sequence number is valid. */
 267         VALID_INST_SEQ_NUM   = 0x00000008,
 268         /** Whether or not the pc is valid. */
 269         VALID_PC             = 0x00000010,
 270         /** Whether or not the context ID is valid. */
 271         VALID_CONTEXT_ID     = 0x00000020,
 272         /** Whether or not the sc result is valid. */
 273         VALID_EXTRA_DATA     = 0x00000080,
 274         /** Whether or not the stream ID and substream ID is valid. */
 275         VALID_STREAM_ID      = 0x00000100,
 276         VALID_SUBSTREAM_ID   = 0x00000200,
 277         /**
 278          * These flags are *not* cleared when a Request object is reused
 279          * (assigned a new address).
 280          */
 281         STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
 282     };
 283
 284   private:
 285
 286     /**
 287      * The physical address of the request. Valid only if validPaddr
 288      * is set.
 289      */
 290     Addr _paddr = 0;
 291
 292     /**
 293      * The size of the request. This field must be set when vaddr or
 294      * paddr is written via setVirt() or a phys basec constructor, so it is
 295      * always valid as long as one of the address fields is valid.
 296      */
 297     unsigned _size = 0;
 298
 299     /** Byte-enable mask for writes. */
 300     std::vector<bool> _byteEnable;
 301
 302     /** The requestor ID which is unique in the system for all ports
 303      * that are capable of issuing a transaction
 304      */
 305     MasterID _masterId = invldMasterId;
 306
 307     /** Flag structure for the request. */
 308     Flags _flags;
 309
 310     /** Flags that control how downstream cache system maintains coherence*/
 311     CacheCoherenceFlags _cacheCoherenceFlags;
 312
 313     /** Private flags for field validity checking. */
 314     PrivateFlags privateFlags;
 315
 316     /**
 317      * The time this request was started. Used to calculate
 318      * latencies. This field is set to curTick() any time paddr or vaddr
 319      * is written.
 320      */
 321     Tick _time = MaxTick;
 322
 323     /**
 324      * The task id associated with this request
 325      */
 326     uint32_t _taskId = ContextSwitchTaskId::Unknown;
 327
 328     /**
 329      * The stream ID uniquely identifies a device behind the
 330      * SMMU/IOMMU Each transaction arriving at the SMMU/IOMMU is
 331      * associated with exactly one stream ID.
 332      */
 333     uint32_t _streamId = 0;
 334
 335     /**
 336      * The substream ID identifies an "execution context" within a
 337      * device behind an SMMU/IOMMU. It's intended to map 1-to-1 to
 338      * PCIe PASID (Process Address Space ID). The presence of a
 339      * substream ID is optional.
 340      */
 341     uint32_t _substreamId = 0;
 342
 343     /** The virtual address of the request. */
 344     Addr _vaddr = MaxAddr;
 345
 346     /**
 347      * Extra data for the request, such as the return value of
 348      * store conditional or the compare value for a CAS. */
 349     uint64_t _extraData = 0;
 350
 351     /** The context ID (for statistics, locks, and wakeups). */
 352     ContextID _contextId = InvalidContextID;
 353
 354     /** program counter of initiating access; for tracing/debugging */
 355     Addr _pc = MaxAddr;
 356
 357     /** Sequence number of the instruction that creates the request */
 358     InstSeqNum _reqInstSeqNum = 0;
 359
 360     /** A pointer to an atomic operation */
 361     AtomicOpFunctorPtr atomicOpFunctor = nullptr;
 362
 363     LocalAccessor _localAccessor;
 364
 365   public:
 366
 367     /**
 368      * Minimal constructor. No fields are initialized. (Note that
 369      *  _flags and privateFlags are cleared by Flags default
 370      *  constructor.)
 371      */
 372     Request() {}
 373
 374     /**
 375      * Constructor for physical (e.g. device) requests.  Initializes
 376      * just physical address, size, flags, and timestamp (to curTick()).
 377      * These fields are adequate to perform a request.
 378      */
 379     Request(Addr paddr, unsigned size, Flags flags, MasterID mid) :
 380         _paddr(paddr), _size(size), _masterId(mid), _time(curTick())
 381     {
 382         _flags.set(flags);
 383         privateFlags.set(VALID_PADDR|VALID_SIZE);
 384     }
 385
 386     Request(Addr vaddr, unsigned size, Flags flags,
 387             MasterID mid, Addr pc, ContextID cid,
 388             AtomicOpFunctorPtr atomic_op=nullptr)
 389     {
 390         setVirt(vaddr, size, flags, mid, pc, std::move(atomic_op));
 391         setContext(cid);
 392     }
 393
 394     Request(const Request& other)
 395         : _paddr(other._paddr), _size(other._size),
 396           _byteEnable(other._byteEnable),
 397           _masterId(other._masterId),
 398           _flags(other._flags),
 399           _cacheCoherenceFlags(other._cacheCoherenceFlags),
 400           privateFlags(other.privateFlags),
 401           _time(other._time),
 402           _taskId(other._taskId), _vaddr(other._vaddr),
 403           _extraData(other._extraData), _contextId(other._contextId),
 404           _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
 405           _localAccessor(other._localAccessor),
 406           translateDelta(other.translateDelta),
 407           accessDelta(other.accessDelta), depth(other.depth)
 408     {
 409         atomicOpFunctor.reset(other.atomicOpFunctor ?
 410                                 other.atomicOpFunctor->clone() : nullptr);
 411     }
 412
 413     ~Request() {}
 414
 415     /**
 416      * Set up Context numbers.
 417      */
 418     void
 419     setContext(ContextID context_id)
 420     {
 421         _contextId = context_id;
 422         privateFlags.set(VALID_CONTEXT_ID);
 423     }
 424
 425     void
 426     setStreamId(uint32_t sid)
 427     {
 428         _streamId = sid;
 429         privateFlags.set(VALID_STREAM_ID);
 430     }
 431
 432     void
 433     setSubStreamId(uint32_t ssid)
 434     {
 435         assert(privateFlags.isSet(VALID_STREAM_ID));
 436         _substreamId = ssid;
 437         privateFlags.set(VALID_SUBSTREAM_ID);
 438     }
 439
 440     /**
 441      * Set up a virtual (e.g., CPU) request in a previously
 442      * allocated Request object.
 443      */
 444     void
 445     setVirt(Addr vaddr, unsigned size, Flags flags, MasterID mid, Addr pc,
 446             AtomicOpFunctorPtr amo_op=nullptr)
 447     {
 448         _vaddr = vaddr;
 449         _size = size;
 450         _masterId = mid;
 451         _pc = pc;
 452         _time = curTick();
 453
 454         _flags.clear(~STICKY_FLAGS);
 455         _flags.set(flags);
 456         privateFlags.clear(~STICKY_PRIVATE_FLAGS);
 457         privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
 458         depth = 0;
 459         accessDelta = 0;
 460         translateDelta = 0;
 461         atomicOpFunctor = std::move(amo_op);
 462         _localAccessor = nullptr;
 463     }
 464
 465     /**
 466      * Set just the physical address. This usually used to record the
 467      * result of a translation.
 468      */
 469     void
 470     setPaddr(Addr paddr)
 471     {
 472         _paddr = paddr;
 473         privateFlags.set(VALID_PADDR);
 474     }
 475
 476     /**
 477      * Generate two requests as if this request had been split into two
 478      * pieces. The original request can't have been translated already.
 479      */
 480     // TODO: this function is still required by TimingSimpleCPU - should be
 481     // removed once TimingSimpleCPU will support arbitrarily long multi-line
 482     // mem. accesses
 483     void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
 484     {
 485         assert(privateFlags.isSet(VALID_VADDR));
 486         assert(privateFlags.noneSet(VALID_PADDR));
 487         assert(split_addr > _vaddr && split_addr < _vaddr + _size);
 488         req1 = std::make_shared<Request>(*this);
 489         req2 = std::make_shared<Request>(*this);
 490         req1->_size = split_addr - _vaddr;
 491         req2->_vaddr = split_addr;
 492         req2->_size = _size - req1->_size;
 493         if (!_byteEnable.empty()) {
 494             req1->_byteEnable = std::vector<bool>(
 495                 _byteEnable.begin(),
 496                 _byteEnable.begin() + req1->_size);
 497             req2->_byteEnable = std::vector<bool>(
 498                 _byteEnable.begin() + req1->_size,
 499                 _byteEnable.end());
 500         }
 501     }
 502
 503     /**
 504      * Accessor for paddr.
 505      */
 506     bool
 507     hasPaddr() const
 508     {
 509         return privateFlags.isSet(VALID_PADDR);
 510     }
 511
 512     Addr
 513     getPaddr() const
 514     {
 515         assert(privateFlags.isSet(VALID_PADDR));
 516         return _paddr;
 517     }
 518
 519     /**
 520      * Time for the TLB/table walker to successfully translate this request.
 521      */
 522     Tick translateDelta = 0;
 523
 524     /**
 525      * Access latency to complete this memory transaction not including
 526      * translation time.
 527      */
 528     Tick accessDelta = 0;
 529
 530     /**
 531      * Level of the cache hierachy where this request was responded to
 532      * (e.g. 0 = L1; 1 = L2).
 533      */
 534     mutable int depth = 0;
 535
 536     /**
 537      *  Accessor for size.
 538      */
 539     bool
 540     hasSize() const
 541     {
 542         return privateFlags.isSet(VALID_SIZE);
 543     }
 544
 545     unsigned
 546     getSize() const
 547     {
 548         assert(privateFlags.isSet(VALID_SIZE));
 549         return _size;
 550     }
 551
 552     const std::vector<bool>&
 553     getByteEnable() const
 554     {
 555         return _byteEnable;
 556     }
 557
 558     void
 559     setByteEnable(const std::vector<bool>& be)
 560     {
 561         assert(be.empty() || be.size() == _size);
 562         _byteEnable = be;
 563     }
 564
 565     /**
 566      * Returns true if the memory request is masked, which means
 567      * there is at least one byteEnable element which is false
 568      * (byte is masked)
 569      */
 570     bool
 571     isMasked() const
 572     {
 573         return std::find(
 574             _byteEnable.begin(),
 575             _byteEnable.end(),
 576             false) != _byteEnable.end();
 577     }
 578
 579     /** Accessor for time. */
 580     Tick
 581     time() const
 582     {
 583         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 584         return _time;
 585     }
 586
 587     /** Is this request for a local memory mapped resource/register? */
 588     bool isLocalAccess() { return (bool)_localAccessor; }
 589     /** Set the function which will enact that access. */
 590     void setLocalAccessor(LocalAccessor acc) { _localAccessor = acc; }
 591     /** Perform the installed local access. */
 592     Cycles
 593     localAccessor(ThreadContext *tc, Packet *pkt)
 594     {
 595         return _localAccessor(tc, pkt);
 596     }
 597
 598     /**
 599      * Accessor for atomic-op functor.
 600      */
 601     bool
 602     hasAtomicOpFunctor()
 603     {
 604         return (bool)atomicOpFunctor;
 605     }
 606
 607     AtomicOpFunctor *
 608     getAtomicOpFunctor()
 609     {
 610         assert(atomicOpFunctor);
 611         return atomicOpFunctor.get();
 612     }
 613
 614     /** Accessor for flags. */
 615     Flags
 616     getFlags()
 617     {
 618         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 619         return _flags;
 620     }
 621
 622     /** Note that unlike other accessors, this function sets *specific
 623         flags* (ORs them in); it does not assign its argument to the
 624         _flags field.  Thus this method should rightly be called
 625         setFlags() and not just flags(). */
 626     void
 627     setFlags(Flags flags)
 628     {
 629         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 630         _flags.set(flags);
 631     }
 632
 633     void
 634     setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
 635     {
 636         // TODO: do mem_sync_op requests have valid paddr/vaddr?
 637         assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
 638         _cacheCoherenceFlags.set(extraFlags);
 639     }
 640
 641     /** Accessor function for vaddr.*/
 642     bool
 643     hasVaddr() const
 644     {
 645         return privateFlags.isSet(VALID_VADDR);
 646     }
 647
 648     Addr
 649     getVaddr() const
 650     {
 651         assert(privateFlags.isSet(VALID_VADDR));
 652         return _vaddr;
 653     }
 654
 655     /** Accesssor for the requestor id. */
 656     MasterID
 657     masterId() const
 658     {
 659         return _masterId;
 660     }
 661
 662     uint32_t
 663     taskId() const
 664     {
 665         return _taskId;
 666     }
 667
 668     void
 669     taskId(uint32_t id) {
 670         _taskId = id;
 671     }
 672
 673     /** Accessor function for architecture-specific flags.*/
 674     ArchFlagsType
 675     getArchFlags() const
 676     {
 677         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 678         return _flags & ARCH_BITS;
 679     }
 680
 681     /** Accessor function to check if sc result is valid. */
 682     bool
 683     extraDataValid() const
 684     {
 685         return privateFlags.isSet(VALID_EXTRA_DATA);
 686     }
 687
 688     /** Accessor function for store conditional return value.*/
 689     uint64_t
 690     getExtraData() const
 691     {
 692         assert(privateFlags.isSet(VALID_EXTRA_DATA));
 693         return _extraData;
 694     }
 695
 696     /** Accessor function for store conditional return value.*/
 697     void
 698     setExtraData(uint64_t extraData)
 699     {
 700         _extraData = extraData;
 701         privateFlags.set(VALID_EXTRA_DATA);
 702     }
 703
 704     bool
 705     hasContextId() const
 706     {
 707         return privateFlags.isSet(VALID_CONTEXT_ID);
 708     }
 709
 710     /** Accessor function for context ID.*/
 711     ContextID
 712     contextId() const
 713     {
 714         assert(privateFlags.isSet(VALID_CONTEXT_ID));
 715         return _contextId;
 716     }
 717
 718     uint32_t
 719     streamId() const
 720     {
 721         assert(privateFlags.isSet(VALID_STREAM_ID));
 722         return _streamId;
 723     }
 724
 725     bool
 726     hasSubstreamId() const
 727     {
 728         return privateFlags.isSet(VALID_SUBSTREAM_ID);
 729     }
 730
 731     uint32_t
 732     substreamId() const
 733     {
 734         assert(privateFlags.isSet(VALID_SUBSTREAM_ID));
 735         return _substreamId;
 736     }
 737
 738     void
 739     setPC(Addr pc)
 740     {
 741         privateFlags.set(VALID_PC);
 742         _pc = pc;
 743     }
 744
 745     bool
 746     hasPC() const
 747     {
 748         return privateFlags.isSet(VALID_PC);
 749     }
 750
 751     /** Accessor function for pc.*/
 752     Addr
 753     getPC() const
 754     {
 755         assert(privateFlags.isSet(VALID_PC));
 756         return _pc;
 757     }
 758
 759     /**
 760      * Increment/Get the depth at which this request is responded to.
 761      * This currently happens when the request misses in any cache level.
 762      */
 763     void incAccessDepth() const { depth++; }
 764     int getAccessDepth() const { return depth; }
 765
 766     /**
 767      * Set/Get the time taken for this request to be successfully translated.
 768      */
 769     void setTranslateLatency() { translateDelta = curTick() - _time; }
 770     Tick getTranslateLatency() const { return translateDelta; }
 771
 772     /**
 773      * Set/Get the time taken to complete this request's access, not including
 774      *  the time to successfully translate the request.
 775      */
 776     void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
 777     Tick getAccessLatency() const { return accessDelta; }
 778
 779     /**
 780      * Accessor for the sequence number of instruction that creates the
 781      * request.
 782      */
 783     bool
 784     hasInstSeqNum() const
 785     {
 786         return privateFlags.isSet(VALID_INST_SEQ_NUM);
 787     }
 788
 789     InstSeqNum
 790     getReqInstSeqNum() const
 791     {
 792         assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
 793         return _reqInstSeqNum;
 794     }
 795
 796     void
 797     setReqInstSeqNum(const InstSeqNum seq_num)
 798     {
 799         privateFlags.set(VALID_INST_SEQ_NUM);
 800         _reqInstSeqNum = seq_num;
 801     }
 802
 803     /** Accessor functions for flags. Note that these are for testing
 804         only; setting flags should be done via setFlags(). */
 805     bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
 806     bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
 807     bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
 808     bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
 809                                       _flags.isSet(PF_EXCLUSIVE)); }
 810     bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
 811     bool isLLSC() const { return _flags.isSet(LLSC); }
 812     bool isPriv() const { return _flags.isSet(PRIVILEGED); }
 813     bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
 814     bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
 815     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
 816     bool isSecure() const { return _flags.isSet(SECURE); }
 817     bool isPTWalk() const { return _flags.isSet(PT_WALK); }
 818     bool isAcquire() const { return _flags.isSet(ACQUIRE); }
 819     bool isRelease() const { return _flags.isSet(RELEASE); }
 820     bool isKernel() const { return _flags.isSet(KERNEL); }
 821     bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
 822     bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
 823
 824     bool
 825     isAtomic() const
 826     {
 827         return _flags.isSet(ATOMIC_RETURN_OP) ||
 828                _flags.isSet(ATOMIC_NO_RETURN_OP);
 829     }
 830
 831     /**
 832      * Accessor functions for the destination of a memory request. The
 833      * destination flag can specify a point of reference for the
 834      * operation (e.g. a cache block clean to the the point of
 835      * unification). At the moment the destination is only used by the
 836      * cache maintenance operations.
 837      */
 838     bool isToPOU() const { return _flags.isSet(DST_POU); }
 839     bool isToPOC() const { return _flags.isSet(DST_POC); }
 840     Flags getDest() const { return _flags & DST_BITS; }
 841
 842     /**
 843      * Accessor functions for the memory space configuration flags and used by
 844      * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
 845      * these are for testing only; setting extraFlags should be done via
 846      * setCacheCoherenceFlags().
 847      */
 848     bool isSLC() const { return _cacheCoherenceFlags.isSet(SLC_BIT); }
 849     bool isGLC() const { return _cacheCoherenceFlags.isSet(GLC_BIT); }
 850
 851     /**
 852      * Accessor functions to determine whether this request is part of
 853      * a cache maintenance operation. At the moment three operations
 854      * are supported:
 855
 856      * 1) A cache clean operation updates all copies of a memory
 857      * location to the point of reference,
 858      * 2) A cache invalidate operation invalidates all copies of the
 859      * specified block in the memory above the point of reference,
 860      * 3) A clean and invalidate operation is a combination of the two
 861      * operations.
 862      * @{ */
 863     bool isCacheClean() const { return _flags.isSet(CLEAN); }
 864     bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
 865     bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
 866     /** @} */
 867 };
 868
 869 #endif // __MEM_REQUEST_HH__