src/mem/request.hh

   1 /*
   2  * Copyright (c) 2012-2013,2017-2020 ARM Limited
   3  * All rights reserved
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   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
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  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
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  27  * this software without specific prior written permission.
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 /**
  43  * @file
  44  * Declaration of a request, the overall memory request consisting of
  45  the parts of the request that are persistent throughout the transaction.
  46  */
  47
  48 #ifndef __MEM_REQUEST_HH__
  49 #define __MEM_REQUEST_HH__
  50
  51 #include <cassert>
  52 #include <climits>
  53
  54 #include "base/amo.hh"
  55 #include "base/flags.hh"
  56 #include "base/logging.hh"
  57 #include "base/types.hh"
  58 #include "cpu/inst_seq.hh"
  59 #include "mem/htm.hh"
  60 #include "sim/core.hh"
  61
  62 /**
  63  * Special TaskIds that are used for per-context-switch stats dumps
  64  * and Cache Occupancy. Having too many tasks seems to be a problem
  65  * with vector stats. 1024 seems to be a reasonable number that
  66  * doesn't cause a problem with stats and is large enough to realistic
  67  * benchmarks (Linux/Android boot, BBench, etc.)
  68  */
  69
  70 namespace ContextSwitchTaskId {
  71     enum TaskId {
  72         MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
  73         Prefetcher = 1022, /* For cache lines brought in by prefetcher */
  74         DMA = 1023, /* Mostly Table Walker */
  75         Unknown = 1024,
  76         NumTaskId
  77     };
  78 }
  79
  80 class Packet;
  81 class Request;
  82 class ThreadContext;
  83
  84 typedef std::shared_ptr<Request> RequestPtr;
  85 typedef uint16_t RequestorID;
  86
  87 class Request
  88 {
  89   public:
  90     typedef uint64_t FlagsType;
  91     typedef uint8_t ArchFlagsType;
  92     typedef ::Flags<FlagsType> Flags;
  93
  94     enum : FlagsType {
  95         /**
  96          * Architecture specific flags.
  97          *
  98          * These bits int the flag field are reserved for
  99          * architecture-specific code. For example, SPARC uses them to
 100          * represent ASIs.
 101          */
 102         ARCH_BITS                   = 0x000000FF,
 103         /** The request was an instruction fetch. */
 104         INST_FETCH                  = 0x00000100,
 105         /** The virtual address is also the physical address. */
 106         PHYSICAL                    = 0x00000200,
 107         /**
 108          * The request is to an uncacheable address.
 109          *
 110          * @note Uncacheable accesses may be reordered by CPU models. The
 111          * STRICT_ORDER flag should be set if such reordering is
 112          * undesirable.
 113          */
 114         UNCACHEABLE                 = 0x00000400,
 115         /**
 116          * The request is required to be strictly ordered by <i>CPU
 117          * models</i> and is non-speculative.
 118          *
 119          * A strictly ordered request is guaranteed to never be
 120          * re-ordered or executed speculatively by a CPU model. The
 121          * memory system may still reorder requests in caches unless
 122          * the UNCACHEABLE flag is set as well.
 123          */
 124         STRICT_ORDER                = 0x00000800,
 125         /** This request is made in privileged mode. */
 126         PRIVILEGED                  = 0x00008000,
 127
 128         /**
 129          * This is a write that is targeted and zeroing an entire
 130          * cache block.  There is no need for a read/modify/write
 131          */
 132         CACHE_BLOCK_ZERO            = 0x00010000,
 133
 134         /** The request should not cause a memory access. */
 135         NO_ACCESS                   = 0x00080000,
 136         /**
 137          * This request will lock or unlock the accessed memory. When
 138          * used with a load, the access locks the particular chunk of
 139          * memory. When used with a store, it unlocks. The rule is
 140          * that locked accesses have to be made up of a locked load,
 141          * some operation on the data, and then a locked store.
 142          */
 143         LOCKED_RMW                  = 0x00100000,
 144         /** The request is a Load locked/store conditional. */
 145         LLSC                        = 0x00200000,
 146         /** This request is for a memory swap. */
 147         MEM_SWAP                    = 0x00400000,
 148         MEM_SWAP_COND               = 0x00800000,
 149
 150         /** The request is a prefetch. */
 151         PREFETCH                    = 0x01000000,
 152         /** The request should be prefetched into the exclusive state. */
 153         PF_EXCLUSIVE                = 0x02000000,
 154         /** The request should be marked as LRU. */
 155         EVICT_NEXT                  = 0x04000000,
 156         /** The request should be marked with ACQUIRE. */
 157         ACQUIRE                     = 0x00020000,
 158         /** The request should be marked with RELEASE. */
 159         RELEASE                     = 0x00040000,
 160
 161         /** The request is an atomic that returns data. */
 162         ATOMIC_RETURN_OP            = 0x40000000,
 163         /** The request is an atomic that does not return data. */
 164         ATOMIC_NO_RETURN_OP         = 0x80000000,
 165
 166         /** The request should be marked with KERNEL.
 167           * Used to indicate the synchronization associated with a GPU kernel
 168           * launch or completion.
 169           */
 170         KERNEL                      = 0x00001000,
 171
 172         /** The request targets the secure memory space. */
 173         SECURE                      = 0x10000000,
 174         /** The request is a page table walk */
 175         PT_WALK                     = 0x20000000,
 176
 177         /** The request invalidates a memory location */
 178         INVALIDATE                  = 0x0000000100000000,
 179         /** The request cleans a memory location */
 180         CLEAN                       = 0x0000000200000000,
 181
 182         /** The request targets the point of unification */
 183         DST_POU                     = 0x0000001000000000,
 184
 185         /** The request targets the point of coherence */
 186         DST_POC                     = 0x0000002000000000,
 187
 188         /** Bits to define the destination of a request */
 189         DST_BITS                    = 0x0000003000000000,
 190
 191         /** hardware transactional memory **/
 192
 193         /** The request starts a HTM transaction */
 194         HTM_START                   = 0x0000010000000000,
 195
 196         /** The request commits a HTM transaction */
 197         HTM_COMMIT                  = 0x0000020000000000,
 198
 199         /** The request cancels a HTM transaction */
 200         HTM_CANCEL                  = 0x0000040000000000,
 201
 202         /** The request aborts a HTM transaction */
 203         HTM_ABORT                   = 0x0000080000000000,
 204
 205         // What is the different between HTM cancel and abort?
 206         //
 207         // HTM_CANCEL will originate from a user instruction, e.g.
 208         // Arm's TCANCEL or x86's XABORT. This is an explicit request
 209         // to end a transaction and restore from the last checkpoint.
 210         //
 211         // HTM_ABORT is an internally generated request used to synchronize
 212         // a transaction's failure between the core and memory subsystem.
 213         // If a transaction fails in the core, e.g. because an instruction
 214         // within the transaction generates an exception, the core will prepare
 215         // itself to stop fetching/executing more instructions and send an
 216         // HTM_ABORT to the memory subsystem before restoring the checkpoint.
 217         // Similarly, the transaction could fail in the memory subsystem and
 218         // this will be communicated to the core via the Packet object.
 219         // Once the core notices, it will do the same as the above and send
 220         // a HTM_ABORT to the memory subsystem.
 221         // A HTM_CANCEL sent to the memory subsystem will ultimately return
 222         // to the core which in turn will send a HTM_ABORT.
 223         //
 224         // This separation is necessary to ensure the disjoint components
 225         // of the system work correctly together.
 226
 227         /**
 228          * These flags are *not* cleared when a Request object is
 229          * reused (assigned a new address).
 230          */
 231         STICKY_FLAGS = INST_FETCH
 232     };
 233     static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
 234         CLEAN | INVALIDATE;
 235
 236     static const FlagsType HTM_CMD = HTM_START | HTM_COMMIT |
 237         HTM_CANCEL | HTM_ABORT;
 238
 239     /** Requestor Ids that are statically allocated
 240      * @{*/
 241     enum : RequestorID {
 242         /** This requestor id is used for writeback requests by the caches */
 243         wbRequestorId = 0,
 244         /**
 245          * This requestor id is used for functional requests that
 246          * don't come from a particular device
 247          */
 248         funcRequestorId = 1,
 249         /** This requestor id is used for message signaled interrupts */
 250         intRequestorId = 2,
 251         /**
 252          * Invalid requestor id for assertion checking only. It is
 253          * invalid behavior to ever send this id as part of a request.
 254          */
 255         invldRequestorId = std::numeric_limits<RequestorID>::max()
 256     };
 257     /** @} */
 258
 259     typedef uint64_t CacheCoherenceFlagsType;
 260     typedef ::Flags<CacheCoherenceFlagsType> CacheCoherenceFlags;
 261
 262     /**
 263      * These bits are used to set the coherence policy
 264      * for the GPU and are encoded in the GCN3 instructions.
 265      * See the AMD GCN3 ISA Architecture Manual for more
 266      * details.
 267      *
 268      * INV_L1: L1 cache invalidation
 269      * WB_L2: L2 cache writeback
 270      *
 271      * SLC: System Level Coherent. Accesses are forced to miss in
 272      *      the L2 cache and are coherent with system memory.
 273      *
 274      * GLC: Globally Coherent. Controls how reads and writes are
 275      *      handled by the L1 cache. Global here referes to the
 276      *      data being visible globally on the GPU (i.e., visible
 277      *      to all WGs).
 278      *
 279      * For atomics, the GLC bit is used to distinguish between
 280      * between atomic return/no-return operations.
 281      */
 282     enum : CacheCoherenceFlagsType {
 283         /** mem_sync_op flags */
 284         INV_L1                  = 0x00000001,
 285         WB_L2                   = 0x00000020,
 286         /** user-policy flags */
 287         /** user-policy flags */
 288         SLC_BIT                 = 0x00000080,
 289         GLC_BIT                 = 0x00000100,
 290     };
 291
 292     using LocalAccessor =
 293         std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
 294
 295   private:
 296     typedef uint16_t PrivateFlagsType;
 297     typedef ::Flags<PrivateFlagsType> PrivateFlags;
 298
 299     enum : PrivateFlagsType {
 300         /** Whether or not the size is valid. */
 301         VALID_SIZE           = 0x00000001,
 302         /** Whether or not paddr is valid (has been written yet). */
 303         VALID_PADDR          = 0x00000002,
 304         /** Whether or not the vaddr is valid. */
 305         VALID_VADDR          = 0x00000004,
 306         /** Whether or not the instruction sequence number is valid. */
 307         VALID_INST_SEQ_NUM   = 0x00000008,
 308         /** Whether or not the pc is valid. */
 309         VALID_PC             = 0x00000010,
 310         /** Whether or not the context ID is valid. */
 311         VALID_CONTEXT_ID     = 0x00000020,
 312         /** Whether or not the sc result is valid. */
 313         VALID_EXTRA_DATA     = 0x00000080,
 314         /** Whether or not the stream ID and substream ID is valid. */
 315         VALID_STREAM_ID      = 0x00000100,
 316         VALID_SUBSTREAM_ID   = 0x00000200,
 317         // hardware transactional memory
 318         /** Whether or not the abort cause is valid. */
 319         VALID_HTM_ABORT_CAUSE = 0x00000400,
 320         /** Whether or not the instruction count is valid. */
 321         VALID_INST_COUNT      = 0x00000800,
 322         /**
 323          * These flags are *not* cleared when a Request object is reused
 324          * (assigned a new address).
 325          */
 326         STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
 327     };
 328
 329   private:
 330
 331     /**
 332      * The physical address of the request. Valid only if validPaddr
 333      * is set.
 334      */
 335     Addr _paddr = 0;
 336
 337     /**
 338      * The size of the request. This field must be set when vaddr or
 339      * paddr is written via setVirt() or a phys basec constructor, so it is
 340      * always valid as long as one of the address fields is valid.
 341      */
 342     unsigned _size = 0;
 343
 344     /** Byte-enable mask for writes. */
 345     std::vector<bool> _byteEnable;
 346
 347     /** The requestor ID which is unique in the system for all ports
 348      * that are capable of issuing a transaction
 349      */
 350     RequestorID _requestorId = invldRequestorId;
 351
 352     /** Flag structure for the request. */
 353     Flags _flags;
 354
 355     /** Flags that control how downstream cache system maintains coherence*/
 356     CacheCoherenceFlags _cacheCoherenceFlags;
 357
 358     /** Private flags for field validity checking. */
 359     PrivateFlags privateFlags;
 360
 361     /**
 362      * The time this request was started. Used to calculate
 363      * latencies. This field is set to curTick() any time paddr or vaddr
 364      * is written.
 365      */
 366     Tick _time = MaxTick;
 367
 368     /**
 369      * The task id associated with this request
 370      */
 371     uint32_t _taskId = ContextSwitchTaskId::Unknown;
 372
 373     /**
 374      * The stream ID uniquely identifies a device behind the
 375      * SMMU/IOMMU Each transaction arriving at the SMMU/IOMMU is
 376      * associated with exactly one stream ID.
 377      */
 378     uint32_t _streamId = 0;
 379
 380     /**
 381      * The substream ID identifies an "execution context" within a
 382      * device behind an SMMU/IOMMU. It's intended to map 1-to-1 to
 383      * PCIe PASID (Process Address Space ID). The presence of a
 384      * substream ID is optional.
 385      */
 386     uint32_t _substreamId = 0;
 387
 388     /** The virtual address of the request. */
 389     Addr _vaddr = MaxAddr;
 390
 391     /**
 392      * Extra data for the request, such as the return value of
 393      * store conditional or the compare value for a CAS. */
 394     uint64_t _extraData = 0;
 395
 396     /** The context ID (for statistics, locks, and wakeups). */
 397     ContextID _contextId = InvalidContextID;
 398
 399     /** program counter of initiating access; for tracing/debugging */
 400     Addr _pc = MaxAddr;
 401
 402     /** Sequence number of the instruction that creates the request */
 403     InstSeqNum _reqInstSeqNum = 0;
 404
 405     /** A pointer to an atomic operation */
 406     AtomicOpFunctorPtr atomicOpFunctor = nullptr;
 407
 408     LocalAccessor _localAccessor;
 409
 410     /** The instruction count at the time this request is created */
 411     Counter _instCount = 0;
 412
 413     /** The cause for HTM transaction abort */
 414     HtmFailureFaultCause _htmAbortCause = HtmFailureFaultCause::INVALID;
 415
 416   public:
 417
 418     /**
 419      * Minimal constructor. No fields are initialized. (Note that
 420      *  _flags and privateFlags are cleared by Flags default
 421      *  constructor.)
 422      */
 423     Request() {}
 424
 425     /**
 426      * Constructor for physical (e.g. device) requests.  Initializes
 427      * just physical address, size, flags, and timestamp (to curTick()).
 428      * These fields are adequate to perform a request.
 429      */
 430     Request(Addr paddr, unsigned size, Flags flags, RequestorID id) :
 431         _paddr(paddr), _size(size), _requestorId(id), _time(curTick())
 432     {
 433         _flags.set(flags);
 434         privateFlags.set(VALID_PADDR|VALID_SIZE);
 435         _byteEnable = std::vector<bool>(size, true);
 436     }
 437
 438     Request(Addr vaddr, unsigned size, Flags flags,
 439             RequestorID id, Addr pc, ContextID cid,
 440             AtomicOpFunctorPtr atomic_op=nullptr)
 441     {
 442         setVirt(vaddr, size, flags, id, pc, std::move(atomic_op));
 443         setContext(cid);
 444         _byteEnable = std::vector<bool>(size, true);
 445     }
 446
 447     Request(const Request& other)
 448         : _paddr(other._paddr), _size(other._size),
 449           _byteEnable(other._byteEnable),
 450           _requestorId(other._requestorId),
 451           _flags(other._flags),
 452           _cacheCoherenceFlags(other._cacheCoherenceFlags),
 453           privateFlags(other.privateFlags),
 454           _time(other._time),
 455           _taskId(other._taskId), _vaddr(other._vaddr),
 456           _extraData(other._extraData), _contextId(other._contextId),
 457           _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
 458           _localAccessor(other._localAccessor),
 459           translateDelta(other.translateDelta),
 460           accessDelta(other.accessDelta), depth(other.depth)
 461     {
 462         atomicOpFunctor.reset(other.atomicOpFunctor ?
 463                                 other.atomicOpFunctor->clone() : nullptr);
 464     }
 465
 466     ~Request() {}
 467
 468     /**
 469      * Set up Context numbers.
 470      */
 471     void
 472     setContext(ContextID context_id)
 473     {
 474         _contextId = context_id;
 475         privateFlags.set(VALID_CONTEXT_ID);
 476     }
 477
 478     void
 479     setStreamId(uint32_t sid)
 480     {
 481         _streamId = sid;
 482         privateFlags.set(VALID_STREAM_ID);
 483     }
 484
 485     void
 486     setSubStreamId(uint32_t ssid)
 487     {
 488         assert(privateFlags.isSet(VALID_STREAM_ID));
 489         _substreamId = ssid;
 490         privateFlags.set(VALID_SUBSTREAM_ID);
 491     }
 492
 493     /**
 494      * Set up a virtual (e.g., CPU) request in a previously
 495      * allocated Request object.
 496      */
 497     void
 498     setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc,
 499             AtomicOpFunctorPtr amo_op=nullptr)
 500     {
 501         _vaddr = vaddr;
 502         _size = size;
 503         _requestorId = id;
 504         _pc = pc;
 505         _time = curTick();
 506
 507         _flags.clear(~STICKY_FLAGS);
 508         _flags.set(flags);
 509         privateFlags.clear(~STICKY_PRIVATE_FLAGS);
 510         privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
 511         depth = 0;
 512         accessDelta = 0;
 513         translateDelta = 0;
 514         atomicOpFunctor = std::move(amo_op);
 515         _localAccessor = nullptr;
 516     }
 517
 518     /**
 519      * Set just the physical address. This usually used to record the
 520      * result of a translation.
 521      */
 522     void
 523     setPaddr(Addr paddr)
 524     {
 525         _paddr = paddr;
 526         privateFlags.set(VALID_PADDR);
 527     }
 528
 529     /**
 530      * Generate two requests as if this request had been split into two
 531      * pieces. The original request can't have been translated already.
 532      */
 533     // TODO: this function is still required by TimingSimpleCPU - should be
 534     // removed once TimingSimpleCPU will support arbitrarily long multi-line
 535     // mem. accesses
 536     void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
 537     {
 538         assert(privateFlags.isSet(VALID_VADDR));
 539         assert(privateFlags.noneSet(VALID_PADDR));
 540         assert(split_addr > _vaddr && split_addr < _vaddr + _size);
 541         req1 = std::make_shared<Request>(*this);
 542         req2 = std::make_shared<Request>(*this);
 543         req1->_size = split_addr - _vaddr;
 544         req2->_vaddr = split_addr;
 545         req2->_size = _size - req1->_size;
 546         req1->_byteEnable = std::vector<bool>(
 547             _byteEnable.begin(),
 548             _byteEnable.begin() + req1->_size);
 549         req2->_byteEnable = std::vector<bool>(
 550             _byteEnable.begin() + req1->_size,
 551             _byteEnable.end());
 552     }
 553
 554     /**
 555      * Accessor for paddr.
 556      */
 557     bool
 558     hasPaddr() const
 559     {
 560         return privateFlags.isSet(VALID_PADDR);
 561     }
 562
 563     Addr
 564     getPaddr() const
 565     {
 566         assert(privateFlags.isSet(VALID_PADDR));
 567         return _paddr;
 568     }
 569
 570     /**
 571      * Accessor for instruction count.
 572      */
 573     Counter getInstCount() const
 574     {
 575         assert(privateFlags.isSet(VALID_INST_COUNT));
 576         return _instCount;
 577     }
 578
 579     void setInstCount(Counter val)
 580     {
 581         privateFlags.set(VALID_INST_COUNT);
 582         _instCount = val;
 583     }
 584
 585     /**
 586      * Time for the TLB/table walker to successfully translate this request.
 587      */
 588     Tick translateDelta = 0;
 589
 590     /**
 591      * Access latency to complete this memory transaction not including
 592      * translation time.
 593      */
 594     Tick accessDelta = 0;
 595
 596     /**
 597      * Level of the cache hierachy where this request was responded to
 598      * (e.g. 0 = L1; 1 = L2).
 599      */
 600     mutable int depth = 0;
 601
 602     /**
 603      *  Accessor for size.
 604      */
 605     bool
 606     hasSize() const
 607     {
 608         return privateFlags.isSet(VALID_SIZE);
 609     }
 610
 611     unsigned
 612     getSize() const
 613     {
 614         assert(privateFlags.isSet(VALID_SIZE));
 615         return _size;
 616     }
 617
 618     const std::vector<bool>&
 619     getByteEnable() const
 620     {
 621         return _byteEnable;
 622     }
 623
 624     void
 625     setByteEnable(const std::vector<bool>& be)
 626     {
 627         assert(be.size() == _size);
 628         _byteEnable = be;
 629     }
 630
 631     /**
 632      * Returns true if the memory request is masked, which means
 633      * there is at least one byteEnable element which is false
 634      * (byte is masked)
 635      */
 636     bool
 637     isMasked() const
 638     {
 639         return std::find(
 640             _byteEnable.begin(),
 641             _byteEnable.end(),
 642             false) != _byteEnable.end();
 643     }
 644
 645     /** Accessor for time. */
 646     Tick
 647     time() const
 648     {
 649         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 650         return _time;
 651     }
 652
 653     /** Is this request for a local memory mapped resource/register? */
 654     bool isLocalAccess() { return (bool)_localAccessor; }
 655     /** Set the function which will enact that access. */
 656     void setLocalAccessor(LocalAccessor acc) { _localAccessor = acc; }
 657     /** Perform the installed local access. */
 658     Cycles
 659     localAccessor(ThreadContext *tc, Packet *pkt)
 660     {
 661         return _localAccessor(tc, pkt);
 662     }
 663
 664     /**
 665      * Accessor for atomic-op functor.
 666      */
 667     bool
 668     hasAtomicOpFunctor()
 669     {
 670         return (bool)atomicOpFunctor;
 671     }
 672
 673     AtomicOpFunctor *
 674     getAtomicOpFunctor()
 675     {
 676         assert(atomicOpFunctor);
 677         return atomicOpFunctor.get();
 678     }
 679
 680     /**
 681      * Accessor for hardware transactional memory abort cause.
 682      */
 683     HtmFailureFaultCause
 684     getHtmAbortCause() const
 685     {
 686         assert(privateFlags.isSet(VALID_HTM_ABORT_CAUSE));
 687         return _htmAbortCause;
 688     }
 689
 690     void
 691     setHtmAbortCause(HtmFailureFaultCause val)
 692     {
 693         assert(isHTMAbort());
 694         privateFlags.set(VALID_HTM_ABORT_CAUSE);
 695         _htmAbortCause = val;
 696     }
 697
 698     /** Accessor for flags. */
 699     Flags
 700     getFlags()
 701     {
 702         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 703         return _flags;
 704     }
 705
 706     /** Note that unlike other accessors, this function sets *specific
 707         flags* (ORs them in); it does not assign its argument to the
 708         _flags field.  Thus this method should rightly be called
 709         setFlags() and not just flags(). */
 710     void
 711     setFlags(Flags flags)
 712     {
 713         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 714         _flags.set(flags);
 715     }
 716
 717     void
 718     setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
 719     {
 720         // TODO: do mem_sync_op requests have valid paddr/vaddr?
 721         assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
 722         _cacheCoherenceFlags.set(extraFlags);
 723     }
 724
 725     /** Accessor function for vaddr.*/
 726     bool
 727     hasVaddr() const
 728     {
 729         return privateFlags.isSet(VALID_VADDR);
 730     }
 731
 732     Addr
 733     getVaddr() const
 734     {
 735         assert(privateFlags.isSet(VALID_VADDR));
 736         return _vaddr;
 737     }
 738
 739     /** Accesssor for the requestor id. */
 740     RequestorID
 741     requestorId() const
 742     {
 743         return _requestorId;
 744     }
 745
 746     uint32_t
 747     taskId() const
 748     {
 749         return _taskId;
 750     }
 751
 752     void
 753     taskId(uint32_t id) {
 754         _taskId = id;
 755     }
 756
 757     /** Accessor function for architecture-specific flags.*/
 758     ArchFlagsType
 759     getArchFlags() const
 760     {
 761         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 762         return _flags & ARCH_BITS;
 763     }
 764
 765     /** Accessor function to check if sc result is valid. */
 766     bool
 767     extraDataValid() const
 768     {
 769         return privateFlags.isSet(VALID_EXTRA_DATA);
 770     }
 771
 772     /** Accessor function for store conditional return value.*/
 773     uint64_t
 774     getExtraData() const
 775     {
 776         assert(privateFlags.isSet(VALID_EXTRA_DATA));
 777         return _extraData;
 778     }
 779
 780     /** Accessor function for store conditional return value.*/
 781     void
 782     setExtraData(uint64_t extraData)
 783     {
 784         _extraData = extraData;
 785         privateFlags.set(VALID_EXTRA_DATA);
 786     }
 787
 788     bool
 789     hasContextId() const
 790     {
 791         return privateFlags.isSet(VALID_CONTEXT_ID);
 792     }
 793
 794     /** Accessor function for context ID.*/
 795     ContextID
 796     contextId() const
 797     {
 798         assert(privateFlags.isSet(VALID_CONTEXT_ID));
 799         return _contextId;
 800     }
 801
 802     uint32_t
 803     streamId() const
 804     {
 805         assert(privateFlags.isSet(VALID_STREAM_ID));
 806         return _streamId;
 807     }
 808
 809     bool
 810     hasSubstreamId() const
 811     {
 812         return privateFlags.isSet(VALID_SUBSTREAM_ID);
 813     }
 814
 815     uint32_t
 816     substreamId() const
 817     {
 818         assert(privateFlags.isSet(VALID_SUBSTREAM_ID));
 819         return _substreamId;
 820     }
 821
 822     void
 823     setPC(Addr pc)
 824     {
 825         privateFlags.set(VALID_PC);
 826         _pc = pc;
 827     }
 828
 829     bool
 830     hasPC() const
 831     {
 832         return privateFlags.isSet(VALID_PC);
 833     }
 834
 835     /** Accessor function for pc.*/
 836     Addr
 837     getPC() const
 838     {
 839         assert(privateFlags.isSet(VALID_PC));
 840         return _pc;
 841     }
 842
 843     /**
 844      * Increment/Get the depth at which this request is responded to.
 845      * This currently happens when the request misses in any cache level.
 846      */
 847     void incAccessDepth() const { depth++; }
 848     int getAccessDepth() const { return depth; }
 849
 850     /**
 851      * Set/Get the time taken for this request to be successfully translated.
 852      */
 853     void setTranslateLatency() { translateDelta = curTick() - _time; }
 854     Tick getTranslateLatency() const { return translateDelta; }
 855
 856     /**
 857      * Set/Get the time taken to complete this request's access, not including
 858      *  the time to successfully translate the request.
 859      */
 860     void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
 861     Tick getAccessLatency() const { return accessDelta; }
 862
 863     /**
 864      * Accessor for the sequence number of instruction that creates the
 865      * request.
 866      */
 867     bool
 868     hasInstSeqNum() const
 869     {
 870         return privateFlags.isSet(VALID_INST_SEQ_NUM);
 871     }
 872
 873     InstSeqNum
 874     getReqInstSeqNum() const
 875     {
 876         assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
 877         return _reqInstSeqNum;
 878     }
 879
 880     void
 881     setReqInstSeqNum(const InstSeqNum seq_num)
 882     {
 883         privateFlags.set(VALID_INST_SEQ_NUM);
 884         _reqInstSeqNum = seq_num;
 885     }
 886
 887     /** Accessor functions for flags. Note that these are for testing
 888         only; setting flags should be done via setFlags(). */
 889     bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
 890     bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
 891     bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
 892     bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
 893                                       _flags.isSet(PF_EXCLUSIVE)); }
 894     bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
 895     bool isLLSC() const { return _flags.isSet(LLSC); }
 896     bool isPriv() const { return _flags.isSet(PRIVILEGED); }
 897     bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
 898     bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
 899     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
 900     bool isSecure() const { return _flags.isSet(SECURE); }
 901     bool isPTWalk() const { return _flags.isSet(PT_WALK); }
 902     bool isRelease() const { return _flags.isSet(RELEASE); }
 903     bool isKernel() const { return _flags.isSet(KERNEL); }
 904     bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
 905     bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
 906     // hardware transactional memory
 907     bool isHTMStart() const { return _flags.isSet(HTM_START); }
 908     bool isHTMCommit() const { return _flags.isSet(HTM_COMMIT); }
 909     bool isHTMCancel() const { return _flags.isSet(HTM_CANCEL); }
 910     bool isHTMAbort() const { return _flags.isSet(HTM_ABORT); }
 911     bool
 912     isHTMCmd() const
 913     {
 914         return (isHTMStart() || isHTMCommit() ||
 915                 isHTMCancel() || isHTMAbort());
 916     }
 917
 918     bool
 919     isAtomic() const
 920     {
 921         return _flags.isSet(ATOMIC_RETURN_OP) ||
 922                _flags.isSet(ATOMIC_NO_RETURN_OP);
 923     }
 924
 925     /**
 926      * Accessor functions for the destination of a memory request. The
 927      * destination flag can specify a point of reference for the
 928      * operation (e.g. a cache block clean to the the point of
 929      * unification). At the moment the destination is only used by the
 930      * cache maintenance operations.
 931      */
 932     bool isToPOU() const { return _flags.isSet(DST_POU); }
 933     bool isToPOC() const { return _flags.isSet(DST_POC); }
 934     Flags getDest() const { return _flags & DST_BITS; }
 935
 936     bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
 937
 938     /**
 939      * Accessor functions for the memory space configuration flags and used by
 940      * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
 941      * these are for testing only; setting extraFlags should be done via
 942      * setCacheCoherenceFlags().
 943      */
 944     bool isSLC() const { return _cacheCoherenceFlags.isSet(SLC_BIT); }
 945     bool isGLC() const { return _cacheCoherenceFlags.isSet(GLC_BIT); }
 946
 947     /**
 948      * Accessor functions to determine whether this request is part of
 949      * a cache maintenance operation. At the moment three operations
 950      * are supported:
 951
 952      * 1) A cache clean operation updates all copies of a memory
 953      * location to the point of reference,
 954      * 2) A cache invalidate operation invalidates all copies of the
 955      * specified block in the memory above the point of reference,
 956      * 3) A clean and invalidate operation is a combination of the two
 957      * operations.
 958      * @{ */
 959     bool isCacheClean() const { return _flags.isSet(CLEAN); }
 960     bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
 961     bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
 962     /** @} */
 963 };
 964
 965 #endif // __MEM_REQUEST_HH__