src/mem/request.hh

   1 /*
   2  * Copyright (c) 2012-2013,2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 /**
  43  * @file
  44  * Declaration of a request, the overall memory request consisting of
  45  the parts of the request that are persistent throughout the transaction.
  46  */
  47
  48 #ifndef __MEM_REQUEST_HH__
  49 #define __MEM_REQUEST_HH__
  50
  51 #include <cassert>
  52 #include <climits>
  53
  54 #include "base/amo.hh"
  55 #include "base/flags.hh"
  56 #include "base/logging.hh"
  57 #include "base/types.hh"
  58 #include "cpu/inst_seq.hh"
  59 #include "sim/core.hh"
  60
  61 /**
  62  * Special TaskIds that are used for per-context-switch stats dumps
  63  * and Cache Occupancy. Having too many tasks seems to be a problem
  64  * with vector stats. 1024 seems to be a reasonable number that
  65  * doesn't cause a problem with stats and is large enough to realistic
  66  * benchmarks (Linux/Android boot, BBench, etc.)
  67  */
  68
  69 namespace ContextSwitchTaskId {
  70     enum TaskId {
  71         MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
  72         Prefetcher = 1022, /* For cache lines brought in by prefetcher */
  73         DMA = 1023, /* Mostly Table Walker */
  74         Unknown = 1024,
  75         NumTaskId
  76     };
  77 }
  78
  79 class Packet;
  80 class Request;
  81 class ThreadContext;
  82
  83 typedef std::shared_ptr<Request> RequestPtr;
  84 typedef uint16_t MasterID;
  85
  86 class Request
  87 {
  88   public:
  89     typedef uint64_t FlagsType;
  90     typedef uint8_t ArchFlagsType;
  91     typedef ::Flags<FlagsType> Flags;
  92
  93     enum : FlagsType {
  94         /**
  95          * Architecture specific flags.
  96          *
  97          * These bits int the flag field are reserved for
  98          * architecture-specific code. For example, SPARC uses them to
  99          * represent ASIs.
 100          */
 101         ARCH_BITS                   = 0x000000FF,
 102         /** The request was an instruction fetch. */
 103         INST_FETCH                  = 0x00000100,
 104         /** The virtual address is also the physical address. */
 105         PHYSICAL                    = 0x00000200,
 106         /**
 107          * The request is to an uncacheable address.
 108          *
 109          * @note Uncacheable accesses may be reordered by CPU models. The
 110          * STRICT_ORDER flag should be set if such reordering is
 111          * undesirable.
 112          */
 113         UNCACHEABLE                = 0x00000400,
 114         /**
 115          * The request is required to be strictly ordered by <i>CPU
 116          * models</i> and is non-speculative.
 117          *
 118          * A strictly ordered request is guaranteed to never be
 119          * re-ordered or executed speculatively by a CPU model. The
 120          * memory system may still reorder requests in caches unless
 121          * the UNCACHEABLE flag is set as well.
 122          */
 123         STRICT_ORDER                = 0x00000800,
 124         /** This request is made in privileged mode. */
 125         PRIVILEGED                  = 0x00008000,
 126
 127         /**
 128          * This is a write that is targeted and zeroing an entire
 129          * cache block.  There is no need for a read/modify/write
 130          */
 131         CACHE_BLOCK_ZERO            = 0x00010000,
 132
 133         /** The request should not cause a memory access. */
 134         NO_ACCESS                   = 0x00080000,
 135         /**
 136          * This request will lock or unlock the accessed memory. When
 137          * used with a load, the access locks the particular chunk of
 138          * memory. When used with a store, it unlocks. The rule is
 139          * that locked accesses have to be made up of a locked load,
 140          * some operation on the data, and then a locked store.
 141          */
 142         LOCKED_RMW                  = 0x00100000,
 143         /** The request is a Load locked/store conditional. */
 144         LLSC                        = 0x00200000,
 145         /** This request is for a memory swap. */
 146         MEM_SWAP                    = 0x00400000,
 147         MEM_SWAP_COND               = 0x00800000,
 148
 149         /** The request is a prefetch. */
 150         PREFETCH                    = 0x01000000,
 151         /** The request should be prefetched into the exclusive state. */
 152         PF_EXCLUSIVE                = 0x02000000,
 153         /** The request should be marked as LRU. */
 154         EVICT_NEXT                  = 0x04000000,
 155         /** The request should be marked with ACQUIRE. */
 156         ACQUIRE                     = 0x00020000,
 157         /** The request should be marked with RELEASE. */
 158         RELEASE                     = 0x00040000,
 159
 160         /** The request is an atomic that returns data. */
 161         ATOMIC_RETURN_OP            = 0x40000000,
 162         /** The request is an atomic that does not return data. */
 163         ATOMIC_NO_RETURN_OP         = 0x80000000,
 164
 165         /** The request should be marked with KERNEL.
 166           * Used to indicate the synchronization associated with a GPU kernel
 167           * launch or completion.
 168           */
 169         KERNEL                      = 0x00001000,
 170
 171         /** The request targets the secure memory space. */
 172         SECURE                      = 0x10000000,
 173         /** The request is a page table walk */
 174         PT_WALK                     = 0x20000000,
 175
 176         /** The request invalidates a memory location */
 177         INVALIDATE                  = 0x0000000100000000,
 178         /** The request cleans a memory location */
 179         CLEAN                       = 0x0000000200000000,
 180
 181         /** The request targets the point of unification */
 182         DST_POU                     = 0x0000001000000000,
 183
 184         /** The request targets the point of coherence */
 185         DST_POC                     = 0x0000002000000000,
 186
 187         /** Bits to define the destination of a request */
 188         DST_BITS                    = 0x0000003000000000,
 189
 190         /**
 191          * These flags are *not* cleared when a Request object is
 192          * reused (assigned a new address).
 193          */
 194         STICKY_FLAGS = INST_FETCH
 195     };
 196     static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
 197         CLEAN | INVALIDATE;
 198
 199     /** Master Ids that are statically allocated
 200      * @{*/
 201     enum : MasterID {
 202         /** This master id is used for writeback requests by the caches */
 203         wbMasterId = 0,
 204         /**
 205          * This master id is used for functional requests that
 206          * don't come from a particular device
 207          */
 208         funcMasterId = 1,
 209         /** This master id is used for message signaled interrupts */
 210         intMasterId = 2,
 211         /**
 212          * Invalid master id for assertion checking only. It is
 213          * invalid behavior to ever send this id as part of a request.
 214          */
 215         invldMasterId = std::numeric_limits<MasterID>::max()
 216     };
 217     /** @} */
 218
 219     typedef uint32_t MemSpaceConfigFlagsType;
 220     typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
 221
 222     enum : MemSpaceConfigFlagsType {
 223         /** Has a synchronization scope been set? */
 224         SCOPE_VALID            = 0x00000001,
 225         /** Access has Wavefront scope visibility */
 226         WAVEFRONT_SCOPE        = 0x00000002,
 227         /** Access has Workgroup scope visibility */
 228         WORKGROUP_SCOPE        = 0x00000004,
 229         /** Access has Device (e.g., GPU) scope visibility */
 230         DEVICE_SCOPE           = 0x00000008,
 231         /** Access has System (e.g., CPU + GPU) scope visibility */
 232         SYSTEM_SCOPE           = 0x00000010,
 233
 234         /** Global Segment */
 235         GLOBAL_SEGMENT         = 0x00000020,
 236         /** Group Segment */
 237         GROUP_SEGMENT          = 0x00000040,
 238         /** Private Segment */
 239         PRIVATE_SEGMENT        = 0x00000080,
 240         /** Kergarg Segment */
 241         KERNARG_SEGMENT        = 0x00000100,
 242         /** Readonly Segment */
 243         READONLY_SEGMENT       = 0x00000200,
 244         /** Spill Segment */
 245         SPILL_SEGMENT          = 0x00000400,
 246         /** Arg Segment */
 247         ARG_SEGMENT            = 0x00000800,
 248     };
 249
 250     using LocalAccessor =
 251         std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
 252
 253   private:
 254     typedef uint16_t PrivateFlagsType;
 255     typedef ::Flags<PrivateFlagsType> PrivateFlags;
 256
 257     enum : PrivateFlagsType {
 258         /** Whether or not the size is valid. */
 259         VALID_SIZE           = 0x00000001,
 260         /** Whether or not paddr is valid (has been written yet). */
 261         VALID_PADDR          = 0x00000002,
 262         /** Whether or not the vaddr is valid. */
 263         VALID_VADDR          = 0x00000004,
 264         /** Whether or not the instruction sequence number is valid. */
 265         VALID_INST_SEQ_NUM   = 0x00000008,
 266         /** Whether or not the pc is valid. */
 267         VALID_PC             = 0x00000010,
 268         /** Whether or not the context ID is valid. */
 269         VALID_CONTEXT_ID     = 0x00000020,
 270         /** Whether or not the sc result is valid. */
 271         VALID_EXTRA_DATA     = 0x00000080,
 272         /** Whether or not the stream ID and substream ID is valid. */
 273         VALID_STREAM_ID      = 0x00000100,
 274         VALID_SUBSTREAM_ID   = 0x00000200,
 275         /**
 276          * These flags are *not* cleared when a Request object is reused
 277          * (assigned a new address).
 278          */
 279         STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
 280     };
 281
 282   private:
 283
 284     /**
 285      * The physical address of the request. Valid only if validPaddr
 286      * is set.
 287      */
 288     Addr _paddr = 0;
 289
 290     /**
 291      * The size of the request. This field must be set when vaddr or
 292      * paddr is written via setVirt() or a phys basec constructor, so it is
 293      * always valid as long as one of the address fields is valid.
 294      */
 295     unsigned _size = 0;
 296
 297     /** Byte-enable mask for writes. */
 298     std::vector<bool> _byteEnable;
 299
 300     /** The requestor ID which is unique in the system for all ports
 301      * that are capable of issuing a transaction
 302      */
 303     MasterID _masterId = invldMasterId;
 304
 305     /** Flag structure for the request. */
 306     Flags _flags;
 307
 308     /** Memory space configuraiton flag structure for the request. */
 309     MemSpaceConfigFlags _memSpaceConfigFlags;
 310
 311     /** Private flags for field validity checking. */
 312     PrivateFlags privateFlags;
 313
 314     /**
 315      * The time this request was started. Used to calculate
 316      * latencies. This field is set to curTick() any time paddr or vaddr
 317      * is written.
 318      */
 319     Tick _time = MaxTick;
 320
 321     /**
 322      * The task id associated with this request
 323      */
 324     uint32_t _taskId = ContextSwitchTaskId::Unknown;
 325
 326     /**
 327      * The stream ID uniquely identifies a device behind the
 328      * SMMU/IOMMU Each transaction arriving at the SMMU/IOMMU is
 329      * associated with exactly one stream ID.
 330      */
 331     uint32_t _streamId = 0;
 332
 333     /**
 334      * The substream ID identifies an "execution context" within a
 335      * device behind an SMMU/IOMMU. It's intended to map 1-to-1 to
 336      * PCIe PASID (Process Address Space ID). The presence of a
 337      * substream ID is optional.
 338      */
 339     uint32_t _substreamId = 0;
 340
 341     /** The virtual address of the request. */
 342     Addr _vaddr = MaxAddr;
 343
 344     /**
 345      * Extra data for the request, such as the return value of
 346      * store conditional or the compare value for a CAS. */
 347     uint64_t _extraData = 0;
 348
 349     /** The context ID (for statistics, locks, and wakeups). */
 350     ContextID _contextId = InvalidContextID;
 351
 352     /** program counter of initiating access; for tracing/debugging */
 353     Addr _pc = MaxAddr;
 354
 355     /** Sequence number of the instruction that creates the request */
 356     InstSeqNum _reqInstSeqNum = 0;
 357
 358     /** A pointer to an atomic operation */
 359     AtomicOpFunctorPtr atomicOpFunctor = nullptr;
 360
 361     LocalAccessor _localAccessor;
 362
 363   public:
 364
 365     /**
 366      * Minimal constructor. No fields are initialized. (Note that
 367      *  _flags and privateFlags are cleared by Flags default
 368      *  constructor.)
 369      */
 370     Request() {}
 371
 372     /**
 373      * Constructor for physical (e.g. device) requests.  Initializes
 374      * just physical address, size, flags, and timestamp (to curTick()).
 375      * These fields are adequate to perform a request.
 376      */
 377     Request(Addr paddr, unsigned size, Flags flags, MasterID mid) :
 378         _paddr(paddr), _size(size), _masterId(mid), _time(curTick())
 379     {
 380         _flags.set(flags);
 381         privateFlags.set(VALID_PADDR|VALID_SIZE);
 382     }
 383
 384     Request(Addr vaddr, unsigned size, Flags flags,
 385             MasterID mid, Addr pc, ContextID cid,
 386             AtomicOpFunctorPtr atomic_op=nullptr)
 387     {
 388         setVirt(vaddr, size, flags, mid, pc, std::move(atomic_op));
 389         setContext(cid);
 390     }
 391
 392     Request(const Request& other)
 393         : _paddr(other._paddr), _size(other._size),
 394           _byteEnable(other._byteEnable),
 395           _masterId(other._masterId),
 396           _flags(other._flags),
 397           _memSpaceConfigFlags(other._memSpaceConfigFlags),
 398           privateFlags(other.privateFlags),
 399           _time(other._time),
 400           _taskId(other._taskId), _vaddr(other._vaddr),
 401           _extraData(other._extraData), _contextId(other._contextId),
 402           _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
 403           _localAccessor(other._localAccessor),
 404           translateDelta(other.translateDelta),
 405           accessDelta(other.accessDelta), depth(other.depth)
 406     {
 407         atomicOpFunctor.reset(other.atomicOpFunctor ?
 408                                 other.atomicOpFunctor->clone() : nullptr);
 409     }
 410
 411     ~Request() {}
 412
 413     /**
 414      * Set up Context numbers.
 415      */
 416     void
 417     setContext(ContextID context_id)
 418     {
 419         _contextId = context_id;
 420         privateFlags.set(VALID_CONTEXT_ID);
 421     }
 422
 423     void
 424     setStreamId(uint32_t sid)
 425     {
 426         _streamId = sid;
 427         privateFlags.set(VALID_STREAM_ID);
 428     }
 429
 430     void
 431     setSubStreamId(uint32_t ssid)
 432     {
 433         assert(privateFlags.isSet(VALID_STREAM_ID));
 434         _substreamId = ssid;
 435         privateFlags.set(VALID_SUBSTREAM_ID);
 436     }
 437
 438     /**
 439      * Set up a virtual (e.g., CPU) request in a previously
 440      * allocated Request object.
 441      */
 442     void
 443     setVirt(Addr vaddr, unsigned size, Flags flags, MasterID mid, Addr pc,
 444             AtomicOpFunctorPtr amo_op=nullptr)
 445     {
 446         _vaddr = vaddr;
 447         _size = size;
 448         _masterId = mid;
 449         _pc = pc;
 450         _time = curTick();
 451
 452         _flags.clear(~STICKY_FLAGS);
 453         _flags.set(flags);
 454         privateFlags.clear(~STICKY_PRIVATE_FLAGS);
 455         privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
 456         depth = 0;
 457         accessDelta = 0;
 458         translateDelta = 0;
 459         atomicOpFunctor = std::move(amo_op);
 460         _localAccessor = nullptr;
 461     }
 462
 463     /**
 464      * Set just the physical address. This usually used to record the
 465      * result of a translation.
 466      */
 467     void
 468     setPaddr(Addr paddr)
 469     {
 470         _paddr = paddr;
 471         privateFlags.set(VALID_PADDR);
 472     }
 473
 474     /**
 475      * Generate two requests as if this request had been split into two
 476      * pieces. The original request can't have been translated already.
 477      */
 478     // TODO: this function is still required by TimingSimpleCPU - should be
 479     // removed once TimingSimpleCPU will support arbitrarily long multi-line
 480     // mem. accesses
 481     void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
 482     {
 483         assert(privateFlags.isSet(VALID_VADDR));
 484         assert(privateFlags.noneSet(VALID_PADDR));
 485         assert(split_addr > _vaddr && split_addr < _vaddr + _size);
 486         req1 = std::make_shared<Request>(*this);
 487         req2 = std::make_shared<Request>(*this);
 488         req1->_size = split_addr - _vaddr;
 489         req2->_vaddr = split_addr;
 490         req2->_size = _size - req1->_size;
 491         if (!_byteEnable.empty()) {
 492             req1->_byteEnable = std::vector<bool>(
 493                 _byteEnable.begin(),
 494                 _byteEnable.begin() + req1->_size);
 495             req2->_byteEnable = std::vector<bool>(
 496                 _byteEnable.begin() + req1->_size,
 497                 _byteEnable.end());
 498         }
 499     }
 500
 501     /**
 502      * Accessor for paddr.
 503      */
 504     bool
 505     hasPaddr() const
 506     {
 507         return privateFlags.isSet(VALID_PADDR);
 508     }
 509
 510     Addr
 511     getPaddr() const
 512     {
 513         assert(privateFlags.isSet(VALID_PADDR));
 514         return _paddr;
 515     }
 516
 517     /**
 518      * Time for the TLB/table walker to successfully translate this request.
 519      */
 520     Tick translateDelta = 0;
 521
 522     /**
 523      * Access latency to complete this memory transaction not including
 524      * translation time.
 525      */
 526     Tick accessDelta = 0;
 527
 528     /**
 529      * Level of the cache hierachy where this request was responded to
 530      * (e.g. 0 = L1; 1 = L2).
 531      */
 532     mutable int depth = 0;
 533
 534     /**
 535      *  Accessor for size.
 536      */
 537     bool
 538     hasSize() const
 539     {
 540         return privateFlags.isSet(VALID_SIZE);
 541     }
 542
 543     unsigned
 544     getSize() const
 545     {
 546         assert(privateFlags.isSet(VALID_SIZE));
 547         return _size;
 548     }
 549
 550     const std::vector<bool>&
 551     getByteEnable() const
 552     {
 553         return _byteEnable;
 554     }
 555
 556     void
 557     setByteEnable(const std::vector<bool>& be)
 558     {
 559         assert(be.empty() || be.size() == _size);
 560         _byteEnable = be;
 561     }
 562
 563     /**
 564      * Returns true if the memory request is masked, which means
 565      * there is at least one byteEnable element which is false
 566      * (byte is masked)
 567      */
 568     bool
 569     isMasked() const
 570     {
 571         return std::find(
 572             _byteEnable.begin(),
 573             _byteEnable.end(),
 574             false) != _byteEnable.end();
 575     }
 576
 577     /** Accessor for time. */
 578     Tick
 579     time() const
 580     {
 581         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 582         return _time;
 583     }
 584
 585     /** Is this request for a local memory mapped resource/register? */
 586     bool isLocalAccess() { return (bool)_localAccessor; }
 587     /** Set the function which will enact that access. */
 588     void setLocalAccessor(LocalAccessor acc) { _localAccessor = acc; }
 589     /** Perform the installed local access. */
 590     Cycles
 591     localAccessor(ThreadContext *tc, Packet *pkt)
 592     {
 593         return _localAccessor(tc, pkt);
 594     }
 595
 596     /**
 597      * Accessor for atomic-op functor.
 598      */
 599     bool
 600     hasAtomicOpFunctor()
 601     {
 602         return (bool)atomicOpFunctor;
 603     }
 604
 605     AtomicOpFunctor *
 606     getAtomicOpFunctor()
 607     {
 608         assert(atomicOpFunctor);
 609         return atomicOpFunctor.get();
 610     }
 611
 612     /** Accessor for flags. */
 613     Flags
 614     getFlags()
 615     {
 616         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 617         return _flags;
 618     }
 619
 620     /** Note that unlike other accessors, this function sets *specific
 621         flags* (ORs them in); it does not assign its argument to the
 622         _flags field.  Thus this method should rightly be called
 623         setFlags() and not just flags(). */
 624     void
 625     setFlags(Flags flags)
 626     {
 627         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 628         _flags.set(flags);
 629     }
 630
 631     void
 632     setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
 633     {
 634         assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
 635         _memSpaceConfigFlags.set(extraFlags);
 636     }
 637
 638     /** Accessor function for vaddr.*/
 639     bool
 640     hasVaddr() const
 641     {
 642         return privateFlags.isSet(VALID_VADDR);
 643     }
 644
 645     Addr
 646     getVaddr() const
 647     {
 648         assert(privateFlags.isSet(VALID_VADDR));
 649         return _vaddr;
 650     }
 651
 652     /** Accesssor for the requestor id. */
 653     MasterID
 654     masterId() const
 655     {
 656         return _masterId;
 657     }
 658
 659     uint32_t
 660     taskId() const
 661     {
 662         return _taskId;
 663     }
 664
 665     void
 666     taskId(uint32_t id) {
 667         _taskId = id;
 668     }
 669
 670     /** Accessor function for architecture-specific flags.*/
 671     ArchFlagsType
 672     getArchFlags() const
 673     {
 674         assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 675         return _flags & ARCH_BITS;
 676     }
 677
 678     /** Accessor function to check if sc result is valid. */
 679     bool
 680     extraDataValid() const
 681     {
 682         return privateFlags.isSet(VALID_EXTRA_DATA);
 683     }
 684
 685     /** Accessor function for store conditional return value.*/
 686     uint64_t
 687     getExtraData() const
 688     {
 689         assert(privateFlags.isSet(VALID_EXTRA_DATA));
 690         return _extraData;
 691     }
 692
 693     /** Accessor function for store conditional return value.*/
 694     void
 695     setExtraData(uint64_t extraData)
 696     {
 697         _extraData = extraData;
 698         privateFlags.set(VALID_EXTRA_DATA);
 699     }
 700
 701     bool
 702     hasContextId() const
 703     {
 704         return privateFlags.isSet(VALID_CONTEXT_ID);
 705     }
 706
 707     /** Accessor function for context ID.*/
 708     ContextID
 709     contextId() const
 710     {
 711         assert(privateFlags.isSet(VALID_CONTEXT_ID));
 712         return _contextId;
 713     }
 714
 715     uint32_t
 716     streamId() const
 717     {
 718         assert(privateFlags.isSet(VALID_STREAM_ID));
 719         return _streamId;
 720     }
 721
 722     bool
 723     hasSubstreamId() const
 724     {
 725         return privateFlags.isSet(VALID_SUBSTREAM_ID);
 726     }
 727
 728     uint32_t
 729     substreamId() const
 730     {
 731         assert(privateFlags.isSet(VALID_SUBSTREAM_ID));
 732         return _substreamId;
 733     }
 734
 735     void
 736     setPC(Addr pc)
 737     {
 738         privateFlags.set(VALID_PC);
 739         _pc = pc;
 740     }
 741
 742     bool
 743     hasPC() const
 744     {
 745         return privateFlags.isSet(VALID_PC);
 746     }
 747
 748     /** Accessor function for pc.*/
 749     Addr
 750     getPC() const
 751     {
 752         assert(privateFlags.isSet(VALID_PC));
 753         return _pc;
 754     }
 755
 756     /**
 757      * Increment/Get the depth at which this request is responded to.
 758      * This currently happens when the request misses in any cache level.
 759      */
 760     void incAccessDepth() const { depth++; }
 761     int getAccessDepth() const { return depth; }
 762
 763     /**
 764      * Set/Get the time taken for this request to be successfully translated.
 765      */
 766     void setTranslateLatency() { translateDelta = curTick() - _time; }
 767     Tick getTranslateLatency() const { return translateDelta; }
 768
 769     /**
 770      * Set/Get the time taken to complete this request's access, not including
 771      *  the time to successfully translate the request.
 772      */
 773     void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
 774     Tick getAccessLatency() const { return accessDelta; }
 775
 776     /**
 777      * Accessor for the sequence number of instruction that creates the
 778      * request.
 779      */
 780     bool
 781     hasInstSeqNum() const
 782     {
 783         return privateFlags.isSet(VALID_INST_SEQ_NUM);
 784     }
 785
 786     InstSeqNum
 787     getReqInstSeqNum() const
 788     {
 789         assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
 790         return _reqInstSeqNum;
 791     }
 792
 793     void
 794     setReqInstSeqNum(const InstSeqNum seq_num)
 795     {
 796         privateFlags.set(VALID_INST_SEQ_NUM);
 797         _reqInstSeqNum = seq_num;
 798     }
 799
 800     /** Accessor functions for flags. Note that these are for testing
 801         only; setting flags should be done via setFlags(). */
 802     bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
 803     bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
 804     bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
 805     bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
 806                                       _flags.isSet(PF_EXCLUSIVE)); }
 807     bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
 808     bool isLLSC() const { return _flags.isSet(LLSC); }
 809     bool isPriv() const { return _flags.isSet(PRIVILEGED); }
 810     bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
 811     bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
 812     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
 813     bool isSecure() const { return _flags.isSet(SECURE); }
 814     bool isPTWalk() const { return _flags.isSet(PT_WALK); }
 815     bool isAcquire() const { return _flags.isSet(ACQUIRE); }
 816     bool isRelease() const { return _flags.isSet(RELEASE); }
 817     bool isKernel() const { return _flags.isSet(KERNEL); }
 818     bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
 819     bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
 820
 821     bool
 822     isAtomic() const
 823     {
 824         return _flags.isSet(ATOMIC_RETURN_OP) ||
 825                _flags.isSet(ATOMIC_NO_RETURN_OP);
 826     }
 827
 828     /**
 829      * Accessor functions for the destination of a memory request. The
 830      * destination flag can specify a point of reference for the
 831      * operation (e.g. a cache block clean to the the point of
 832      * unification). At the moment the destination is only used by the
 833      * cache maintenance operations.
 834      */
 835     bool isToPOU() const { return _flags.isSet(DST_POU); }
 836     bool isToPOC() const { return _flags.isSet(DST_POC); }
 837     Flags getDest() const { return _flags & DST_BITS; }
 838
 839     /**
 840      * Accessor functions for the memory space configuration flags and used by
 841      * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
 842      * these are for testing only; setting extraFlags should be done via
 843      * setMemSpaceConfigFlags().
 844      */
 845     bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
 846
 847     bool
 848     isWavefrontScope() const
 849     {
 850         assert(isScoped());
 851         return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
 852     }
 853
 854     bool
 855     isWorkgroupScope() const
 856     {
 857         assert(isScoped());
 858         return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
 859     }
 860
 861     bool
 862     isDeviceScope() const
 863     {
 864         assert(isScoped());
 865         return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
 866     }
 867
 868     bool
 869     isSystemScope() const
 870     {
 871         assert(isScoped());
 872         return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
 873     }
 874
 875     bool
 876     isGlobalSegment() const
 877     {
 878         return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
 879                (!isGroupSegment() && !isPrivateSegment() &&
 880                 !isKernargSegment() && !isReadonlySegment() &&
 881                 !isSpillSegment() && !isArgSegment());
 882     }
 883
 884     bool
 885     isGroupSegment() const
 886     {
 887         return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
 888     }
 889
 890     bool
 891     isPrivateSegment() const
 892     {
 893         return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
 894     }
 895
 896     bool
 897     isKernargSegment() const
 898     {
 899         return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
 900     }
 901
 902     bool
 903     isReadonlySegment() const
 904     {
 905         return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
 906     }
 907
 908     bool
 909     isSpillSegment() const
 910     {
 911         return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
 912     }
 913
 914     bool
 915     isArgSegment() const
 916     {
 917         return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
 918     }
 919
 920     /**
 921      * Accessor functions to determine whether this request is part of
 922      * a cache maintenance operation. At the moment three operations
 923      * are supported:
 924
 925      * 1) A cache clean operation updates all copies of a memory
 926      * location to the point of reference,
 927      * 2) A cache invalidate operation invalidates all copies of the
 928      * specified block in the memory above the point of reference,
 929      * 3) A clean and invalidate operation is a combination of the two
 930      * operations.
 931      * @{ */
 932     bool isCacheClean() const { return _flags.isSet(CLEAN); }
 933     bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
 934     bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
 935     /** @} */
 936 };
 937
 938 #endif // __MEM_REQUEST_HH__