3 # Creates a homogeneous CMP system with a single unified cache per
4 # core and a crossbar network. Uses the default parameters listed
5 # below, which can be overridden if a wrapper script sets the hash
22 protocol
= "MI_example"
27 for i
in 0..$
*.size-1
do
32 num_cores
= $
*[i
+1].to_i
35 num_memories
= $
*[i
+1].to_i
39 RubySystem
.random_seed
= "rand"
41 RubySystem
.random_seed
= $
*[i
+1].to_i
45 memory_size_mb
= $
*[i
+1].to_i
51 iface_ports
= Array
.new
53 assert(protocol
== "MI_example", __FILE__
+ " cannot be used with protocol " + protocol
)
55 require protocol
+".rb"
58 cache
= SetAssociativeCache
.new("l1u_"+n
.to_s
, l1_cache_size_kb
, l1_cache_latency
, l1_cache_assoc
, "PSEUDO_LRU")
59 sequencer
= Sequencer
.new("Sequencer_"+n
.to_s
, cache
, cache
)
60 iface_ports
<< sequencer
61 net_ports
<< MI_example_CacheController
.new("L1CacheController_"+n
.to_s
,
66 num_memories
.times
{ |n
|
67 directory
= DirectoryMemory
.new("DirectoryMemory_"+n
.to_s
, memory_size_mb
/num_memories
)
68 memory_control
= MemoryControl
.new("MemoryControl_"+n
.to_s
)
69 net_ports
<< MI_example_DirectoryController
.new("DirectoryController_"+n
.to_s
,
71 directory
, memory_control
)
74 dma_sequencer
= DMASequencer
.new("DMASequencer_"+n
.to_s
)
75 iface_ports
<< dma_sequencer
76 net_ports
<< MI_example_DMAController
.new("DMAController_"+n
.to_s
, "DMA", dma_sequencer
)
79 topology
= CrossbarTopology
.new("theTopology", net_ports
)
80 on_chip_net
= Network
.new("theNetwork", topology
)
82 RubySystem
.init(iface_ports
, on_chip_net
)