8c2eef0091525a5cbaadad97b9b75f5c7233e070
[gem5.git] / src / mem / ruby / config / MI_example-homogeneous.rb
1 #!/usr/bin/ruby
2 #
3 # Creates a homogeneous CMP system with a single unified cache per
4 # core and a crossbar network. Uses the default parameters listed
5 # below, which can be overridden if a wrapper script sets the hash
6 # libruby_args.
7 #
8
9 require "cfg.rb"
10
11 # default values
12
13 num_cores = 16
14 L1_CACHE_SIZE_KB = 32
15 L1_CACHE_ASSOC = 8
16 L1_CACHE_LATENCY = "auto"
17 num_memories = 2
18 memory_size_mb = 1024
19 NUM_DMA = 1
20
21 # check for overrides
22
23 for i in 0..$*.size-1 do
24 if $*[i] == "-p"
25 num_cores = $*[i+1].to_i
26 i = i+1
27 elsif $*[i] == "-m"
28 num_memories = $*[i+1].to_i
29 i = i+1
30 elsif $*[i] == "-s"
31 memory_size_mb = $*[i+1].to_i
32 i = i + 1
33 end
34 end
35
36 net_ports = Array.new
37 iface_ports = Array.new
38
39 num_cores.times { |n|
40 cache = SetAssociativeCache.new("l1u_"+n.to_s, L1_CACHE_SIZE_KB, L1_CACHE_LATENCY, L1_CACHE_ASSOC, "PSEUDO_LRU")
41 sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache)
42 iface_ports << sequencer
43 net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s,
44 "L1Cache",
45 [cache],
46 sequencer)
47 }
48 num_memories.times { |n|
49 directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
50 memory_control = MemoryControl.new("MemoryControl_"+n.to_s)
51 net_ports << MI_example_DirectoryController.new("DirectoryController_"+n.to_s,
52 "Directory",
53 directory, memory_control)
54 }
55 NUM_DMA.times { |n|
56 dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
57 iface_ports << dma_sequencer
58 net_ports << DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer)
59 }
60
61 topology = CrossbarTopology.new("theTopology", net_ports)
62 on_chip_net = Network.new("theNetwork", topology)
63
64 RubySystem.init(iface_ports, on_chip_net)